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agp/intel: fix cache control for sandybridge
author
Zhenyu Wang
<zhenyuw@linux.intel.com>
Tue, 2 Nov 2010 09:30:46 +0000
(17:30 +0800)
committer
Chris Wilson
<chris@chris-wilson.co.uk>
Tue, 2 Nov 2010 10:05:46 +0000
(10:05 +0000)
This is broken from
97ef1bdd0bc75bce7b2058e9c432b6c277dcf4d3
.
Let's set the correct bit for LLC+MLC and LLC only.
Signed-off-by: Zhenyu Wang <zhenyuw@linux.intel.com>
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
drivers/char/agp/intel-gtt.c
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diff --git
a/drivers/char/agp/intel-gtt.c
b/drivers/char/agp/intel-gtt.c
index f800e9cfc3684b5a611260d65d2df30b3d712ba5..c51efe6f2c7fcad354b8540f9911d52986f10ac4 100644
(file)
--- a/
drivers/char/agp/intel-gtt.c
+++ b/
drivers/char/agp/intel-gtt.c
@@
-1291,11
+1291,11
@@
static void gen6_write_entry(dma_addr_t addr, unsigned int entry,
if (type_mask == AGP_USER_UNCACHED_MEMORY)
pte_flags = GEN6_PTE_UNCACHED | I810_PTE_VALID;
else if (type_mask == AGP_USER_CACHED_MEMORY_LLC_MLC) {
- pte_flags = GEN6_PTE_LLC | I810_PTE_VALID;
+ pte_flags = GEN6_PTE_LLC
_MLC
| I810_PTE_VALID;
if (gfdt)
pte_flags |= GEN6_PTE_GFDT;
} else { /* set 'normal'/'cached' to LLC by default */
- pte_flags = GEN6_PTE_LLC
_MLC
| I810_PTE_VALID;
+ pte_flags = GEN6_PTE_LLC | I810_PTE_VALID;
if (gfdt)
pte_flags |= GEN6_PTE_GFDT;
}