pinctrl: sunxi: Replace hardcoded pin defines by a macro

We previously had an evergrowing (and exhaustive) list of the pins that could
be used on any Allwinner SoCs. These defines were then used by each pinctrl
driver to declare the list of functions for this pin. Since it's pretty much
all boilerplate, we can remove it just by a single macro.

Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>

diff --git a/drivers/pinctrl/sunxi/pinctrl-sunxi-pins.h b/drivers/pinctrl/sunxi/pinctrl-sunxi-pins.h
index 51100ca..e1ea6d8 100644 (file)
--- a/drivers/pinctrl/sunxi/pinctrl-sunxi-pins.h
+++ b/drivers/pinctrl/sunxi/pinctrl-sunxi-pins.h
@@ -16,637 +16,637 @@
 #include "pinctrl-sunxi.h"
 
 static const struct sunxi_desc_pin sun4i_a10_pins[] = {
-       SUNXI_PIN(SUNXI_PINCTRL_PIN_PA0,
+       SUNXI_PIN(SUNXI_PINCTRL_PIN(A, 0),
                  SUNXI_FUNCTION(0x0, "gpio_in"),
                  SUNXI_FUNCTION(0x1, "gpio_out"),
                  SUNXI_FUNCTION(0x2, "emac"),          /* ERXD3 */
                  SUNXI_FUNCTION(0x3, "spi1"),          /* CS0 */
                  SUNXI_FUNCTION(0x4, "uart2")),        /* RTS */
-       SUNXI_PIN(SUNXI_PINCTRL_PIN_PA1,
+       SUNXI_PIN(SUNXI_PINCTRL_PIN(A, 1),
                  SUNXI_FUNCTION(0x0, "gpio_in"),
                  SUNXI_FUNCTION(0x1, "gpio_out"),
                  SUNXI_FUNCTION(0x2, "emac"),          /* ERXD2 */
                  SUNXI_FUNCTION(0x3, "spi1"),          /* CLK */
                  SUNXI_FUNCTION(0x4, "uart2")),        /* CTS */
-       SUNXI_PIN(SUNXI_PINCTRL_PIN_PA2,
+       SUNXI_PIN(SUNXI_PINCTRL_PIN(A, 2),
                  SUNXI_FUNCTION(0x0, "gpio_in"),
                  SUNXI_FUNCTION(0x1, "gpio_out"),
                  SUNXI_FUNCTION(0x2, "emac"),          /* ERXD1 */
                  SUNXI_FUNCTION(0x3, "spi1"),          /* MOSI */
                  SUNXI_FUNCTION(0x4, "uart2")),        /* TX */
-       SUNXI_PIN(SUNXI_PINCTRL_PIN_PA3,
+       SUNXI_PIN(SUNXI_PINCTRL_PIN(A, 3),
                  SUNXI_FUNCTION(0x0, "gpio_in"),
                  SUNXI_FUNCTION(0x1, "gpio_out"),
                  SUNXI_FUNCTION(0x2, "emac"),          /* ERXD0 */
                  SUNXI_FUNCTION(0x3, "spi1"),          /* MISO */
                  SUNXI_FUNCTION(0x4, "uart2")),        /* RX */
-       SUNXI_PIN(SUNXI_PINCTRL_PIN_PA4,
+       SUNXI_PIN(SUNXI_PINCTRL_PIN(A, 4),
                  SUNXI_FUNCTION(0x0, "gpio_in"),
                  SUNXI_FUNCTION(0x1, "gpio_out"),
                  SUNXI_FUNCTION(0x2, "emac"),          /* ETXD3 */
                  SUNXI_FUNCTION(0x3, "spi1")),         /* CS1 */
-       SUNXI_PIN(SUNXI_PINCTRL_PIN_PA5,
+       SUNXI_PIN(SUNXI_PINCTRL_PIN(A, 5),
                  SUNXI_FUNCTION(0x0, "gpio_in"),
                  SUNXI_FUNCTION(0x1, "gpio_out"),
                  SUNXI_FUNCTION(0x2, "emac"),          /* ETXD2 */
                  SUNXI_FUNCTION(0x3, "spi3")),         /* CS0 */
-       SUNXI_PIN(SUNXI_PINCTRL_PIN_PA6,
+       SUNXI_PIN(SUNXI_PINCTRL_PIN(A, 6),
                  SUNXI_FUNCTION(0x0, "gpio_in"),
                  SUNXI_FUNCTION(0x1, "gpio_out"),
                  SUNXI_FUNCTION(0x2, "emac"),          /* ETXD1 */
                  SUNXI_FUNCTION(0x3, "spi3")),         /* CLK */
-       SUNXI_PIN(SUNXI_PINCTRL_PIN_PA7,
+       SUNXI_PIN(SUNXI_PINCTRL_PIN(A, 7),
                  SUNXI_FUNCTION(0x0, "gpio_in"),
                  SUNXI_FUNCTION(0x1, "gpio_out"),
                  SUNXI_FUNCTION(0x2, "emac"),          /* ETXD0 */
                  SUNXI_FUNCTION(0x3, "spi3")),         /* MOSI */
-       SUNXI_PIN(SUNXI_PINCTRL_PIN_PA8,
+       SUNXI_PIN(SUNXI_PINCTRL_PIN(A, 8),
                  SUNXI_FUNCTION(0x0, "gpio_in"),
                  SUNXI_FUNCTION(0x1, "gpio_out"),
                  SUNXI_FUNCTION(0x2, "emac"),          /* ERXCK */
                  SUNXI_FUNCTION(0x3, "spi3")),         /* MISO */
-       SUNXI_PIN(SUNXI_PINCTRL_PIN_PA9,
+       SUNXI_PIN(SUNXI_PINCTRL_PIN(A, 9),
                  SUNXI_FUNCTION(0x0, "gpio_in"),
                  SUNXI_FUNCTION(0x1, "gpio_out"),
                  SUNXI_FUNCTION(0x2, "emac"),          /* ERXERR */
                  SUNXI_FUNCTION(0x3, "spi3")),         /* CS1 */
-       SUNXI_PIN(SUNXI_PINCTRL_PIN_PA10,
+       SUNXI_PIN(SUNXI_PINCTRL_PIN(A, 10),
                  SUNXI_FUNCTION(0x0, "gpio_in"),
                  SUNXI_FUNCTION(0x1, "gpio_out"),
                  SUNXI_FUNCTION(0x2, "emac"),          /* ERXDV */
                  SUNXI_FUNCTION(0x4, "uart1")),        /* TX */
-       SUNXI_PIN(SUNXI_PINCTRL_PIN_PA11,
+       SUNXI_PIN(SUNXI_PINCTRL_PIN(A, 11),
                  SUNXI_FUNCTION(0x0, "gpio_in"),
                  SUNXI_FUNCTION(0x1, "gpio_out"),
                  SUNXI_FUNCTION(0x2, "emac"),          /* EMDC */
                  SUNXI_FUNCTION(0x4, "uart1")),        /* RX */
-       SUNXI_PIN(SUNXI_PINCTRL_PIN_PA12,
+       SUNXI_PIN(SUNXI_PINCTRL_PIN(A, 12),
                  SUNXI_FUNCTION(0x0, "gpio_in"),
                  SUNXI_FUNCTION(0x1, "gpio_out"),
                  SUNXI_FUNCTION(0x2, "emac"),          /* EMDIO */
                  SUNXI_FUNCTION(0x3, "uart6"),         /* TX */
                  SUNXI_FUNCTION(0x4, "uart1")),        /* RTS */
-       SUNXI_PIN(SUNXI_PINCTRL_PIN_PA13,
+       SUNXI_PIN(SUNXI_PINCTRL_PIN(A, 13),
                  SUNXI_FUNCTION(0x0, "gpio_in"),
                  SUNXI_FUNCTION(0x1, "gpio_out"),
                  SUNXI_FUNCTION(0x2, "emac"),          /* ETXEN */
                  SUNXI_FUNCTION(0x3, "uart6"),         /* RX */
                  SUNXI_FUNCTION(0x4, "uart1")),        /* CTS */
-       SUNXI_PIN(SUNXI_PINCTRL_PIN_PA14,
+       SUNXI_PIN(SUNXI_PINCTRL_PIN(A, 14),
                  SUNXI_FUNCTION(0x0, "gpio_in"),
                  SUNXI_FUNCTION(0x1, "gpio_out"),
                  SUNXI_FUNCTION(0x2, "emac"),          /* ETXCK */
                  SUNXI_FUNCTION(0x3, "uart7"),         /* TX */
                  SUNXI_FUNCTION(0x4, "uart1")),        /* DTR */
-       SUNXI_PIN(SUNXI_PINCTRL_PIN_PA15,
+       SUNXI_PIN(SUNXI_PINCTRL_PIN(A, 15),
                  SUNXI_FUNCTION(0x0, "gpio_in"),
                  SUNXI_FUNCTION(0x1, "gpio_out"),
                  SUNXI_FUNCTION(0x2, "emac"),          /* ECRS */
                  SUNXI_FUNCTION(0x3, "uart7"),         /* RX */
                  SUNXI_FUNCTION(0x4, "uart1")),        /* DSR */
-       SUNXI_PIN(SUNXI_PINCTRL_PIN_PA16,
+       SUNXI_PIN(SUNXI_PINCTRL_PIN(A, 16),
                  SUNXI_FUNCTION(0x0, "gpio_in"),
                  SUNXI_FUNCTION(0x1, "gpio_out"),
                  SUNXI_FUNCTION(0x2, "emac"),          /* ECOL */
                  SUNXI_FUNCTION(0x3, "can"),           /* TX */
                  SUNXI_FUNCTION(0x4, "uart1")),        /* DCD */
-       SUNXI_PIN(SUNXI_PINCTRL_PIN_PA17,
+       SUNXI_PIN(SUNXI_PINCTRL_PIN(A, 17),
                  SUNXI_FUNCTION(0x0, "gpio_in"),
                  SUNXI_FUNCTION(0x1, "gpio_out"),
                  SUNXI_FUNCTION(0x2, "emac"),          /* ETXERR */
                  SUNXI_FUNCTION(0x3, "can"),           /* RX */
                  SUNXI_FUNCTION(0x4, "uart1")),        /* RING */
        /* Hole */
-       SUNXI_PIN(SUNXI_PINCTRL_PIN_PB0,
+       SUNXI_PIN(SUNXI_PINCTRL_PIN(B, 0),
                  SUNXI_FUNCTION(0x0, "gpio_in"),
                  SUNXI_FUNCTION(0x1, "gpio_out"),
                  SUNXI_FUNCTION(0x2, "i2c0")),         /* SCK */
-       SUNXI_PIN(SUNXI_PINCTRL_PIN_PB1,
+       SUNXI_PIN(SUNXI_PINCTRL_PIN(B, 1),
                  SUNXI_FUNCTION(0x0, "gpio_in"),
                  SUNXI_FUNCTION(0x1, "gpio_out"),
                  SUNXI_FUNCTION(0x2, "i2c0")),         /* SDA */
-       SUNXI_PIN(SUNXI_PINCTRL_PIN_PB2,
+       SUNXI_PIN(SUNXI_PINCTRL_PIN(B, 2),
                  SUNXI_FUNCTION(0x0, "gpio_in"),
                  SUNXI_FUNCTION(0x1, "gpio_out"),
                  SUNXI_FUNCTION(0x2, "pwm")),          /* PWM0 */
-       SUNXI_PIN(SUNXI_PINCTRL_PIN_PB3,
+       SUNXI_PIN(SUNXI_PINCTRL_PIN(B, 3),
                  SUNXI_FUNCTION(0x0, "gpio_in"),
                  SUNXI_FUNCTION(0x1, "gpio_out"),
                  SUNXI_FUNCTION(0x2, "ir0")),          /* TX */
-       SUNXI_PIN(SUNXI_PINCTRL_PIN_PB4,
+       SUNXI_PIN(SUNXI_PINCTRL_PIN(B, 4),
                  SUNXI_FUNCTION(0x0, "gpio_in"),
                  SUNXI_FUNCTION(0x1, "gpio_out"),
                  SUNXI_FUNCTION(0x2, "ir0")),          /* RX */
-       SUNXI_PIN(SUNXI_PINCTRL_PIN_PB5,
+       SUNXI_PIN(SUNXI_PINCTRL_PIN(B, 5),
                  SUNXI_FUNCTION(0x0, "gpio_in"),
                  SUNXI_FUNCTION(0x1, "gpio_out"),
                  SUNXI_FUNCTION(0x2, "i2s"),           /* MCLK */
                  SUNXI_FUNCTION(0x3, "ac97")),         /* MCLK */
-       SUNXI_PIN(SUNXI_PINCTRL_PIN_PB6,
+       SUNXI_PIN(SUNXI_PINCTRL_PIN(B, 6),
                  SUNXI_FUNCTION(0x0, "gpio_in"),
                  SUNXI_FUNCTION(0x1, "gpio_out"),
                  SUNXI_FUNCTION(0x2, "i2s"),           /* BCLK */
                  SUNXI_FUNCTION(0x3, "ac97")),         /* BCLK */
-       SUNXI_PIN(SUNXI_PINCTRL_PIN_PB7,
+       SUNXI_PIN(SUNXI_PINCTRL_PIN(B, 7),
                  SUNXI_FUNCTION(0x0, "gpio_in"),
                  SUNXI_FUNCTION(0x1, "gpio_out"),
                  SUNXI_FUNCTION(0x2, "i2s"),           /* LRCK */
                  SUNXI_FUNCTION(0x3, "ac97")),         /* SYNC */
-       SUNXI_PIN(SUNXI_PINCTRL_PIN_PB8,
+       SUNXI_PIN(SUNXI_PINCTRL_PIN(B, 8),
                  SUNXI_FUNCTION(0x0, "gpio_in"),
                  SUNXI_FUNCTION(0x1, "gpio_out"),
                  SUNXI_FUNCTION(0x2, "i2s"),           /* DO0 */
                  SUNXI_FUNCTION(0x3, "ac97")),         /* DO */
-       SUNXI_PIN(SUNXI_PINCTRL_PIN_PB9,
+       SUNXI_PIN(SUNXI_PINCTRL_PIN(B, 9),
                  SUNXI_FUNCTION(0x0, "gpio_in"),
                  SUNXI_FUNCTION(0x1, "gpio_out"),
                  SUNXI_FUNCTION(0x2, "i2s")),          /* DO1 */
-       SUNXI_PIN(SUNXI_PINCTRL_PIN_PB10,
+       SUNXI_PIN(SUNXI_PINCTRL_PIN(B, 10),
                  SUNXI_FUNCTION(0x0, "gpio_in"),
                  SUNXI_FUNCTION(0x1, "gpio_out"),
                  SUNXI_FUNCTION(0x2, "i2s")),          /* DO2 */
-       SUNXI_PIN(SUNXI_PINCTRL_PIN_PB11,
+       SUNXI_PIN(SUNXI_PINCTRL_PIN(B, 11),
                  SUNXI_FUNCTION(0x0, "gpio_in"),
                  SUNXI_FUNCTION(0x1, "gpio_out"),
                  SUNXI_FUNCTION(0x2, "i2s")),          /* DO3 */
-       SUNXI_PIN(SUNXI_PINCTRL_PIN_PB12,
+       SUNXI_PIN(SUNXI_PINCTRL_PIN(B, 12),
                  SUNXI_FUNCTION(0x0, "gpio_in"),
                  SUNXI_FUNCTION(0x1, "gpio_out"),
                  SUNXI_FUNCTION(0x2, "i2s"),           /* DI */
                  SUNXI_FUNCTION(0x3, "ac97")),         /* DI */
-       SUNXI_PIN(SUNXI_PINCTRL_PIN_PB13,
+       SUNXI_PIN(SUNXI_PINCTRL_PIN(B, 13),
                  SUNXI_FUNCTION(0x0, "gpio_in"),
                  SUNXI_FUNCTION(0x1, "gpio_out"),
                  SUNXI_FUNCTION(0x2, "spi2")),         /* CS1 */
-       SUNXI_PIN(SUNXI_PINCTRL_PIN_PB14,
+       SUNXI_PIN(SUNXI_PINCTRL_PIN(B, 14),
                  SUNXI_FUNCTION(0x0, "gpio_in"),
                  SUNXI_FUNCTION(0x1, "gpio_out"),
                  SUNXI_FUNCTION(0x2, "spi2"),          /* CS0 */
                  SUNXI_FUNCTION(0x3, "jtag")),         /* MS0 */
-       SUNXI_PIN(SUNXI_PINCTRL_PIN_PB15,
+       SUNXI_PIN(SUNXI_PINCTRL_PIN(B, 15),
                  SUNXI_FUNCTION(0x0, "gpio_in"),
                  SUNXI_FUNCTION(0x1, "gpio_out"),
                  SUNXI_FUNCTION(0x2, "spi2"),          /* CLK */
                  SUNXI_FUNCTION(0x3, "jtag")),         /* CK0 */
-       SUNXI_PIN(SUNXI_PINCTRL_PIN_PB16,
+       SUNXI_PIN(SUNXI_PINCTRL_PIN(B, 16),
                  SUNXI_FUNCTION(0x0, "gpio_in"),
                  SUNXI_FUNCTION(0x1, "gpio_out"),
                  SUNXI_FUNCTION(0x2, "spi2"),          /* MOSI */
                  SUNXI_FUNCTION(0x3, "jtag")),         /* DO0 */
-       SUNXI_PIN(SUNXI_PINCTRL_PIN_PB17,
+       SUNXI_PIN(SUNXI_PINCTRL_PIN(B, 17),
                  SUNXI_FUNCTION(0x0, "gpio_in"),
                  SUNXI_FUNCTION(0x1, "gpio_out"),
                  SUNXI_FUNCTION(0x2, "spi2"),          /* MISO */
                  SUNXI_FUNCTION(0x3, "jtag")),         /* DI0 */
-       SUNXI_PIN(SUNXI_PINCTRL_PIN_PB18,
+       SUNXI_PIN(SUNXI_PINCTRL_PIN(B, 18),
                  SUNXI_FUNCTION(0x0, "gpio_in"),
                  SUNXI_FUNCTION(0x1, "gpio_out"),
                  SUNXI_FUNCTION(0x2, "i2c1")),         /* SCK */
-       SUNXI_PIN(SUNXI_PINCTRL_PIN_PB19,
+       SUNXI_PIN(SUNXI_PINCTRL_PIN(B, 19),
                  SUNXI_FUNCTION(0x0, "gpio_in"),
                  SUNXI_FUNCTION(0x1, "gpio_out"),
                  SUNXI_FUNCTION(0x2, "i2c1")),         /* SDA */
-       SUNXI_PIN(SUNXI_PINCTRL_PIN_PB20,
+       SUNXI_PIN(SUNXI_PINCTRL_PIN(B, 20),
                  SUNXI_FUNCTION(0x0, "gpio_in"),
                  SUNXI_FUNCTION(0x1, "gpio_out"),
                  SUNXI_FUNCTION(0x2, "i2c2")),         /* SCK */
-       SUNXI_PIN(SUNXI_PINCTRL_PIN_PB21,
+       SUNXI_PIN(SUNXI_PINCTRL_PIN(B, 21),
                  SUNXI_FUNCTION(0x0, "gpio_in"),
                  SUNXI_FUNCTION(0x1, "gpio_out"),
                  SUNXI_FUNCTION(0x2, "i2c2")),         /* SDA */
-       SUNXI_PIN(SUNXI_PINCTRL_PIN_PB22,
+       SUNXI_PIN(SUNXI_PINCTRL_PIN(B, 22),
                  SUNXI_FUNCTION(0x0, "gpio_in"),
                  SUNXI_FUNCTION(0x1, "gpio_out"),
                  SUNXI_FUNCTION(0x2, "uart0"),         /* TX */
                  SUNXI_FUNCTION(0x3, "ir1")),          /* TX */
-       SUNXI_PIN(SUNXI_PINCTRL_PIN_PB23,
+       SUNXI_PIN(SUNXI_PINCTRL_PIN(B, 23),
                  SUNXI_FUNCTION(0x0, "gpio_in"),
                  SUNXI_FUNCTION(0x1, "gpio_out"),
                  SUNXI_FUNCTION(0x2, "uart0"),         /* RX */
                  SUNXI_FUNCTION(0x3, "ir1")),          /* RX */
        /* Hole */
-       SUNXI_PIN(SUNXI_PINCTRL_PIN_PC0,
+       SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 0),
                  SUNXI_FUNCTION(0x0, "gpio_in"),
                  SUNXI_FUNCTION(0x1, "gpio_out"),
                  SUNXI_FUNCTION(0x2, "nand0"),         /* NWE */
                  SUNXI_FUNCTION(0x3, "spi0")),         /* MOSI */
-       SUNXI_PIN(SUNXI_PINCTRL_PIN_PC1,
+       SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 1),
                  SUNXI_FUNCTION(0x0, "gpio_in"),
                  SUNXI_FUNCTION(0x1, "gpio_out"),
                  SUNXI_FUNCTION(0x2, "nand0"),         /* NALE */
                  SUNXI_FUNCTION(0x3, "spi0")),         /* MISO */
-       SUNXI_PIN(SUNXI_PINCTRL_PIN_PC2,
+       SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 2),
                  SUNXI_FUNCTION(0x0, "gpio_in"),
                  SUNXI_FUNCTION(0x1, "gpio_out"),
                  SUNXI_FUNCTION(0x2, "nand0"),         /* NCLE */
                  SUNXI_FUNCTION(0x3, "spi0")),         /* SCK */
-       SUNXI_PIN(SUNXI_PINCTRL_PIN_PC3,
+       SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 3),
                  SUNXI_FUNCTION(0x0, "gpio_in"),
                  SUNXI_FUNCTION(0x1, "gpio_out"),
                  SUNXI_FUNCTION(0x2, "nand0")),        /* NCE1 */
-       SUNXI_PIN(SUNXI_PINCTRL_PIN_PC4,
+       SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 4),
                  SUNXI_FUNCTION(0x0, "gpio_in"),
                  SUNXI_FUNCTION(0x1, "gpio_out"),
                  SUNXI_FUNCTION(0x2, "nand0")),        /* NCE0 */
-       SUNXI_PIN(SUNXI_PINCTRL_PIN_PC5,
+       SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 5),
                  SUNXI_FUNCTION(0x0, "gpio_in"),
                  SUNXI_FUNCTION(0x1, "gpio_out"),
                  SUNXI_FUNCTION(0x2, "nand0")),        /* NRE# */
-       SUNXI_PIN(SUNXI_PINCTRL_PIN_PC6,
+       SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 6),
                  SUNXI_FUNCTION(0x0, "gpio_in"),
                  SUNXI_FUNCTION(0x1, "gpio_out"),
                  SUNXI_FUNCTION(0x2, "nand0"),         /* NRB0 */
                  SUNXI_FUNCTION(0x3, "mmc2")),         /* CMD */
-       SUNXI_PIN(SUNXI_PINCTRL_PIN_PC7,
+       SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 7),
                  SUNXI_FUNCTION(0x0, "gpio_in"),
                  SUNXI_FUNCTION(0x1, "gpio_out"),
                  SUNXI_FUNCTION(0x2, "nand0"),         /* NRB1 */
                  SUNXI_FUNCTION(0x3, "mmc2")),         /* CLK */
-       SUNXI_PIN(SUNXI_PINCTRL_PIN_PC8,
+       SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 8),
                  SUNXI_FUNCTION(0x0, "gpio_in"),
                  SUNXI_FUNCTION(0x1, "gpio_out"),
                  SUNXI_FUNCTION(0x2, "nand0"),         /* NDQ0 */
                  SUNXI_FUNCTION(0x3, "mmc2")),         /* D0 */
-       SUNXI_PIN(SUNXI_PINCTRL_PIN_PC9,
+       SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 9),
                  SUNXI_FUNCTION(0x0, "gpio_in"),
                  SUNXI_FUNCTION(0x1, "gpio_out"),
                  SUNXI_FUNCTION(0x2, "nand0"),         /* NDQ1 */
                  SUNXI_FUNCTION(0x3, "mmc2")),         /* D1 */
-       SUNXI_PIN(SUNXI_PINCTRL_PIN_PC10,
+       SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 10),
                  SUNXI_FUNCTION(0x0, "gpio_in"),
                  SUNXI_FUNCTION(0x1, "gpio_out"),
                  SUNXI_FUNCTION(0x2, "nand0"),         /* NDQ2 */
                  SUNXI_FUNCTION(0x3, "mmc2")),         /* D2 */
-       SUNXI_PIN(SUNXI_PINCTRL_PIN_PC11,
+       SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 11),
                  SUNXI_FUNCTION(0x0, "gpio_in"),
                  SUNXI_FUNCTION(0x1, "gpio_out"),
                  SUNXI_FUNCTION(0x2, "nand0"),         /* NDQ3 */
                  SUNXI_FUNCTION(0x3, "mmc2")),         /* D3 */
-       SUNXI_PIN(SUNXI_PINCTRL_PIN_PC12,
+       SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 12),
                  SUNXI_FUNCTION(0x0, "gpio_in"),
                  SUNXI_FUNCTION(0x1, "gpio_out"),
                  SUNXI_FUNCTION(0x2, "nand0")),        /* NDQ4 */
-       SUNXI_PIN(SUNXI_PINCTRL_PIN_PC13,
+       SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 13),
                  SUNXI_FUNCTION(0x0, "gpio_in"),
                  SUNXI_FUNCTION(0x1, "gpio_out"),
                  SUNXI_FUNCTION(0x2, "nand0")),        /* NDQ5 */
-       SUNXI_PIN(SUNXI_PINCTRL_PIN_PC14,
+       SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 14),
                  SUNXI_FUNCTION(0x0, "gpio_in"),
                  SUNXI_FUNCTION(0x1, "gpio_out"),
                  SUNXI_FUNCTION(0x2, "nand0")),        /* NDQ6 */
-       SUNXI_PIN(SUNXI_PINCTRL_PIN_PC15,
+       SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 15),
                  SUNXI_FUNCTION(0x0, "gpio_in"),
                  SUNXI_FUNCTION(0x1, "gpio_out"),
                  SUNXI_FUNCTION(0x2, "nand0")),        /* NDQ7 */
-       SUNXI_PIN(SUNXI_PINCTRL_PIN_PC16,
+       SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 16),
                  SUNXI_FUNCTION(0x0, "gpio_in"),
                  SUNXI_FUNCTION(0x1, "gpio_out"),
                  SUNXI_FUNCTION(0x2, "nand0")),        /* NWP */
-       SUNXI_PIN(SUNXI_PINCTRL_PIN_PC17,
+       SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 17),
                  SUNXI_FUNCTION(0x0, "gpio_in"),
                  SUNXI_FUNCTION(0x1, "gpio_out"),
                  SUNXI_FUNCTION(0x2, "nand0")),        /* NCE2 */
-       SUNXI_PIN(SUNXI_PINCTRL_PIN_PC18,
+       SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 18),
                  SUNXI_FUNCTION(0x0, "gpio_in"),
                  SUNXI_FUNCTION(0x1, "gpio_out"),
                  SUNXI_FUNCTION(0x2, "nand0")),        /* NCE3 */
-       SUNXI_PIN(SUNXI_PINCTRL_PIN_PC19,
+       SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 19),
                  SUNXI_FUNCTION(0x0, "gpio_in"),
                  SUNXI_FUNCTION(0x1, "gpio_out"),
                  SUNXI_FUNCTION(0x2, "nand0"),         /* NCE4 */
                  SUNXI_FUNCTION(0x3, "spi2")),         /* CS0 */
-       SUNXI_PIN(SUNXI_PINCTRL_PIN_PC20,
+       SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 20),
                  SUNXI_FUNCTION(0x0, "gpio_in"),
                  SUNXI_FUNCTION(0x1, "gpio_out"),
                  SUNXI_FUNCTION(0x2, "nand0"),         /* NCE5 */
                  SUNXI_FUNCTION(0x3, "spi2")),         /* CLK */
-       SUNXI_PIN(SUNXI_PINCTRL_PIN_PC21,
+       SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 21),
                  SUNXI_FUNCTION(0x0, "gpio_in"),
                  SUNXI_FUNCTION(0x1, "gpio_out"),
                  SUNXI_FUNCTION(0x2, "nand0"),         /* NCE6 */
                  SUNXI_FUNCTION(0x3, "spi2")),         /* MOSI */
-       SUNXI_PIN(SUNXI_PINCTRL_PIN_PC22,
+       SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 22),
                  SUNXI_FUNCTION(0x0, "gpio_in"),
                  SUNXI_FUNCTION(0x1, "gpio_out"),
                  SUNXI_FUNCTION(0x2, "nand0"),         /* NCE7 */
                  SUNXI_FUNCTION(0x3, "spi2")),         /* MISO */
-       SUNXI_PIN(SUNXI_PINCTRL_PIN_PC23,
+       SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 23),
                  SUNXI_FUNCTION(0x0, "gpio_in"),
                  SUNXI_FUNCTION(0x1, "gpio_out"),
                  SUNXI_FUNCTION(0x3, "spi0")),         /* CS0 */
-       SUNXI_PIN(SUNXI_PINCTRL_PIN_PC24,
+       SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 24),
                  SUNXI_FUNCTION(0x0, "gpio_in"),
                  SUNXI_FUNCTION(0x1, "gpio_out"),
                  SUNXI_FUNCTION(0x2, "nand0")),        /* NDQS */
        /* Hole */
-       SUNXI_PIN(SUNXI_PINCTRL_PIN_PD0,
+       SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 0),
                  SUNXI_FUNCTION(0x0, "gpio_in"),
                  SUNXI_FUNCTION(0x1, "gpio_out"),
                  SUNXI_FUNCTION(0x2, "lcd0"),          /* D0 */
                  SUNXI_FUNCTION(0x3, "lvds0")),        /* VP0 */
-       SUNXI_PIN(SUNXI_PINCTRL_PIN_PD1,
+       SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 1),
                  SUNXI_FUNCTION(0x0, "gpio_in"),
                  SUNXI_FUNCTION(0x1, "gpio_out"),
                  SUNXI_FUNCTION(0x2, "lcd0"),          /* D1 */
                  SUNXI_FUNCTION(0x3, "lvds0")),        /* VN0 */
-       SUNXI_PIN(SUNXI_PINCTRL_PIN_PD2,
+       SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 2),
                  SUNXI_FUNCTION(0x0, "gpio_in"),
                  SUNXI_FUNCTION(0x1, "gpio_out"),
                  SUNXI_FUNCTION(0x2, "lcd0"),          /* D2 */
                  SUNXI_FUNCTION(0x3, "lvds0")),        /* VP1 */
-       SUNXI_PIN(SUNXI_PINCTRL_PIN_PD3,
+       SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 3),
                  SUNXI_FUNCTION(0x0, "gpio_in"),
                  SUNXI_FUNCTION(0x1, "gpio_out"),
                  SUNXI_FUNCTION(0x2, "lcd0"),          /* D3 */
                  SUNXI_FUNCTION(0x3, "lvds0")),        /* VN1 */
-       SUNXI_PIN(SUNXI_PINCTRL_PIN_PD4,
+       SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 4),
                  SUNXI_FUNCTION(0x0, "gpio_in"),
                  SUNXI_FUNCTION(0x1, "gpio_out"),
                  SUNXI_FUNCTION(0x2, "lcd0"),          /* D4 */
                  SUNXI_FUNCTION(0x3, "lvds0")),        /* VP2 */
-       SUNXI_PIN(SUNXI_PINCTRL_PIN_PD5,
+       SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 5),
                  SUNXI_FUNCTION(0x0, "gpio_in"),
                  SUNXI_FUNCTION(0x1, "gpio_out"),
                  SUNXI_FUNCTION(0x2, "lcd0"),          /* D5 */
                  SUNXI_FUNCTION(0x3, "lvds0")),        /* VN2 */
-       SUNXI_PIN(SUNXI_PINCTRL_PIN_PD6,
+       SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 6),
                  SUNXI_FUNCTION(0x0, "gpio_in"),
                  SUNXI_FUNCTION(0x1, "gpio_out"),
                  SUNXI_FUNCTION(0x2, "lcd0"),          /* D6 */
                  SUNXI_FUNCTION(0x3, "lvds0")),        /* VPC */
-       SUNXI_PIN(SUNXI_PINCTRL_PIN_PD7,
+       SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 7),
                  SUNXI_FUNCTION(0x0, "gpio_in"),
                  SUNXI_FUNCTION(0x1, "gpio_out"),
                  SUNXI_FUNCTION(0x2, "lcd0"),          /* D7 */
                  SUNXI_FUNCTION(0x3, "lvds0")),        /* VNC */
-       SUNXI_PIN(SUNXI_PINCTRL_PIN_PD8,
+       SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 8),
                  SUNXI_FUNCTION(0x0, "gpio_in"),
                  SUNXI_FUNCTION(0x1, "gpio_out"),
                  SUNXI_FUNCTION(0x2, "lcd0"),          /* D8 */
                  SUNXI_FUNCTION(0x3, "lvds0")),        /* VP3 */
-       SUNXI_PIN(SUNXI_PINCTRL_PIN_PD9,
+       SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 9),
                  SUNXI_FUNCTION(0x0, "gpio_in"),
                  SUNXI_FUNCTION(0x1, "gpio_out"),
                  SUNXI_FUNCTION(0x2, "lcd0"),          /* D9 */
                  SUNXI_FUNCTION(0x3, "lvds0")),        /* VM3 */
-       SUNXI_PIN(SUNXI_PINCTRL_PIN_PD10,
+       SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 10),
                  SUNXI_FUNCTION(0x0, "gpio_in"),
                  SUNXI_FUNCTION(0x1, "gpio_out"),
                  SUNXI_FUNCTION(0x2, "lcd0"),          /* D10 */
                  SUNXI_FUNCTION(0x3, "lvds1")),        /* VP0 */
-       SUNXI_PIN(SUNXI_PINCTRL_PIN_PD11,
+       SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 11),
                  SUNXI_FUNCTION(0x0, "gpio_in"),
                  SUNXI_FUNCTION(0x1, "gpio_out"),
                  SUNXI_FUNCTION(0x2, "lcd0"),          /* D11 */
                  SUNXI_FUNCTION(0x3, "lvds1")),        /* VN0 */
-       SUNXI_PIN(SUNXI_PINCTRL_PIN_PD12,
+       SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 12),
                  SUNXI_FUNCTION(0x0, "gpio_in"),
                  SUNXI_FUNCTION(0x1, "gpio_out"),
                  SUNXI_FUNCTION(0x2, "lcd0"),          /* D12 */
                  SUNXI_FUNCTION(0x3, "lvds1")),        /* VP1 */
-       SUNXI_PIN(SUNXI_PINCTRL_PIN_PD13,
+       SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 13),
                  SUNXI_FUNCTION(0x0, "gpio_in"),
                  SUNXI_FUNCTION(0x1, "gpio_out"),
                  SUNXI_FUNCTION(0x2, "lcd0"),          /* D13 */
                  SUNXI_FUNCTION(0x3, "lvds1")),        /* VN1 */
-       SUNXI_PIN(SUNXI_PINCTRL_PIN_PD14,
+       SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 14),
                  SUNXI_FUNCTION(0x0, "gpio_in"),
                  SUNXI_FUNCTION(0x1, "gpio_out"),
                  SUNXI_FUNCTION(0x2, "lcd0"),          /* D14 */
                  SUNXI_FUNCTION(0x3, "lvds1")),        /* VP2 */
-       SUNXI_PIN(SUNXI_PINCTRL_PIN_PD15,
+       SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 15),
                  SUNXI_FUNCTION(0x0, "gpio_in"),
                  SUNXI_FUNCTION(0x1, "gpio_out"),
                  SUNXI_FUNCTION(0x2, "lcd0"),          /* D15 */
                  SUNXI_FUNCTION(0x3, "lvds1")),        /* VN2 */
-       SUNXI_PIN(SUNXI_PINCTRL_PIN_PD16,
+       SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 16),
                  SUNXI_FUNCTION(0x0, "gpio_in"),
                  SUNXI_FUNCTION(0x1, "gpio_out"),
                  SUNXI_FUNCTION(0x2, "lcd0"),          /* D16 */
                  SUNXI_FUNCTION(0x3, "lvds1")),        /* VPC */
-       SUNXI_PIN(SUNXI_PINCTRL_PIN_PD17,
+       SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 17),
                  SUNXI_FUNCTION(0x0, "gpio_in"),
                  SUNXI_FUNCTION(0x1, "gpio_out"),
                  SUNXI_FUNCTION(0x2, "lcd0"),          /* D17 */
                  SUNXI_FUNCTION(0x3, "lvds1")),        /* VNC */
-       SUNXI_PIN(SUNXI_PINCTRL_PIN_PD18,
+       SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 18),
                  SUNXI_FUNCTION(0x0, "gpio_in"),
                  SUNXI_FUNCTION(0x1, "gpio_out"),
                  SUNXI_FUNCTION(0x2, "lcd0"),          /* D18 */
                  SUNXI_FUNCTION(0x3, "lvds1")),        /* VP3 */
-       SUNXI_PIN(SUNXI_PINCTRL_PIN_PD19,
+       SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 19),
                  SUNXI_FUNCTION(0x0, "gpio_in"),
                  SUNXI_FUNCTION(0x1, "gpio_out"),
                  SUNXI_FUNCTION(0x2, "lcd0"),          /* D19 */
                  SUNXI_FUNCTION(0x3, "lvds1")),        /* VN3 */
-       SUNXI_PIN(SUNXI_PINCTRL_PIN_PD20,
+       SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 20),
                  SUNXI_FUNCTION(0x0, "gpio_in"),
                  SUNXI_FUNCTION(0x1, "gpio_out"),
                  SUNXI_FUNCTION(0x2, "lcd0"),          /* D20 */
                  SUNXI_FUNCTION(0x3, "csi1")),         /* MCLK */
-       SUNXI_PIN(SUNXI_PINCTRL_PIN_PD21,
+       SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 21),
                  SUNXI_FUNCTION(0x0, "gpio_in"),
                  SUNXI_FUNCTION(0x1, "gpio_out"),
                  SUNXI_FUNCTION(0x2, "lcd0"),          /* D21 */
                  SUNXI_FUNCTION(0x3, "sim")),          /* VPPEN */
-       SUNXI_PIN(SUNXI_PINCTRL_PIN_PD22,
+       SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 22),
                  SUNXI_FUNCTION(0x0, "gpio_in"),
                  SUNXI_FUNCTION(0x1, "gpio_out"),
                  SUNXI_FUNCTION(0x2, "lcd0"),          /* D22 */
                  SUNXI_FUNCTION(0x3, "sim")),          /* VPPPP */
-       SUNXI_PIN(SUNXI_PINCTRL_PIN_PD23,
+       SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 23),
                  SUNXI_FUNCTION(0x0, "gpio_in"),
                  SUNXI_FUNCTION(0x1, "gpio_out"),
                  SUNXI_FUNCTION(0x2, "lcd0"),          /* D23 */
                  SUNXI_FUNCTION(0x3, "sim")),          /* DET */
-       SUNXI_PIN(SUNXI_PINCTRL_PIN_PD24,
+       SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 24),
                  SUNXI_FUNCTION(0x0, "gpio_in"),
                  SUNXI_FUNCTION(0x1, "gpio_out"),
                  SUNXI_FUNCTION(0x2, "lcd0"),          /* CLK */
                  SUNXI_FUNCTION(0x3, "sim")),          /* VCCEN */
-       SUNXI_PIN(SUNXI_PINCTRL_PIN_PD25,
+       SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 25),
                  SUNXI_FUNCTION(0x0, "gpio_in"),
                  SUNXI_FUNCTION(0x1, "gpio_out"),
                  SUNXI_FUNCTION(0x2, "lcd0"),          /* DE */
                  SUNXI_FUNCTION(0x3, "sim")),          /* RST */
-       SUNXI_PIN(SUNXI_PINCTRL_PIN_PD26,
+       SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 26),
                  SUNXI_FUNCTION(0x0, "gpio_in"),
                  SUNXI_FUNCTION(0x1, "gpio_out"),
                  SUNXI_FUNCTION(0x2, "lcd0"),          /* HSYNC */
                  SUNXI_FUNCTION(0x3, "sim")),          /* SCK */
-       SUNXI_PIN(SUNXI_PINCTRL_PIN_PD27,
+       SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 27),
                  SUNXI_FUNCTION(0x0, "gpio_in"),
                  SUNXI_FUNCTION(0x1, "gpio_out"),
                  SUNXI_FUNCTION(0x2, "lcd0"),          /* VSYNC */
                  SUNXI_FUNCTION(0x3, "sim")),          /* SDA */
        /* Hole */
-       SUNXI_PIN(SUNXI_PINCTRL_PIN_PE0,
+       SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 0),
                  SUNXI_FUNCTION(0x0, "gpio_in"),
                  SUNXI_FUNCTION(0x1, "gpio_out"),
                  SUNXI_FUNCTION(0x2, "ts0"),           /* CLK */
                  SUNXI_FUNCTION(0x3, "csi0")),         /* PCK */
-       SUNXI_PIN(SUNXI_PINCTRL_PIN_PE1,
+       SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 1),
                  SUNXI_FUNCTION(0x0, "gpio_in"),
                  SUNXI_FUNCTION(0x1, "gpio_out"),
                  SUNXI_FUNCTION(0x2, "ts0"),           /* ERR */
                  SUNXI_FUNCTION(0x3, "csi0")),         /* CK */
-       SUNXI_PIN(SUNXI_PINCTRL_PIN_PE2,
+       SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 2),
                  SUNXI_FUNCTION(0x0, "gpio_in"),
                  SUNXI_FUNCTION(0x1, "gpio_out"),
                  SUNXI_FUNCTION(0x2, "ts0"),           /* SYNC */
                  SUNXI_FUNCTION(0x3, "csi0")),         /* HSYNC */
-       SUNXI_PIN(SUNXI_PINCTRL_PIN_PE3,
+       SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 3),
                  SUNXI_FUNCTION(0x0, "gpio_in"),
                  SUNXI_FUNCTION(0x1, "gpio_out"),
                  SUNXI_FUNCTION(0x2, "ts0"),           /* DVLD */
                  SUNXI_FUNCTION(0x3, "csi0")),         /* VSYNC */
-       SUNXI_PIN(SUNXI_PINCTRL_PIN_PE4,
+       SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 4),
                  SUNXI_FUNCTION(0x0, "gpio_in"),
                  SUNXI_FUNCTION(0x1, "gpio_out"),
                  SUNXI_FUNCTION(0x2, "ts0"),           /* D0 */
                  SUNXI_FUNCTION(0x3, "csi0")),         /* D0 */
-       SUNXI_PIN(SUNXI_PINCTRL_PIN_PE5,
+       SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 5),
                  SUNXI_FUNCTION(0x0, "gpio_in"),
                  SUNXI_FUNCTION(0x1, "gpio_out"),
                  SUNXI_FUNCTION(0x2, "ts0"),           /* D1 */
                  SUNXI_FUNCTION(0x3, "csi0"),          /* D1 */
                  SUNXI_FUNCTION(0x4, "sim")),          /* VPPEN */
-       SUNXI_PIN(SUNXI_PINCTRL_PIN_PE6,
+       SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 6),
                  SUNXI_FUNCTION(0x0, "gpio_in"),
                  SUNXI_FUNCTION(0x1, "gpio_out"),
                  SUNXI_FUNCTION(0x2, "ts0"),           /* D2 */
                  SUNXI_FUNCTION(0x3, "csi0")),         /* D2 */
-       SUNXI_PIN(SUNXI_PINCTRL_PIN_PE7,
+       SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 7),
                  SUNXI_FUNCTION(0x0, "gpio_in"),
                  SUNXI_FUNCTION(0x1, "gpio_out"),
                  SUNXI_FUNCTION(0x2, "ts0"),           /* D3 */
                  SUNXI_FUNCTION(0x3, "csi0")),         /* D3 */
-       SUNXI_PIN(SUNXI_PINCTRL_PIN_PE8,
+       SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 8),
                  SUNXI_FUNCTION(0x0, "gpio_in"),
                  SUNXI_FUNCTION(0x1, "gpio_out"),
                  SUNXI_FUNCTION(0x2, "ts0"),           /* D4 */
                  SUNXI_FUNCTION(0x3, "csi0")),         /* D4 */
-       SUNXI_PIN(SUNXI_PINCTRL_PIN_PE9,
+       SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 9),
                  SUNXI_FUNCTION(0x0, "gpio_in"),
                  SUNXI_FUNCTION(0x1, "gpio_out"),
                  SUNXI_FUNCTION(0x2, "ts0"),           /* D5 */
                  SUNXI_FUNCTION(0x3, "csi0")),         /* D5 */
-       SUNXI_PIN(SUNXI_PINCTRL_PIN_PE10,
+       SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 10),
                  SUNXI_FUNCTION(0x0, "gpio_in"),
                  SUNXI_FUNCTION(0x1, "gpio_out"),
                  SUNXI_FUNCTION(0x2, "ts0"),           /* D6 */
                  SUNXI_FUNCTION(0x3, "csi0")),         /* D6 */
-       SUNXI_PIN(SUNXI_PINCTRL_PIN_PE11,
+       SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 11),
                  SUNXI_FUNCTION(0x0, "gpio_in"),
                  SUNXI_FUNCTION(0x1, "gpio_out"),
                  SUNXI_FUNCTION(0x2, "ts0"),           /* D7 */
                  SUNXI_FUNCTION(0x3, "csi0")),         /* D7 */
        /* Hole */
-       SUNXI_PIN(SUNXI_PINCTRL_PIN_PF0,
+       SUNXI_PIN(SUNXI_PINCTRL_PIN(F, 0),
                  SUNXI_FUNCTION(0x0, "gpio_in"),
                  SUNXI_FUNCTION(0x1, "gpio_out"),
                  SUNXI_FUNCTION(0x2, "mmc0"),          /* D1 */
                  SUNXI_FUNCTION(0x4, "jtag")),         /* MSI */
-       SUNXI_PIN(SUNXI_PINCTRL_PIN_PF1,
+       SUNXI_PIN(SUNXI_PINCTRL_PIN(F, 1),
                  SUNXI_FUNCTION(0x0, "gpio_in"),
                  SUNXI_FUNCTION(0x1, "gpio_out"),
                  SUNXI_FUNCTION(0x2, "mmc0"),          /* D0 */
                  SUNXI_FUNCTION(0x4, "jtag")),         /* DI1 */
-       SUNXI_PIN(SUNXI_PINCTRL_PIN_PF2,
+       SUNXI_PIN(SUNXI_PINCTRL_PIN(F, 2),
                  SUNXI_FUNCTION(0x0, "gpio_in"),
                  SUNXI_FUNCTION(0x1, "gpio_out"),
                  SUNXI_FUNCTION(0x2, "mmc0"),          /* CLK */
                  SUNXI_FUNCTION(0x4, "uart0")),        /* TX */
-       SUNXI_PIN(SUNXI_PINCTRL_PIN_PF3,
+       SUNXI_PIN(SUNXI_PINCTRL_PIN(F, 3),
                  SUNXI_FUNCTION(0x0, "gpio_in"),
                  SUNXI_FUNCTION(0x1, "gpio_out"),
                  SUNXI_FUNCTION(0x2, "mmc0"),          /* CMD */
                  SUNXI_FUNCTION(0x4, "jtag")),         /* DO1 */
-       SUNXI_PIN(SUNXI_PINCTRL_PIN_PF4,
+       SUNXI_PIN(SUNXI_PINCTRL_PIN(F, 4),
                  SUNXI_FUNCTION(0x0, "gpio_in"),
                  SUNXI_FUNCTION(0x1, "gpio_out"),
                  SUNXI_FUNCTION(0x2, "mmc0"),          /* D3 */
                  SUNXI_FUNCTION(0x4, "uart0")),        /* RX */
-       SUNXI_PIN(SUNXI_PINCTRL_PIN_PF5,
+       SUNXI_PIN(SUNXI_PINCTRL_PIN(F, 5),
                  SUNXI_FUNCTION(0x0, "gpio_in"),
                  SUNXI_FUNCTION(0x1, "gpio_out"),
                  SUNXI_FUNCTION(0x2, "mmc0"),          /* D2 */
                  SUNXI_FUNCTION(0x4, "jtag")),         /* CK1 */
        /* Hole */
-       SUNXI_PIN(SUNXI_PINCTRL_PIN_PG0,
+       SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 0),
                  SUNXI_FUNCTION(0x0, "gpio_in"),
                  SUNXI_FUNCTION(0x1, "gpio_out"),
                  SUNXI_FUNCTION(0x2, "ts1"),           /* CLK */
                  SUNXI_FUNCTION(0x3, "csi1"),          /* PCK */
                  SUNXI_FUNCTION(0x4, "mmc1")),         /* CMD */
-       SUNXI_PIN(SUNXI_PINCTRL_PIN_PG1,
+       SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 1),
                  SUNXI_FUNCTION(0x0, "gpio_in"),
                  SUNXI_FUNCTION(0x1, "gpio_out"),
                  SUNXI_FUNCTION(0x2, "ts1"),           /* ERR */
                  SUNXI_FUNCTION(0x3, "csi1"),          /* CK */
                  SUNXI_FUNCTION(0x4, "mmc1")),         /* CLK */
-       SUNXI_PIN(SUNXI_PINCTRL_PIN_PG2,
+       SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 2),
                  SUNXI_FUNCTION(0x0, "gpio_in"),
                  SUNXI_FUNCTION(0x1, "gpio_out"),
                  SUNXI_FUNCTION(0x2, "ts1"),           /* SYNC */
                  SUNXI_FUNCTION(0x3, "csi1"),          /* HSYNC */
                  SUNXI_FUNCTION(0x4, "mmc1")),         /* D0 */
-       SUNXI_PIN(SUNXI_PINCTRL_PIN_PG3,
+       SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 3),
                  SUNXI_FUNCTION(0x0, "gpio_in"),
                  SUNXI_FUNCTION(0x1, "gpio_out"),
                  SUNXI_FUNCTION(0x2, "ts1"),           /* DVLD */
                  SUNXI_FUNCTION(0x3, "csi1"),          /* VSYNC */
                  SUNXI_FUNCTION(0x4, "mmc1")),         /* D1 */
-       SUNXI_PIN(SUNXI_PINCTRL_PIN_PG4,
+       SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 4),
                  SUNXI_FUNCTION(0x0, "gpio_in"),
                  SUNXI_FUNCTION(0x1, "gpio_out"),
                  SUNXI_FUNCTION(0x2, "ts1"),           /* D0 */
                  SUNXI_FUNCTION(0x3, "csi1"),          /* D0 */
                  SUNXI_FUNCTION(0x4, "mmc1"),          /* D2 */
                  SUNXI_FUNCTION(0x5, "csi0")),         /* D8 */
-       SUNXI_PIN(SUNXI_PINCTRL_PIN_PG5,
+       SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 5),
                  SUNXI_FUNCTION(0x0, "gpio_in"),
                  SUNXI_FUNCTION(0x1, "gpio_out"),
                  SUNXI_FUNCTION(0x2, "ts1"),           /* D1 */
                  SUNXI_FUNCTION(0x3, "csi1"),          /* D1 */
                  SUNXI_FUNCTION(0x4, "mmc1"),          /* D3 */
                  SUNXI_FUNCTION(0x5, "csi0")),         /* D9 */
-       SUNXI_PIN(SUNXI_PINCTRL_PIN_PG6,
+       SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 6),
                  SUNXI_FUNCTION(0x0, "gpio_in"),
                  SUNXI_FUNCTION(0x1, "gpio_out"),
                  SUNXI_FUNCTION(0x2, "ts1"),           /* D2 */
                  SUNXI_FUNCTION(0x3, "csi1"),          /* D2 */
                  SUNXI_FUNCTION(0x4, "uart3"),         /* TX */
                  SUNXI_FUNCTION(0x5, "csi0")),         /* D10 */
-       SUNXI_PIN(SUNXI_PINCTRL_PIN_PG7,
+       SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 7),
                  SUNXI_FUNCTION(0x0, "gpio_in"),
                  SUNXI_FUNCTION(0x1, "gpio_out"),
                  SUNXI_FUNCTION(0x2, "ts1"),           /* D3 */
                  SUNXI_FUNCTION(0x3, "csi1"),          /* D3 */
                  SUNXI_FUNCTION(0x4, "uart3"),         /* RX */
                  SUNXI_FUNCTION(0x5, "csi0")),         /* D11 */
-       SUNXI_PIN(SUNXI_PINCTRL_PIN_PG8,
+       SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 8),
                  SUNXI_FUNCTION(0x0, "gpio_in"),
                  SUNXI_FUNCTION(0x1, "gpio_out"),
                  SUNXI_FUNCTION(0x2, "ts1"),           /* D4 */
                  SUNXI_FUNCTION(0x3, "csi1"),          /* D4 */
                  SUNXI_FUNCTION(0x4, "uart3"),         /* RTS */
                  SUNXI_FUNCTION(0x5, "csi0")),         /* D12 */
-       SUNXI_PIN(SUNXI_PINCTRL_PIN_PG9,
+       SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 9),
                  SUNXI_FUNCTION(0x0, "gpio_in"),
                  SUNXI_FUNCTION(0x1, "gpio_out"),
                  SUNXI_FUNCTION(0x2, "ts1"),           /* D5 */
                  SUNXI_FUNCTION(0x3, "csi1"),          /* D5 */
                  SUNXI_FUNCTION(0x4, "uart3"),         /* CTS */
                  SUNXI_FUNCTION(0x5, "csi0")),         /* D13 */
-       SUNXI_PIN(SUNXI_PINCTRL_PIN_PG10,
+       SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 10),
                  SUNXI_FUNCTION(0x0, "gpio_in"),
                  SUNXI_FUNCTION(0x1, "gpio_out"),
                  SUNXI_FUNCTION(0x2, "ts1"),           /* D6 */
                  SUNXI_FUNCTION(0x3, "csi1"),          /* D6 */
                  SUNXI_FUNCTION(0x4, "uart4"),         /* TX */
                  SUNXI_FUNCTION(0x5, "csi0")),         /* D14 */
-       SUNXI_PIN(SUNXI_PINCTRL_PIN_PG11,
+       SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 11),
                  SUNXI_FUNCTION(0x0, "gpio_in"),
                  SUNXI_FUNCTION(0x1, "gpio_out"),
                  SUNXI_FUNCTION(0x2, "ts1"),           /* D7 */
@@ -654,7 +654,7 @@ static const struct sunxi_desc_pin sun4i_a10_pins[] = {
                  SUNXI_FUNCTION(0x4, "uart4"),         /* RX */
                  SUNXI_FUNCTION(0x5, "csi0")),         /* D15 */
        /* Hole */
-       SUNXI_PIN(SUNXI_PINCTRL_PIN_PH0,
+       SUNXI_PIN(SUNXI_PINCTRL_PIN(H, 0),
                  SUNXI_FUNCTION(0x0, "gpio_in"),
                  SUNXI_FUNCTION(0x1, "gpio_out"),
                  SUNXI_FUNCTION(0x2, "lcd1"),          /* D0 */
@@ -662,7 +662,7 @@ static const struct sunxi_desc_pin sun4i_a10_pins[] = {
                  SUNXI_FUNCTION(0x4, "uart3"),         /* TX */
                  SUNXI_FUNCTION_IRQ(0x6, 0),           /* EINT0 */
                  SUNXI_FUNCTION(0x7, "csi1")),         /* D0 */
-       SUNXI_PIN(SUNXI_PINCTRL_PIN_PH1,
+       SUNXI_PIN(SUNXI_PINCTRL_PIN(H, 1),
                  SUNXI_FUNCTION(0x0, "gpio_in"),
                  SUNXI_FUNCTION(0x1, "gpio_out"),
                  SUNXI_FUNCTION(0x2, "lcd1"),          /* D1 */
@@ -670,7 +670,7 @@ static const struct sunxi_desc_pin sun4i_a10_pins[] = {
                  SUNXI_FUNCTION(0x4, "uart3"),         /* RX */
                  SUNXI_FUNCTION_IRQ(0x6, 1),           /* EINT1 */
                  SUNXI_FUNCTION(0x7, "csi1")),         /* D1 */
-       SUNXI_PIN(SUNXI_PINCTRL_PIN_PH2,
+       SUNXI_PIN(SUNXI_PINCTRL_PIN(H, 2),
                  SUNXI_FUNCTION(0x0, "gpio_in"),
                  SUNXI_FUNCTION(0x1, "gpio_out"),
                  SUNXI_FUNCTION(0x2, "lcd1"),          /* D2 */
@@ -678,7 +678,7 @@ static const struct sunxi_desc_pin sun4i_a10_pins[] = {
                  SUNXI_FUNCTION(0x4, "uart3"),         /* RTS */
                  SUNXI_FUNCTION_IRQ(0x6, 2),           /* EINT2 */
                  SUNXI_FUNCTION(0x7, "csi1")),         /* D2 */
-       SUNXI_PIN(SUNXI_PINCTRL_PIN_PH3,
+       SUNXI_PIN(SUNXI_PINCTRL_PIN(H, 3),
                  SUNXI_FUNCTION(0x0, "gpio_in"),
                  SUNXI_FUNCTION(0x1, "gpio_out"),
                  SUNXI_FUNCTION(0x2, "lcd1"),          /* D3 */
@@ -686,7 +686,7 @@ static const struct sunxi_desc_pin sun4i_a10_pins[] = {
                  SUNXI_FUNCTION(0x4, "uart3"),         /* CTS */
                  SUNXI_FUNCTION_IRQ(0x6, 3),           /* EINT3 */
                  SUNXI_FUNCTION(0x7, "csi1")),         /* D3 */
-       SUNXI_PIN(SUNXI_PINCTRL_PIN_PH4,
+       SUNXI_PIN(SUNXI_PINCTRL_PIN(H, 4),
                  SUNXI_FUNCTION(0x0, "gpio_in"),
                  SUNXI_FUNCTION(0x1, "gpio_out"),
                  SUNXI_FUNCTION(0x2, "lcd1"),          /* D4 */
@@ -694,7 +694,7 @@ static const struct sunxi_desc_pin sun4i_a10_pins[] = {
                  SUNXI_FUNCTION(0x4, "uart4"),         /* TX */
                  SUNXI_FUNCTION_IRQ(0x6, 4),           /* EINT4 */
                  SUNXI_FUNCTION(0x7, "csi1")),         /* D4 */
-       SUNXI_PIN(SUNXI_PINCTRL_PIN_PH5,
+       SUNXI_PIN(SUNXI_PINCTRL_PIN(H, 5),
                  SUNXI_FUNCTION(0x0, "gpio_in"),
                  SUNXI_FUNCTION(0x1, "gpio_out"),
                  SUNXI_FUNCTION(0x2, "lcd1"),          /* D5 */
@@ -702,7 +702,7 @@ static const struct sunxi_desc_pin sun4i_a10_pins[] = {
                  SUNXI_FUNCTION(0x4, "uart4"),         /* RX */
                  SUNXI_FUNCTION_IRQ(0x6, 5),           /* EINT5 */
                  SUNXI_FUNCTION(0x7, "csi1")),         /* D5 */
-       SUNXI_PIN(SUNXI_PINCTRL_PIN_PH6,
+       SUNXI_PIN(SUNXI_PINCTRL_PIN(H, 6),
                  SUNXI_FUNCTION(0x0, "gpio_in"),
                  SUNXI_FUNCTION(0x1, "gpio_out"),
                  SUNXI_FUNCTION(0x2, "lcd1"),          /* D6 */
@@ -711,7 +711,7 @@ static const struct sunxi_desc_pin sun4i_a10_pins[] = {
                  SUNXI_FUNCTION(0x5, "ms"),            /* BS */
                  SUNXI_FUNCTION_IRQ(0x6, 6),           /* EINT6 */
                  SUNXI_FUNCTION(0x7, "csi1")),         /* D6 */
-       SUNXI_PIN(SUNXI_PINCTRL_PIN_PH7,
+       SUNXI_PIN(SUNXI_PINCTRL_PIN(H, 7),
                  SUNXI_FUNCTION(0x0, "gpio_in"),
                  SUNXI_FUNCTION(0x1, "gpio_out"),
                  SUNXI_FUNCTION(0x2, "lcd1"),          /* D7 */
@@ -720,7 +720,7 @@ static const struct sunxi_desc_pin sun4i_a10_pins[] = {
                  SUNXI_FUNCTION(0x5, "ms"),            /* CLK */
                  SUNXI_FUNCTION_IRQ(0x6, 7),           /* EINT7 */
                  SUNXI_FUNCTION(0x7, "csi1")),         /* D7 */
-       SUNXI_PIN(SUNXI_PINCTRL_PIN_PH8,
+       SUNXI_PIN(SUNXI_PINCTRL_PIN(H, 8),
                  SUNXI_FUNCTION(0x0, "gpio_in"),
                  SUNXI_FUNCTION(0x1, "gpio_out"),
                  SUNXI_FUNCTION(0x2, "lcd1"),          /* D8 */
@@ -729,7 +729,7 @@ static const struct sunxi_desc_pin sun4i_a10_pins[] = {
                  SUNXI_FUNCTION(0x5, "ms"),            /* D0 */
                  SUNXI_FUNCTION_IRQ(0x6, 8),           /* EINT8 */
                  SUNXI_FUNCTION(0x7, "csi1")),         /* D8 */
-       SUNXI_PIN(SUNXI_PINCTRL_PIN_PH9,
+       SUNXI_PIN(SUNXI_PINCTRL_PIN(H, 9),
                  SUNXI_FUNCTION(0x0, "gpio_in"),
                  SUNXI_FUNCTION(0x1, "gpio_out"),
                  SUNXI_FUNCTION(0x2, "lcd1"),          /* D9 */
@@ -738,7 +738,7 @@ static const struct sunxi_desc_pin sun4i_a10_pins[] = {
                  SUNXI_FUNCTION(0x5, "ms"),            /* D1 */
                  SUNXI_FUNCTION_IRQ(0x6, 9),           /* EINT9 */
                  SUNXI_FUNCTION(0x7, "csi1")),         /* D9 */
-       SUNXI_PIN(SUNXI_PINCTRL_PIN_PH10,
+       SUNXI_PIN(SUNXI_PINCTRL_PIN(H, 10),
                  SUNXI_FUNCTION(0x0, "gpio_in"),
                  SUNXI_FUNCTION(0x1, "gpio_out"),
                  SUNXI_FUNCTION(0x2, "lcd1"),          /* D10 */
@@ -747,7 +747,7 @@ static const struct sunxi_desc_pin sun4i_a10_pins[] = {
                  SUNXI_FUNCTION(0x5, "ms"),            /* D2 */
                  SUNXI_FUNCTION_IRQ(0x6, 10),          /* EINT10 */
                  SUNXI_FUNCTION(0x7, "csi1")),         /* D10 */
-       SUNXI_PIN(SUNXI_PINCTRL_PIN_PH11,
+       SUNXI_PIN(SUNXI_PINCTRL_PIN(H, 11),
                  SUNXI_FUNCTION(0x0, "gpio_in"),
                  SUNXI_FUNCTION(0x1, "gpio_out"),
                  SUNXI_FUNCTION(0x2, "lcd1"),          /* D11 */
@@ -756,7 +756,7 @@ static const struct sunxi_desc_pin sun4i_a10_pins[] = {
                  SUNXI_FUNCTION(0x5, "ms"),            /* D3 */
                  SUNXI_FUNCTION_IRQ(0x6, 11),          /* EINT11 */
                  SUNXI_FUNCTION(0x7, "csi1")),         /* D11 */
-       SUNXI_PIN(SUNXI_PINCTRL_PIN_PH12,
+       SUNXI_PIN(SUNXI_PINCTRL_PIN(H, 12),
                  SUNXI_FUNCTION(0x0, "gpio_in"),
                  SUNXI_FUNCTION(0x1, "gpio_out"),
                  SUNXI_FUNCTION(0x2, "lcd1"),          /* D12 */
@@ -764,7 +764,7 @@ static const struct sunxi_desc_pin sun4i_a10_pins[] = {
                  SUNXI_FUNCTION(0x4, "ps2"),           /* SCK1 */
                  SUNXI_FUNCTION_IRQ(0x6, 12),          /* EINT12 */
                  SUNXI_FUNCTION(0x7, "csi1")),         /* D12 */
-       SUNXI_PIN(SUNXI_PINCTRL_PIN_PH13,
+       SUNXI_PIN(SUNXI_PINCTRL_PIN(H, 13),
                  SUNXI_FUNCTION(0x0, "gpio_in"),
                  SUNXI_FUNCTION(0x1, "gpio_out"),
                  SUNXI_FUNCTION(0x2, "lcd1"),          /* D13 */
@@ -773,7 +773,7 @@ static const struct sunxi_desc_pin sun4i_a10_pins[] = {
                  SUNXI_FUNCTION(0x5, "sim"),           /* RST */
                  SUNXI_FUNCTION_IRQ(0x6, 13),          /* EINT13 */
                  SUNXI_FUNCTION(0x7, "csi1")),         /* D13 */
-       SUNXI_PIN(SUNXI_PINCTRL_PIN_PH14,
+       SUNXI_PIN(SUNXI_PINCTRL_PIN(H, 14),
                  SUNXI_FUNCTION(0x0, "gpio_in"),
                  SUNXI_FUNCTION(0x1, "gpio_out"),
                  SUNXI_FUNCTION(0x2, "lcd1"),          /* D14 */
@@ -782,7 +782,7 @@ static const struct sunxi_desc_pin sun4i_a10_pins[] = {
                  SUNXI_FUNCTION(0x5, "sim"),           /* VPPEN */
                  SUNXI_FUNCTION_IRQ(0x6, 14),          /* EINT14 */
                  SUNXI_FUNCTION(0x7, "csi1")),         /* D14 */
-       SUNXI_PIN(SUNXI_PINCTRL_PIN_PH15,
+       SUNXI_PIN(SUNXI_PINCTRL_PIN(H, 15),
                  SUNXI_FUNCTION(0x0, "gpio_in"),
                  SUNXI_FUNCTION(0x1, "gpio_out"),
                  SUNXI_FUNCTION(0x2, "lcd1"),          /* D15 */
@@ -791,7 +791,7 @@ static const struct sunxi_desc_pin sun4i_a10_pins[] = {
                  SUNXI_FUNCTION(0x5, "sim"),           /* VPPPP */
                  SUNXI_FUNCTION_IRQ(0x6, 15),          /* EINT15 */
                  SUNXI_FUNCTION(0x7, "csi1")),         /* D15 */
-       SUNXI_PIN(SUNXI_PINCTRL_PIN_PH16,
+       SUNXI_PIN(SUNXI_PINCTRL_PIN(H, 16),
                  SUNXI_FUNCTION(0x0, "gpio_in"),
                  SUNXI_FUNCTION(0x1, "gpio_out"),
                  SUNXI_FUNCTION(0x2, "lcd1"),          /* D16 */
@@ -799,7 +799,7 @@ static const struct sunxi_desc_pin sun4i_a10_pins[] = {
                  SUNXI_FUNCTION(0x4, "keypad"),        /* IN6 */
                  SUNXI_FUNCTION_IRQ(0x6, 16),          /* EINT16 */
                  SUNXI_FUNCTION(0x7, "csi1")),         /* D16 */
-       SUNXI_PIN(SUNXI_PINCTRL_PIN_PH17,
+       SUNXI_PIN(SUNXI_PINCTRL_PIN(H, 17),
                  SUNXI_FUNCTION(0x0, "gpio_in"),
                  SUNXI_FUNCTION(0x1, "gpio_out"),
                  SUNXI_FUNCTION(0x2, "lcd1"),          /* D17 */
@@ -808,7 +808,7 @@ static const struct sunxi_desc_pin sun4i_a10_pins[] = {
                  SUNXI_FUNCTION(0x5, "sim"),           /* VCCEN */
                  SUNXI_FUNCTION_IRQ(0x6, 17),          /* EINT17 */
                  SUNXI_FUNCTION(0x7, "csi1")),         /* D17 */
-       SUNXI_PIN(SUNXI_PINCTRL_PIN_PH18,
+       SUNXI_PIN(SUNXI_PINCTRL_PIN(H, 18),
                  SUNXI_FUNCTION(0x0, "gpio_in"),
                  SUNXI_FUNCTION(0x1, "gpio_out"),
                  SUNXI_FUNCTION(0x2, "lcd1"),          /* D18 */
@@ -817,7 +817,7 @@ static const struct sunxi_desc_pin sun4i_a10_pins[] = {
                  SUNXI_FUNCTION(0x5, "sim"),           /* SCK */
                  SUNXI_FUNCTION_IRQ(0x6, 18),          /* EINT18 */
                  SUNXI_FUNCTION(0x7, "csi1")),         /* D18 */
-       SUNXI_PIN(SUNXI_PINCTRL_PIN_PH19,
+       SUNXI_PIN(SUNXI_PINCTRL_PIN(H, 19),
                  SUNXI_FUNCTION(0x0, "gpio_in"),
                  SUNXI_FUNCTION(0x1, "gpio_out"),
                  SUNXI_FUNCTION(0x2, "lcd1"),          /* D19 */
@@ -826,7 +826,7 @@ static const struct sunxi_desc_pin sun4i_a10_pins[] = {
                  SUNXI_FUNCTION(0x5, "sim"),           /* SDA */
                  SUNXI_FUNCTION_IRQ(0x6, 19),          /* EINT19 */
                  SUNXI_FUNCTION(0x7, "csi1")),         /* D19 */
-       SUNXI_PIN(SUNXI_PINCTRL_PIN_PH20,
+       SUNXI_PIN(SUNXI_PINCTRL_PIN(H, 20),
                  SUNXI_FUNCTION(0x0, "gpio_in"),
                  SUNXI_FUNCTION(0x1, "gpio_out"),
                  SUNXI_FUNCTION(0x2, "lcd1"),          /* D20 */
@@ -834,7 +834,7 @@ static const struct sunxi_desc_pin sun4i_a10_pins[] = {
                  SUNXI_FUNCTION(0x4, "can"),           /* TX */
                  SUNXI_FUNCTION_IRQ(0x6, 20),          /* EINT20 */
                  SUNXI_FUNCTION(0x7, "csi1")),         /* D20 */
-       SUNXI_PIN(SUNXI_PINCTRL_PIN_PH21,
+       SUNXI_PIN(SUNXI_PINCTRL_PIN(H, 21),
                  SUNXI_FUNCTION(0x0, "gpio_in"),
                  SUNXI_FUNCTION(0x1, "gpio_out"),
                  SUNXI_FUNCTION(0x2, "lcd1"),          /* D21 */
@@ -842,7 +842,7 @@ static const struct sunxi_desc_pin sun4i_a10_pins[] = {
                  SUNXI_FUNCTION(0x4, "can"),           /* RX */
                  SUNXI_FUNCTION_IRQ(0x6, 21),          /* EINT21 */
                  SUNXI_FUNCTION(0x7, "csi1")),         /* D21 */
-       SUNXI_PIN(SUNXI_PINCTRL_PIN_PH22,
+       SUNXI_PIN(SUNXI_PINCTRL_PIN(H, 22),
                  SUNXI_FUNCTION(0x0, "gpio_in"),
                  SUNXI_FUNCTION(0x1, "gpio_out"),
                  SUNXI_FUNCTION(0x2, "lcd1"),          /* D22 */
@@ -850,7 +850,7 @@ static const struct sunxi_desc_pin sun4i_a10_pins[] = {
                  SUNXI_FUNCTION(0x4, "keypad"),        /* OUT2 */
                  SUNXI_FUNCTION(0x5, "mmc1"),          /* CMD */
                  SUNXI_FUNCTION(0x7, "csi1")),         /* D22 */
-       SUNXI_PIN(SUNXI_PINCTRL_PIN_PH23,
+       SUNXI_PIN(SUNXI_PINCTRL_PIN(H, 23),
                  SUNXI_FUNCTION(0x0, "gpio_in"),
                  SUNXI_FUNCTION(0x1, "gpio_out"),
                  SUNXI_FUNCTION(0x2, "lcd1"),          /* D23 */
@@ -858,7 +858,7 @@ static const struct sunxi_desc_pin sun4i_a10_pins[] = {
                  SUNXI_FUNCTION(0x4, "keypad"),        /* OUT3 */
                  SUNXI_FUNCTION(0x5, "mmc1"),          /* CLK */
                  SUNXI_FUNCTION(0x7, "csi1")),         /* D23 */
-       SUNXI_PIN(SUNXI_PINCTRL_PIN_PH24,
+       SUNXI_PIN(SUNXI_PINCTRL_PIN(H, 24),
                  SUNXI_FUNCTION(0x0, "gpio_in"),
                  SUNXI_FUNCTION(0x1, "gpio_out"),
                  SUNXI_FUNCTION(0x2, "lcd1"),          /* CLK */
@@ -866,7 +866,7 @@ static const struct sunxi_desc_pin sun4i_a10_pins[] = {
                  SUNXI_FUNCTION(0x4, "keypad"),        /* OUT4 */
                  SUNXI_FUNCTION(0x5, "mmc1"),          /* D0 */
                  SUNXI_FUNCTION(0x7, "csi1")),         /* PCLK */
-       SUNXI_PIN(SUNXI_PINCTRL_PIN_PH25,
+       SUNXI_PIN(SUNXI_PINCTRL_PIN(H, 25),
                  SUNXI_FUNCTION(0x0, "gpio_in"),
                  SUNXI_FUNCTION(0x1, "gpio_out"),
                  SUNXI_FUNCTION(0x2, "lcd1"),          /* DE */
@@ -874,7 +874,7 @@ static const struct sunxi_desc_pin sun4i_a10_pins[] = {
                  SUNXI_FUNCTION(0x4, "keypad"),        /* OUT5 */
                  SUNXI_FUNCTION(0x5, "mmc1"),          /* D1 */
                  SUNXI_FUNCTION(0x7, "csi1")),         /* FIELD */
-       SUNXI_PIN(SUNXI_PINCTRL_PIN_PH26,
+       SUNXI_PIN(SUNXI_PINCTRL_PIN(H, 26),
                  SUNXI_FUNCTION(0x0, "gpio_in"),
                  SUNXI_FUNCTION(0x1, "gpio_out"),
                  SUNXI_FUNCTION(0x2, "lcd1"),          /* HSYNC */
@@ -882,7 +882,7 @@ static const struct sunxi_desc_pin sun4i_a10_pins[] = {
                  SUNXI_FUNCTION(0x4, "keypad"),        /* OUT6 */
                  SUNXI_FUNCTION(0x5, "mmc1"),          /* D2 */
                  SUNXI_FUNCTION(0x7, "csi1")),         /* HSYNC */
-       SUNXI_PIN(SUNXI_PINCTRL_PIN_PH27,
+       SUNXI_PIN(SUNXI_PINCTRL_PIN(H, 27),
                  SUNXI_FUNCTION(0x0, "gpio_in"),
                  SUNXI_FUNCTION(0x1, "gpio_out"),
                  SUNXI_FUNCTION(0x2, "lcd1"),          /* VSYNC */
@@ -891,112 +891,112 @@ static const struct sunxi_desc_pin sun4i_a10_pins[] = {
                  SUNXI_FUNCTION(0x5, "mmc1"),          /* D3 */
                  SUNXI_FUNCTION(0x7, "csi1")),         /* VSYNC */
        /* Hole */
-       SUNXI_PIN(SUNXI_PINCTRL_PIN_PI0,
+       SUNXI_PIN(SUNXI_PINCTRL_PIN(I, 0),
                  SUNXI_FUNCTION(0x0, "gpio_in"),
                  SUNXI_FUNCTION(0x1, "gpio_out")),
-       SUNXI_PIN(SUNXI_PINCTRL_PIN_PI1,
+       SUNXI_PIN(SUNXI_PINCTRL_PIN(I, 1),
                  SUNXI_FUNCTION(0x0, "gpio_in"),
                  SUNXI_FUNCTION(0x1, "gpio_out")),
-       SUNXI_PIN(SUNXI_PINCTRL_PIN_PI2,
+       SUNXI_PIN(SUNXI_PINCTRL_PIN(I, 2),
                  SUNXI_FUNCTION(0x0, "gpio_in"),
                  SUNXI_FUNCTION(0x1, "gpio_out")),
-       SUNXI_PIN(SUNXI_PINCTRL_PIN_PI3,
+       SUNXI_PIN(SUNXI_PINCTRL_PIN(I, 3),
                  SUNXI_FUNCTION(0x0, "gpio_in"),
                  SUNXI_FUNCTION(0x1, "gpio_out"),
                  SUNXI_FUNCTION(0x2, "pwm")),          /* PWM1 */
-       SUNXI_PIN(SUNXI_PINCTRL_PIN_PI4,
+       SUNXI_PIN(SUNXI_PINCTRL_PIN(I, 4),
                  SUNXI_FUNCTION(0x0, "gpio_in"),
                  SUNXI_FUNCTION(0x1, "gpio_out"),
                  SUNXI_FUNCTION(0x2, "mmc3")),         /* CMD */
-       SUNXI_PIN(SUNXI_PINCTRL_PIN_PI5,
+       SUNXI_PIN(SUNXI_PINCTRL_PIN(I, 5),
                  SUNXI_FUNCTION(0x0, "gpio_in"),
                  SUNXI_FUNCTION(0x1, "gpio_out"),
                  SUNXI_FUNCTION(0x2, "mmc3")),         /* CLK */
-       SUNXI_PIN(SUNXI_PINCTRL_PIN_PI6,
+       SUNXI_PIN(SUNXI_PINCTRL_PIN(I, 6),
                  SUNXI_FUNCTION(0x0, "gpio_in"),
                  SUNXI_FUNCTION(0x1, "gpio_out"),
                  SUNXI_FUNCTION(0x2, "mmc3")),         /* D0 */
-       SUNXI_PIN(SUNXI_PINCTRL_PIN_PI7,
+       SUNXI_PIN(SUNXI_PINCTRL_PIN(I, 7),
                  SUNXI_FUNCTION(0x0, "gpio_in"),
                  SUNXI_FUNCTION(0x1, "gpio_out"),
                  SUNXI_FUNCTION(0x2, "mmc3")),         /* D1 */
-       SUNXI_PIN(SUNXI_PINCTRL_PIN_PI8,
+       SUNXI_PIN(SUNXI_PINCTRL_PIN(I, 8),
                  SUNXI_FUNCTION(0x0, "gpio_in"),
                  SUNXI_FUNCTION(0x1, "gpio_out"),
                  SUNXI_FUNCTION(0x2, "mmc3")),         /* D2 */
-       SUNXI_PIN(SUNXI_PINCTRL_PIN_PI9,
+       SUNXI_PIN(SUNXI_PINCTRL_PIN(I, 9),
                  SUNXI_FUNCTION(0x0, "gpio_in"),
                  SUNXI_FUNCTION(0x1, "gpio_out"),
                  SUNXI_FUNCTION(0x2, "mmc3")),         /* D3 */
-       SUNXI_PIN(SUNXI_PINCTRL_PIN_PI10,
+       SUNXI_PIN(SUNXI_PINCTRL_PIN(I, 10),
                  SUNXI_FUNCTION(0x0, "gpio_in"),
                  SUNXI_FUNCTION(0x1, "gpio_out"),
                  SUNXI_FUNCTION(0x2, "spi0"),          /* CS0 */
                  SUNXI_FUNCTION(0x3, "uart5"),         /* TX */
                  SUNXI_FUNCTION_IRQ(0x6, 22)),         /* EINT22 */
-       SUNXI_PIN(SUNXI_PINCTRL_PIN_PI11,
+       SUNXI_PIN(SUNXI_PINCTRL_PIN(I, 11),
                  SUNXI_FUNCTION(0x0, "gpio_in"),
                  SUNXI_FUNCTION(0x1, "gpio_out"),
                  SUNXI_FUNCTION(0x2, "spi0"),          /* CLK */
                  SUNXI_FUNCTION(0x3, "uart5"),         /* RX */
                  SUNXI_FUNCTION_IRQ(0x6, 23)),         /* EINT23 */
-       SUNXI_PIN(SUNXI_PINCTRL_PIN_PI12,
+       SUNXI_PIN(SUNXI_PINCTRL_PIN(I, 12),
                  SUNXI_FUNCTION(0x0, "gpio_in"),
                  SUNXI_FUNCTION(0x1, "gpio_out"),
                  SUNXI_FUNCTION(0x2, "spi0"),          /* MOSI */
                  SUNXI_FUNCTION(0x3, "uart6"),         /* TX */
                  SUNXI_FUNCTION_IRQ(0x6, 24)),         /* EINT24 */
-       SUNXI_PIN(SUNXI_PINCTRL_PIN_PI13,
+       SUNXI_PIN(SUNXI_PINCTRL_PIN(I, 13),
                  SUNXI_FUNCTION(0x0, "gpio_in"),
                  SUNXI_FUNCTION(0x1, "gpio_out"),
                  SUNXI_FUNCTION(0x2, "spi0"),          /* MISO */
                  SUNXI_FUNCTION(0x3, "uart6"),         /* RX */
                  SUNXI_FUNCTION_IRQ(0x6, 25)),         /* EINT25 */
-       SUNXI_PIN(SUNXI_PINCTRL_PIN_PI14,
+       SUNXI_PIN(SUNXI_PINCTRL_PIN(I, 14),
                  SUNXI_FUNCTION(0x0, "gpio_in"),
                  SUNXI_FUNCTION(0x1, "gpio_out"),
                  SUNXI_FUNCTION(0x2, "spi0"),          /* CS1 */
                  SUNXI_FUNCTION(0x3, "ps2"),           /* SCK1 */
                  SUNXI_FUNCTION(0x4, "timer4"),        /* TCLKIN0 */
                  SUNXI_FUNCTION_IRQ(0x6, 26)),         /* EINT26 */
-       SUNXI_PIN(SUNXI_PINCTRL_PIN_PI15,
+       SUNXI_PIN(SUNXI_PINCTRL_PIN(I, 15),
                  SUNXI_FUNCTION(0x0, "gpio_in"),
                  SUNXI_FUNCTION(0x1, "gpio_out"),
                  SUNXI_FUNCTION(0x2, "spi1"),          /* CS1 */
                  SUNXI_FUNCTION(0x3, "ps2"),           /* SDA1 */
                  SUNXI_FUNCTION(0x4, "timer5"),        /* TCLKIN1 */
                  SUNXI_FUNCTION_IRQ(0x6, 27)),         /* EINT27 */
-       SUNXI_PIN(SUNXI_PINCTRL_PIN_PI16,
+       SUNXI_PIN(SUNXI_PINCTRL_PIN(I, 16),
                  SUNXI_FUNCTION(0x0, "gpio_in"),
                  SUNXI_FUNCTION(0x1, "gpio_out"),
                  SUNXI_FUNCTION(0x2, "spi1"),          /* CS0 */
                  SUNXI_FUNCTION(0x3, "uart2"),         /* RTS */
                  SUNXI_FUNCTION_IRQ(0x6, 28)),         /* EINT28 */
-       SUNXI_PIN(SUNXI_PINCTRL_PIN_PI17,
+       SUNXI_PIN(SUNXI_PINCTRL_PIN(I, 17),
                  SUNXI_FUNCTION(0x0, "gpio_in"),
                  SUNXI_FUNCTION(0x1, "gpio_out"),
                  SUNXI_FUNCTION(0x2, "spi1"),          /* CLK */
                  SUNXI_FUNCTION(0x3, "uart2"),         /* CTS */
                  SUNXI_FUNCTION_IRQ(0x6, 29)),         /* EINT29 */
-       SUNXI_PIN(SUNXI_PINCTRL_PIN_PI18,
+       SUNXI_PIN(SUNXI_PINCTRL_PIN(I, 18),
                  SUNXI_FUNCTION(0x0, "gpio_in"),
                  SUNXI_FUNCTION(0x1, "gpio_out"),
                  SUNXI_FUNCTION(0x2, "spi1"),          /* MOSI */
                  SUNXI_FUNCTION(0x3, "uart2"),         /* TX */
                  SUNXI_FUNCTION_IRQ(0x6, 30)),         /* EINT30 */
-       SUNXI_PIN(SUNXI_PINCTRL_PIN_PI19,
+       SUNXI_PIN(SUNXI_PINCTRL_PIN(I, 19),
                  SUNXI_FUNCTION(0x0, "gpio_in"),
                  SUNXI_FUNCTION(0x1, "gpio_out"),
                  SUNXI_FUNCTION(0x2, "spi1"),          /* MISO */
                  SUNXI_FUNCTION(0x3, "uart2"),         /* RX */
                  SUNXI_FUNCTION_IRQ(0x6, 31)),         /* EINT31 */
-       SUNXI_PIN(SUNXI_PINCTRL_PIN_PI20,
+       SUNXI_PIN(SUNXI_PINCTRL_PIN(I, 20),
                  SUNXI_FUNCTION(0x0, "gpio_in"),
                  SUNXI_FUNCTION(0x1, "gpio_out"),
                  SUNXI_FUNCTION(0x2, "ps2"),           /* SCK0 */
                  SUNXI_FUNCTION(0x3, "uart7"),         /* TX */
                  SUNXI_FUNCTION(0x4, "hdmi")),         /* HSCL */
-       SUNXI_PIN(SUNXI_PINCTRL_PIN_PI21,
+       SUNXI_PIN(SUNXI_PINCTRL_PIN(I, 21),
                  SUNXI_FUNCTION(0x0, "gpio_in"),
                  SUNXI_FUNCTION(0x1, "gpio_out"),
                  SUNXI_FUNCTION(0x2, "ps2"),           /* SDA0 */
@@ -1005,637 +1005,637 @@ static const struct sunxi_desc_pin sun4i_a10_pins[] = {
 };
 
 static const struct sunxi_desc_pin sun5i_a10s_pins[] = {
-       SUNXI_PIN(SUNXI_PINCTRL_PIN_PA0,
+       SUNXI_PIN(SUNXI_PINCTRL_PIN(A, 0),
                  SUNXI_FUNCTION(0x0, "gpio_in"),
                  SUNXI_FUNCTION(0x1, "gpio_out"),
                  SUNXI_FUNCTION(0x2, "emac"),          /* ERXD3 */
                  SUNXI_FUNCTION(0x3, "ts0"),           /* CLK */
                  SUNXI_FUNCTION(0x5, "keypad")),       /* IN0 */
-       SUNXI_PIN(SUNXI_PINCTRL_PIN_PA1,
+       SUNXI_PIN(SUNXI_PINCTRL_PIN(A, 1),
                  SUNXI_FUNCTION(0x0, "gpio_in"),
                  SUNXI_FUNCTION(0x1, "gpio_out"),
                  SUNXI_FUNCTION(0x2, "emac"),          /* ERXD2 */
                  SUNXI_FUNCTION(0x3, "ts0"),           /* ERR */
                  SUNXI_FUNCTION(0x5, "keypad")),       /* IN1 */
-       SUNXI_PIN(SUNXI_PINCTRL_PIN_PA2,
+       SUNXI_PIN(SUNXI_PINCTRL_PIN(A, 2),
                  SUNXI_FUNCTION(0x0, "gpio_in"),
                  SUNXI_FUNCTION(0x1, "gpio_out"),
                  SUNXI_FUNCTION(0x2, "emac"),          /* ERXD1 */
                  SUNXI_FUNCTION(0x3, "ts0"),           /* SYNC */
                  SUNXI_FUNCTION(0x5, "keypad")),       /* IN2 */
-       SUNXI_PIN(SUNXI_PINCTRL_PIN_PA3,
+       SUNXI_PIN(SUNXI_PINCTRL_PIN(A, 3),
                  SUNXI_FUNCTION(0x0, "gpio_in"),
                  SUNXI_FUNCTION(0x1, "gpio_out"),
                  SUNXI_FUNCTION(0x2, "emac"),          /* ERXD0 */
                  SUNXI_FUNCTION(0x3, "ts0"),           /* DLVD */
                  SUNXI_FUNCTION(0x5, "keypad")),       /* IN3 */
-       SUNXI_PIN(SUNXI_PINCTRL_PIN_PA4,
+       SUNXI_PIN(SUNXI_PINCTRL_PIN(A, 4),
                  SUNXI_FUNCTION(0x0, "gpio_in"),
                  SUNXI_FUNCTION(0x1, "gpio_out"),
                  SUNXI_FUNCTION(0x2, "emac"),          /* ETXD3 */
                  SUNXI_FUNCTION(0x3, "ts0"),           /* D0 */
                  SUNXI_FUNCTION(0x5, "keypad")),       /* IN4 */
-       SUNXI_PIN(SUNXI_PINCTRL_PIN_PA5,
+       SUNXI_PIN(SUNXI_PINCTRL_PIN(A, 5),
                  SUNXI_FUNCTION(0x0, "gpio_in"),
                  SUNXI_FUNCTION(0x1, "gpio_out"),
                  SUNXI_FUNCTION(0x2, "emac"),          /* ETXD2 */
                  SUNXI_FUNCTION(0x3, "ts0"),           /* D1 */
                  SUNXI_FUNCTION(0x5, "keypad")),       /* IN5 */
-       SUNXI_PIN(SUNXI_PINCTRL_PIN_PA6,
+       SUNXI_PIN(SUNXI_PINCTRL_PIN(A, 6),
                  SUNXI_FUNCTION(0x0, "gpio_in"),
                  SUNXI_FUNCTION(0x1, "gpio_out"),
                  SUNXI_FUNCTION(0x2, "emac"),          /* ETXD1 */
                  SUNXI_FUNCTION(0x3, "ts0"),           /* D2 */
                  SUNXI_FUNCTION(0x5, "keypad")),       /* IN6 */
-       SUNXI_PIN(SUNXI_PINCTRL_PIN_PA7,
+       SUNXI_PIN(SUNXI_PINCTRL_PIN(A, 7),
                  SUNXI_FUNCTION(0x0, "gpio_in"),
                  SUNXI_FUNCTION(0x1, "gpio_out"),
                  SUNXI_FUNCTION(0x2, "emac"),          /* ETXD0 */
                  SUNXI_FUNCTION(0x3, "ts0"),           /* D3 */
                  SUNXI_FUNCTION(0x5, "keypad")),       /* IN7 */
-       SUNXI_PIN(SUNXI_PINCTRL_PIN_PA8,
+       SUNXI_PIN(SUNXI_PINCTRL_PIN(A, 8),
                  SUNXI_FUNCTION(0x0, "gpio_in"),
                  SUNXI_FUNCTION(0x1, "gpio_out"),
                  SUNXI_FUNCTION(0x2, "emac"),          /* ERXCK */
                  SUNXI_FUNCTION(0x3, "ts0"),           /* D4 */
                  SUNXI_FUNCTION(0x4, "uart1"),         /* DTR */
                  SUNXI_FUNCTION(0x5, "keypad")),       /* OUT0 */
-       SUNXI_PIN(SUNXI_PINCTRL_PIN_PA9,
+       SUNXI_PIN(SUNXI_PINCTRL_PIN(A, 9),
                  SUNXI_FUNCTION(0x0, "gpio_in"),
                  SUNXI_FUNCTION(0x1, "gpio_out"),
                  SUNXI_FUNCTION(0x2, "emac"),          /* ERXERR */
                  SUNXI_FUNCTION(0x3, "ts0"),           /* D5 */
                  SUNXI_FUNCTION(0x4, "uart1"),         /* DSR */
                  SUNXI_FUNCTION(0x5, "keypad")),       /* OUT1 */
-       SUNXI_PIN(SUNXI_PINCTRL_PIN_PA10,
+       SUNXI_PIN(SUNXI_PINCTRL_PIN(A, 10),
                  SUNXI_FUNCTION(0x0, "gpio_in"),
                  SUNXI_FUNCTION(0x1, "gpio_out"),
                  SUNXI_FUNCTION(0x2, "emac"),          /* ERXDV */
                  SUNXI_FUNCTION(0x3, "ts0"),           /* D6 */
                  SUNXI_FUNCTION(0x4, "uart1"),         /* DCD */
                  SUNXI_FUNCTION(0x5, "keypad")),       /* OUT2 */
-       SUNXI_PIN(SUNXI_PINCTRL_PIN_PA11,
+       SUNXI_PIN(SUNXI_PINCTRL_PIN(A, 11),
                  SUNXI_FUNCTION(0x0, "gpio_in"),
                  SUNXI_FUNCTION(0x1, "gpio_out"),
                  SUNXI_FUNCTION(0x2, "emac"),          /* EMDC */
                  SUNXI_FUNCTION(0x3, "ts0"),           /* D7 */
                  SUNXI_FUNCTION(0x4, "uart1"),         /* RING */
                  SUNXI_FUNCTION(0x5, "keypad")),       /* OUT3 */
-       SUNXI_PIN(SUNXI_PINCTRL_PIN_PA12,
+       SUNXI_PIN(SUNXI_PINCTRL_PIN(A, 12),
                  SUNXI_FUNCTION(0x0, "gpio_in"),
                  SUNXI_FUNCTION(0x1, "gpio_out"),
                  SUNXI_FUNCTION(0x2, "emac"),          /* EMDIO */
                  SUNXI_FUNCTION(0x3, "uart1"),         /* TX */
                  SUNXI_FUNCTION(0x5, "keypad")),       /* OUT4 */
-       SUNXI_PIN(SUNXI_PINCTRL_PIN_PA13,
+       SUNXI_PIN(SUNXI_PINCTRL_PIN(A, 13),
                  SUNXI_FUNCTION(0x0, "gpio_in"),
                  SUNXI_FUNCTION(0x1, "gpio_out"),
                  SUNXI_FUNCTION(0x2, "emac"),          /* ETXEN */
                  SUNXI_FUNCTION(0x3, "uart1"),         /* RX */
                  SUNXI_FUNCTION(0x5, "keypad")),       /* OUT5 */
-       SUNXI_PIN(SUNXI_PINCTRL_PIN_PA14,
+       SUNXI_PIN(SUNXI_PINCTRL_PIN(A, 14),
                  SUNXI_FUNCTION(0x0, "gpio_in"),
                  SUNXI_FUNCTION(0x1, "gpio_out"),
                  SUNXI_FUNCTION(0x2, "emac"),          /* ETXCK */
                  SUNXI_FUNCTION(0x3, "uart1"),         /* CTS */
                  SUNXI_FUNCTION(0x4, "uart3"),         /* TX */
                  SUNXI_FUNCTION(0x5, "keypad")),       /* OUT6 */
-       SUNXI_PIN(SUNXI_PINCTRL_PIN_PA15,
+       SUNXI_PIN(SUNXI_PINCTRL_PIN(A, 15),
                  SUNXI_FUNCTION(0x0, "gpio_in"),
                  SUNXI_FUNCTION(0x1, "gpio_out"),
                  SUNXI_FUNCTION(0x2, "emac"),          /* ECRS */
                  SUNXI_FUNCTION(0x3, "uart1"),         /* RTS */
                  SUNXI_FUNCTION(0x4, "uart3"),         /* RX */
                  SUNXI_FUNCTION(0x5, "keypad")),       /* OUT7 */
-       SUNXI_PIN(SUNXI_PINCTRL_PIN_PA16,
+       SUNXI_PIN(SUNXI_PINCTRL_PIN(A, 16),
                  SUNXI_FUNCTION(0x0, "gpio_in"),
                  SUNXI_FUNCTION(0x1, "gpio_out"),
                  SUNXI_FUNCTION(0x2, "emac"),          /* ECOL */
                  SUNXI_FUNCTION(0x3, "uart2")),        /* TX */
-       SUNXI_PIN(SUNXI_PINCTRL_PIN_PA17,
+       SUNXI_PIN(SUNXI_PINCTRL_PIN(A, 17),
                  SUNXI_FUNCTION(0x0, "gpio_in"),
                  SUNXI_FUNCTION(0x1, "gpio_out"),
                  SUNXI_FUNCTION(0x2, "emac"),          /* ETXERR */
                  SUNXI_FUNCTION(0x3, "uart2"),         /* RX */
                  SUNXI_FUNCTION_IRQ(0x6, 31)),         /* EINT31 */
        /* Hole */
-       SUNXI_PIN(SUNXI_PINCTRL_PIN_PB0,
+       SUNXI_PIN(SUNXI_PINCTRL_PIN(B, 0),
                  SUNXI_FUNCTION(0x0, "gpio_in"),
                  SUNXI_FUNCTION(0x1, "gpio_out"),
                  SUNXI_FUNCTION(0x2, "i2c0")),         /* SCK */
-       SUNXI_PIN(SUNXI_PINCTRL_PIN_PB1,
+       SUNXI_PIN(SUNXI_PINCTRL_PIN(B, 1),
                  SUNXI_FUNCTION(0x0, "gpio_in"),
                  SUNXI_FUNCTION(0x1, "gpio_out"),
                  SUNXI_FUNCTION(0x2, "i2c0")),         /* SDA */
-       SUNXI_PIN(SUNXI_PINCTRL_PIN_PB2,
+       SUNXI_PIN(SUNXI_PINCTRL_PIN(B, 2),
                  SUNXI_FUNCTION(0x0, "gpio_in"),
                  SUNXI_FUNCTION(0x1, "gpio_out"),
                  SUNXI_FUNCTION(0x2, "pwm"),           /* PWM0 */
                  SUNXI_FUNCTION_IRQ(0x6, 16)),         /* EINT16 */
-       SUNXI_PIN(SUNXI_PINCTRL_PIN_PB3,
+       SUNXI_PIN(SUNXI_PINCTRL_PIN(B, 3),
                  SUNXI_FUNCTION(0x0, "gpio_in"),
                  SUNXI_FUNCTION(0x1, "gpio_out"),
                  SUNXI_FUNCTION(0x2, "ir0"),           /* TX */
                  SUNXI_FUNCTION_IRQ(0x6, 17)),         /* EINT17 */
-       SUNXI_PIN(SUNXI_PINCTRL_PIN_PB4,
+       SUNXI_PIN(SUNXI_PINCTRL_PIN(B, 4),
                  SUNXI_FUNCTION(0x0, "gpio_in"),
                  SUNXI_FUNCTION(0x1, "gpio_out"),
                  SUNXI_FUNCTION(0x2, "ir0"),           /* RX */
                  SUNXI_FUNCTION_IRQ(0x6, 18)),         /* EINT18 */
-       SUNXI_PIN(SUNXI_PINCTRL_PIN_PB5,
+       SUNXI_PIN(SUNXI_PINCTRL_PIN(B, 5),
                  SUNXI_FUNCTION(0x0, "gpio_in"),
                  SUNXI_FUNCTION(0x1, "gpio_out"),
                  SUNXI_FUNCTION(0x2, "i2s"),           /* MCLK */
                  SUNXI_FUNCTION_IRQ(0x6, 19)),         /* EINT19 */
-       SUNXI_PIN(SUNXI_PINCTRL_PIN_PB6,
+       SUNXI_PIN(SUNXI_PINCTRL_PIN(B, 6),
                  SUNXI_FUNCTION(0x0, "gpio_in"),
                  SUNXI_FUNCTION(0x1, "gpio_out"),
                  SUNXI_FUNCTION(0x2, "i2s"),           /* BCLK */
                  SUNXI_FUNCTION_IRQ(0x6, 20)),         /* EINT20 */
-       SUNXI_PIN(SUNXI_PINCTRL_PIN_PB7,
+       SUNXI_PIN(SUNXI_PINCTRL_PIN(B, 7),
                  SUNXI_FUNCTION(0x0, "gpio_in"),
                  SUNXI_FUNCTION(0x1, "gpio_out"),
                  SUNXI_FUNCTION(0x2, "i2s"),           /* LRCK */
                  SUNXI_FUNCTION_IRQ(0x6, 21)),         /* EINT21 */
-       SUNXI_PIN(SUNXI_PINCTRL_PIN_PB8,
+       SUNXI_PIN(SUNXI_PINCTRL_PIN(B, 8),
                  SUNXI_FUNCTION(0x0, "gpio_in"),
                  SUNXI_FUNCTION(0x1, "gpio_out"),
                  SUNXI_FUNCTION(0x2, "i2s"),           /* DO */
                  SUNXI_FUNCTION_IRQ(0x6, 22)),         /* EINT22 */
-       SUNXI_PIN(SUNXI_PINCTRL_PIN_PB9,
+       SUNXI_PIN(SUNXI_PINCTRL_PIN(B, 9),
                  SUNXI_FUNCTION(0x0, "gpio_in"),
                  SUNXI_FUNCTION(0x1, "gpio_out"),
                  SUNXI_FUNCTION(0x2, "i2s"),           /* DI */
                  SUNXI_FUNCTION_IRQ(0x6, 23)),         /* EINT23 */
-       SUNXI_PIN(SUNXI_PINCTRL_PIN_PB10,
+       SUNXI_PIN(SUNXI_PINCTRL_PIN(B, 10),
                  SUNXI_FUNCTION(0x0, "gpio_in"),
                  SUNXI_FUNCTION(0x1, "gpio_out"),
                  SUNXI_FUNCTION(0x2, "spi2"),          /* CS1 */
                  SUNXI_FUNCTION_IRQ(0x6, 24)),         /* EINT24 */
-       SUNXI_PIN(SUNXI_PINCTRL_PIN_PB11,
+       SUNXI_PIN(SUNXI_PINCTRL_PIN(B, 11),
                  SUNXI_FUNCTION(0x0, "gpio_in"),
                  SUNXI_FUNCTION(0x1, "gpio_out"),
                  SUNXI_FUNCTION(0x2, "spi2"),          /* CS0 */
                  SUNXI_FUNCTION(0x3, "jtag"),          /* MS0 */
                  SUNXI_FUNCTION_IRQ(0x6, 25)),         /* EINT25 */
-       SUNXI_PIN(SUNXI_PINCTRL_PIN_PB12,
+       SUNXI_PIN(SUNXI_PINCTRL_PIN(B, 12),
                  SUNXI_FUNCTION(0x0, "gpio_in"),
                  SUNXI_FUNCTION(0x1, "gpio_out"),
                  SUNXI_FUNCTION(0x2, "spi2"),          /* CLK */
                  SUNXI_FUNCTION(0x3, "jtag"),          /* CK0 */
                  SUNXI_FUNCTION_IRQ(0x6, 26)),         /* EINT26 */
-       SUNXI_PIN(SUNXI_PINCTRL_PIN_PB13,
+       SUNXI_PIN(SUNXI_PINCTRL_PIN(B, 13),
                  SUNXI_FUNCTION(0x0, "gpio_in"),
                  SUNXI_FUNCTION(0x1, "gpio_out"),
                  SUNXI_FUNCTION(0x2, "spi2"),          /* MOSI */
                  SUNXI_FUNCTION(0x3, "jtag"),          /* DO0 */
                  SUNXI_FUNCTION_IRQ(0x6, 27)),         /* EINT27 */
-       SUNXI_PIN(SUNXI_PINCTRL_PIN_PB14,
+       SUNXI_PIN(SUNXI_PINCTRL_PIN(B, 14),
                  SUNXI_FUNCTION(0x0, "gpio_in"),
                  SUNXI_FUNCTION(0x1, "gpio_out"),
                  SUNXI_FUNCTION(0x2, "spi2"),          /* MISO */
                  SUNXI_FUNCTION(0x3, "jtag"),          /* DI0 */
                  SUNXI_FUNCTION_IRQ(0x6, 28)),         /* EINT28 */
-       SUNXI_PIN(SUNXI_PINCTRL_PIN_PB15,
+       SUNXI_PIN(SUNXI_PINCTRL_PIN(B, 15),
                  SUNXI_FUNCTION(0x0, "gpio_in"),
                  SUNXI_FUNCTION(0x1, "gpio_out"),
                  SUNXI_FUNCTION(0x2, "i2c1")),         /* SCK */
-       SUNXI_PIN(SUNXI_PINCTRL_PIN_PB16,
+       SUNXI_PIN(SUNXI_PINCTRL_PIN(B, 16),
                  SUNXI_FUNCTION(0x0, "gpio_in"),
                  SUNXI_FUNCTION(0x1, "gpio_out"),
                  SUNXI_FUNCTION(0x2, "i2c1")),         /* SDA */
-       SUNXI_PIN(SUNXI_PINCTRL_PIN_PB17,
+       SUNXI_PIN(SUNXI_PINCTRL_PIN(B, 17),
                  SUNXI_FUNCTION(0x0, "gpio_in"),
                  SUNXI_FUNCTION(0x1, "gpio_out"),
                  SUNXI_FUNCTION(0x2, "i2c2")),         /* SCK */
-       SUNXI_PIN(SUNXI_PINCTRL_PIN_PB18,
+       SUNXI_PIN(SUNXI_PINCTRL_PIN(B, 18),
                  SUNXI_FUNCTION(0x0, "gpio_in"),
                  SUNXI_FUNCTION(0x1, "gpio_out"),
                  SUNXI_FUNCTION(0x2, "i2c2")),         /* SDA */
-       SUNXI_PIN(SUNXI_PINCTRL_PIN_PB19,
+       SUNXI_PIN(SUNXI_PINCTRL_PIN(B, 19),
                  SUNXI_FUNCTION(0x0, "gpio_in"),
                  SUNXI_FUNCTION(0x1, "gpio_out"),
                  SUNXI_FUNCTION(0x2, "uart0"),         /* TX */
                  SUNXI_FUNCTION_IRQ(0x6, 29)),         /* EINT29 */
-       SUNXI_PIN(SUNXI_PINCTRL_PIN_PB20,
+       SUNXI_PIN(SUNXI_PINCTRL_PIN(B, 20),
                  SUNXI_FUNCTION(0x0, "gpio_in"),
                  SUNXI_FUNCTION(0x1, "gpio_out"),
                  SUNXI_FUNCTION(0x2, "uart0"),         /* RX */
                  SUNXI_FUNCTION_IRQ(0x6, 30)),         /* EINT30 */
        /* Hole */
-       SUNXI_PIN(SUNXI_PINCTRL_PIN_PC0,
+       SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 0),
                  SUNXI_FUNCTION(0x0, "gpio_in"),
                  SUNXI_FUNCTION(0x1, "gpio_out"),
                  SUNXI_FUNCTION(0x2, "nand0"),         /* NWE */
                  SUNXI_FUNCTION(0x3, "spi0")),         /* MOSI */
-       SUNXI_PIN(SUNXI_PINCTRL_PIN_PC1,
+       SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 1),
                  SUNXI_FUNCTION(0x0, "gpio_in"),
                  SUNXI_FUNCTION(0x1, "gpio_out"),
                  SUNXI_FUNCTION(0x2, "nand0"),         /* NALE */
                  SUNXI_FUNCTION(0x3, "spi0")),         /* MISO */
-       SUNXI_PIN(SUNXI_PINCTRL_PIN_PC2,
+       SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 2),
                  SUNXI_FUNCTION(0x0, "gpio_in"),
                  SUNXI_FUNCTION(0x1, "gpio_out"),
                  SUNXI_FUNCTION(0x2, "nand0"),         /* NCLE */
                  SUNXI_FUNCTION(0x3, "spi0")),         /* SCK */
-       SUNXI_PIN(SUNXI_PINCTRL_PIN_PC3,
+       SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 3),
                  SUNXI_FUNCTION(0x0, "gpio_in"),
                  SUNXI_FUNCTION(0x1, "gpio_out"),
                  SUNXI_FUNCTION(0x2, "nand0"),         /* NCE1 */
                  SUNXI_FUNCTION(0x3, "spi0")),         /* CS0 */
-       SUNXI_PIN(SUNXI_PINCTRL_PIN_PC4,
+       SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 4),
                  SUNXI_FUNCTION(0x0, "gpio_in"),
                  SUNXI_FUNCTION(0x1, "gpio_out"),
                  SUNXI_FUNCTION(0x2, "nand0")),        /* NCE0 */
-       SUNXI_PIN(SUNXI_PINCTRL_PIN_PC5,
+       SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 5),
                  SUNXI_FUNCTION(0x0, "gpio_in"),
                  SUNXI_FUNCTION(0x1, "gpio_out"),
                  SUNXI_FUNCTION(0x2, "nand0")),        /* NRE */
-       SUNXI_PIN(SUNXI_PINCTRL_PIN_PC6,
+       SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 6),
                  SUNXI_FUNCTION(0x0, "gpio_in"),
                  SUNXI_FUNCTION(0x1, "gpio_out"),
                  SUNXI_FUNCTION(0x2, "nand0"),         /* NRB0 */
                  SUNXI_FUNCTION(0x3, "mmc2")),         /* CMD */
-       SUNXI_PIN(SUNXI_PINCTRL_PIN_PC7,
+       SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 7),
                  SUNXI_FUNCTION(0x0, "gpio_in"),
                  SUNXI_FUNCTION(0x1, "gpio_out"),
                  SUNXI_FUNCTION(0x2, "nand0"),         /* NRB1 */
                  SUNXI_FUNCTION(0x3, "mmc2")),         /* CLK */
-       SUNXI_PIN(SUNXI_PINCTRL_PIN_PC8,
+       SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 8),
                  SUNXI_FUNCTION(0x0, "gpio_in"),
                  SUNXI_FUNCTION(0x1, "gpio_out"),
                  SUNXI_FUNCTION(0x2, "nand0"),         /* NDQ0 */
                  SUNXI_FUNCTION(0x3, "mmc2")),         /* D0 */
-       SUNXI_PIN(SUNXI_PINCTRL_PIN_PC9,
+       SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 9),
                  SUNXI_FUNCTION(0x0, "gpio_in"),
                  SUNXI_FUNCTION(0x1, "gpio_out"),
                  SUNXI_FUNCTION(0x2, "nand0"),         /* NDQ1 */
                  SUNXI_FUNCTION(0x3, "mmc2")),         /* D1 */
-       SUNXI_PIN(SUNXI_PINCTRL_PIN_PC10,
+       SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 10),
                  SUNXI_FUNCTION(0x0, "gpio_in"),
                  SUNXI_FUNCTION(0x1, "gpio_out"),
                  SUNXI_FUNCTION(0x2, "nand0"),         /* NDQ2 */
                  SUNXI_FUNCTION(0x3, "mmc2")),         /* D2 */
-       SUNXI_PIN(SUNXI_PINCTRL_PIN_PC11,
+       SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 11),
                  SUNXI_FUNCTION(0x0, "gpio_in"),
                  SUNXI_FUNCTION(0x1, "gpio_out"),
                  SUNXI_FUNCTION(0x2, "nand0"),         /* NDQ3 */
                  SUNXI_FUNCTION(0x3, "mmc2")),         /* D3 */
-       SUNXI_PIN(SUNXI_PINCTRL_PIN_PC12,
+       SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 12),
                  SUNXI_FUNCTION(0x0, "gpio_in"),
                  SUNXI_FUNCTION(0x1, "gpio_out"),
                  SUNXI_FUNCTION(0x2, "nand0"),         /* NDQ4 */
                  SUNXI_FUNCTION(0x3, "mmc2")),         /* D4 */
-       SUNXI_PIN(SUNXI_PINCTRL_PIN_PC13,
+       SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 13),
                  SUNXI_FUNCTION(0x0, "gpio_in"),
                  SUNXI_FUNCTION(0x1, "gpio_out"),
                  SUNXI_FUNCTION(0x2, "nand0"),         /* NDQ5 */
                  SUNXI_FUNCTION(0x3, "mmc2")),         /* D5 */
-       SUNXI_PIN(SUNXI_PINCTRL_PIN_PC14,
+       SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 14),
                  SUNXI_FUNCTION(0x0, "gpio_in"),
                  SUNXI_FUNCTION(0x1, "gpio_out"),
                  SUNXI_FUNCTION(0x2, "nand0"),         /* NDQ6 */
                  SUNXI_FUNCTION(0x3, "mmc2")),         /* D6 */
-       SUNXI_PIN(SUNXI_PINCTRL_PIN_PC15,
+       SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 15),
                  SUNXI_FUNCTION(0x0, "gpio_in"),
                  SUNXI_FUNCTION(0x1, "gpio_out"),
                  SUNXI_FUNCTION(0x2, "nand0"),         /* NDQ7 */
                  SUNXI_FUNCTION(0x3, "mmc2")),         /* D7 */
-       SUNXI_PIN(SUNXI_PINCTRL_PIN_PC16,
+       SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 16),
                  SUNXI_FUNCTION(0x0, "gpio_in"),
                  SUNXI_FUNCTION(0x1, "gpio_out"),
                  SUNXI_FUNCTION(0x2, "nand0"),         /* NWP */
                  SUNXI_FUNCTION(0x4, "uart3")),        /* TX */
-       SUNXI_PIN(SUNXI_PINCTRL_PIN_PC17,
+       SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 17),
                  SUNXI_FUNCTION(0x0, "gpio_in"),
                  SUNXI_FUNCTION(0x1, "gpio_out"),
                  SUNXI_FUNCTION(0x2, "nand0"),         /* NCE2 */
                  SUNXI_FUNCTION(0x4, "uart3")),        /* RX */
-       SUNXI_PIN(SUNXI_PINCTRL_PIN_PC18,
+       SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 18),
                  SUNXI_FUNCTION(0x0, "gpio_in"),
                  SUNXI_FUNCTION(0x1, "gpio_out"),
                  SUNXI_FUNCTION(0x2, "nand0"),         /* NCE3 */
                  SUNXI_FUNCTION(0x3, "uart2"),         /* TX */
                  SUNXI_FUNCTION(0x4, "uart3")),        /* CTS */
-       SUNXI_PIN(SUNXI_PINCTRL_PIN_PC19,
+       SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 19),
                  SUNXI_FUNCTION(0x0, "gpio_in"),
                  SUNXI_FUNCTION(0x1, "gpio_out"),
                  SUNXI_FUNCTION(0x2, "nand0"),         /* NCE4 */
                  SUNXI_FUNCTION(0x3, "uart2"),         /* RX */
                  SUNXI_FUNCTION(0x4, "uart3")),        /* RTS */
        /* Hole */
-       SUNXI_PIN(SUNXI_PINCTRL_PIN_PD0,
+       SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 0),
                  SUNXI_FUNCTION(0x0, "gpio_in"),
                  SUNXI_FUNCTION(0x1, "gpio_out"),
                  SUNXI_FUNCTION(0x2, "lcd0")),         /* D0 */
-       SUNXI_PIN(SUNXI_PINCTRL_PIN_PD1,
+       SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 1),
                  SUNXI_FUNCTION(0x0, "gpio_in"),
                  SUNXI_FUNCTION(0x1, "gpio_out"),
                  SUNXI_FUNCTION(0x2, "lcd0")),         /* D1 */
-       SUNXI_PIN(SUNXI_PINCTRL_PIN_PD2,
+       SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 2),
                  SUNXI_FUNCTION(0x0, "gpio_in"),
                  SUNXI_FUNCTION(0x1, "gpio_out"),
                  SUNXI_FUNCTION(0x2, "lcd0"),          /* D2 */
                  SUNXI_FUNCTION(0x3, "uart2")),        /* TX */
-       SUNXI_PIN(SUNXI_PINCTRL_PIN_PD3,
+       SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 3),
                  SUNXI_FUNCTION(0x0, "gpio_in"),
                  SUNXI_FUNCTION(0x1, "gpio_out"),
                  SUNXI_FUNCTION(0x2, "lcd0"),          /* D3 */
                  SUNXI_FUNCTION(0x3, "uart2")),        /* RX */
-       SUNXI_PIN(SUNXI_PINCTRL_PIN_PD4,
+       SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 4),
                  SUNXI_FUNCTION(0x0, "gpio_in"),
                  SUNXI_FUNCTION(0x1, "gpio_out"),
                  SUNXI_FUNCTION(0x2, "lcd0"),          /* D4 */
                  SUNXI_FUNCTION(0x3, "uart2")),        /* CTS */
-       SUNXI_PIN(SUNXI_PINCTRL_PIN_PD5,
+       SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 5),
                  SUNXI_FUNCTION(0x0, "gpio_in"),
                  SUNXI_FUNCTION(0x1, "gpio_out"),
                  SUNXI_FUNCTION(0x2, "lcd0"),          /* D5 */
                  SUNXI_FUNCTION(0x3, "uart2")),        /* RTS */
-       SUNXI_PIN(SUNXI_PINCTRL_PIN_PD6,
+       SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 6),
                  SUNXI_FUNCTION(0x0, "gpio_in"),
                  SUNXI_FUNCTION(0x1, "gpio_out"),
                  SUNXI_FUNCTION(0x2, "lcd0"),          /* D6 */
                  SUNXI_FUNCTION(0x3, "emac")),         /* ECRS */
-       SUNXI_PIN(SUNXI_PINCTRL_PIN_PD7,
+       SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 7),
                  SUNXI_FUNCTION(0x0, "gpio_in"),
                  SUNXI_FUNCTION(0x1, "gpio_out"),
                  SUNXI_FUNCTION(0x2, "lcd0"),          /* D7 */
                  SUNXI_FUNCTION(0x3, "emac")),         /* ECOL */
-       SUNXI_PIN(SUNXI_PINCTRL_PIN_PD8,
+       SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 8),
                  SUNXI_FUNCTION(0x0, "gpio_in"),
                  SUNXI_FUNCTION(0x1, "gpio_out"),
                  SUNXI_FUNCTION(0x2, "lcd0")),         /* D8 */
-       SUNXI_PIN(SUNXI_PINCTRL_PIN_PD9,
+       SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 9),
                  SUNXI_FUNCTION(0x0, "gpio_in"),
                  SUNXI_FUNCTION(0x1, "gpio_out"),
                  SUNXI_FUNCTION(0x2, "lcd0")),         /* D9 */
-       SUNXI_PIN(SUNXI_PINCTRL_PIN_PD10,
+       SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 10),
                  SUNXI_FUNCTION(0x0, "gpio_in"),
                  SUNXI_FUNCTION(0x1, "gpio_out"),
                  SUNXI_FUNCTION(0x2, "lcd0"),          /* D10 */
                  SUNXI_FUNCTION(0x3, "emac")),         /* ERXD0 */
-       SUNXI_PIN(SUNXI_PINCTRL_PIN_PD11,
+       SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 11),
                  SUNXI_FUNCTION(0x0, "gpio_in"),
                  SUNXI_FUNCTION(0x1, "gpio_out"),
                  SUNXI_FUNCTION(0x2, "lcd0"),          /* D11 */
                  SUNXI_FUNCTION(0x3, "emac")),         /* ERXD1 */
-       SUNXI_PIN(SUNXI_PINCTRL_PIN_PD12,
+       SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 12),
                  SUNXI_FUNCTION(0x0, "gpio_in"),
                  SUNXI_FUNCTION(0x1, "gpio_out"),
                  SUNXI_FUNCTION(0x2, "lcd0"),          /* D12 */
                  SUNXI_FUNCTION(0x3, "emac")),         /* ERXD2 */
-       SUNXI_PIN(SUNXI_PINCTRL_PIN_PD13,
+       SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 13),
                  SUNXI_FUNCTION(0x0, "gpio_in"),
                  SUNXI_FUNCTION(0x1, "gpio_out"),
                  SUNXI_FUNCTION(0x2, "lcd0"),          /* D13 */
                  SUNXI_FUNCTION(0x3, "emac")),         /* ERXD3 */
-       SUNXI_PIN(SUNXI_PINCTRL_PIN_PD14,
+       SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 14),
                  SUNXI_FUNCTION(0x0, "gpio_in"),
                  SUNXI_FUNCTION(0x1, "gpio_out"),
                  SUNXI_FUNCTION(0x2, "lcd0"),          /* D14 */
                  SUNXI_FUNCTION(0x3, "emac")),         /* ERXCK */
-       SUNXI_PIN(SUNXI_PINCTRL_PIN_PD15,
+       SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 15),
                  SUNXI_FUNCTION(0x0, "gpio_in"),
                  SUNXI_FUNCTION(0x1, "gpio_out"),
                  SUNXI_FUNCTION(0x2, "lcd0"),          /* D15 */
                  SUNXI_FUNCTION(0x3, "emac")),         /* ERXERR */
-       SUNXI_PIN(SUNXI_PINCTRL_PIN_PD16,
+       SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 16),
                  SUNXI_FUNCTION(0x0, "gpio_in"),
                  SUNXI_FUNCTION(0x1, "gpio_out"),
                  SUNXI_FUNCTION(0x2, "lcd0")),         /* D16 */
-       SUNXI_PIN(SUNXI_PINCTRL_PIN_PD17,
+       SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 17),
                  SUNXI_FUNCTION(0x0, "gpio_in"),
                  SUNXI_FUNCTION(0x1, "gpio_out"),
                  SUNXI_FUNCTION(0x2, "lcd0")),         /* D17 */
-       SUNXI_PIN(SUNXI_PINCTRL_PIN_PD18,
+       SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 18),
                  SUNXI_FUNCTION(0x0, "gpio_in"),
                  SUNXI_FUNCTION(0x1, "gpio_out"),
                  SUNXI_FUNCTION(0x2, "lcd0"),          /* D18 */
                  SUNXI_FUNCTION(0x3, "emac")),         /* ERXDV */
-       SUNXI_PIN(SUNXI_PINCTRL_PIN_PD19,
+       SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 19),
                  SUNXI_FUNCTION(0x0, "gpio_in"),
                  SUNXI_FUNCTION(0x1, "gpio_out"),
                  SUNXI_FUNCTION(0x2, "lcd0"),          /* D19 */
                  SUNXI_FUNCTION(0x3, "emac")),         /* ETXD0 */
-       SUNXI_PIN(SUNXI_PINCTRL_PIN_PD20,
+       SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 20),
                  SUNXI_FUNCTION(0x0, "gpio_in"),
                  SUNXI_FUNCTION(0x1, "gpio_out"),
                  SUNXI_FUNCTION(0x2, "lcd0"),          /* D20 */
                  SUNXI_FUNCTION(0x3, "emac")),         /* ETXD1 */
-       SUNXI_PIN(SUNXI_PINCTRL_PIN_PD21,
+       SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 21),
                  SUNXI_FUNCTION(0x0, "gpio_in"),
                  SUNXI_FUNCTION(0x1, "gpio_out"),
                  SUNXI_FUNCTION(0x2, "lcd0"),          /* D21 */
                  SUNXI_FUNCTION(0x3, "emac")),         /* ETXD2 */
-       SUNXI_PIN(SUNXI_PINCTRL_PIN_PD22,
+       SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 22),
                  SUNXI_FUNCTION(0x0, "gpio_in"),
                  SUNXI_FUNCTION(0x1, "gpio_out"),
                  SUNXI_FUNCTION(0x2, "lcd0"),          /* D22 */
                  SUNXI_FUNCTION(0x3, "emac")),         /* ETXD3 */
-       SUNXI_PIN(SUNXI_PINCTRL_PIN_PD23,
+       SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 23),
                  SUNXI_FUNCTION(0x0, "gpio_in"),
                  SUNXI_FUNCTION(0x1, "gpio_out"),
                  SUNXI_FUNCTION(0x2, "lcd0"),          /* D23 */
                  SUNXI_FUNCTION(0x3, "emac")),         /* ETXEN */
-       SUNXI_PIN(SUNXI_PINCTRL_PIN_PD24,
+       SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 24),
                  SUNXI_FUNCTION(0x0, "gpio_in"),
                  SUNXI_FUNCTION(0x1, "gpio_out"),
                  SUNXI_FUNCTION(0x2, "lcd0"),          /* CLK */
                  SUNXI_FUNCTION(0x3, "emac")),         /* ETXCK */
-       SUNXI_PIN(SUNXI_PINCTRL_PIN_PD25,
+       SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 25),
                  SUNXI_FUNCTION(0x0, "gpio_in"),
                  SUNXI_FUNCTION(0x1, "gpio_out"),
                  SUNXI_FUNCTION(0x2, "lcd0"),          /* DE */
                  SUNXI_FUNCTION(0x3, "emac")),         /* ETXERR */
-       SUNXI_PIN(SUNXI_PINCTRL_PIN_PD26,
+       SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 26),
                  SUNXI_FUNCTION(0x0, "gpio_in"),
                  SUNXI_FUNCTION(0x1, "gpio_out"),
                  SUNXI_FUNCTION(0x2, "lcd0"),          /* HSYNC */
                  SUNXI_FUNCTION(0x3, "emac")),         /* EMDC */
-       SUNXI_PIN(SUNXI_PINCTRL_PIN_PD27,
+       SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 27),
                  SUNXI_FUNCTION(0x0, "gpio_in"),
                  SUNXI_FUNCTION(0x1, "gpio_out"),
                  SUNXI_FUNCTION(0x2, "lcd0"),          /* VSYNC */
                  SUNXI_FUNCTION(0x3, "emac")),         /* EMDIO */
        /* Hole */
-       SUNXI_PIN(SUNXI_PINCTRL_PIN_PE0,
+       SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 0),
                  SUNXI_FUNCTION(0x0, "gpio_in"),
                  SUNXI_FUNCTION(0x2, "ts0"),           /* CLK */
                  SUNXI_FUNCTION(0x3, "csi0"),          /* PCK */
                  SUNXI_FUNCTION(0x4, "spi2"),          /* CS0 */
                  SUNXI_FUNCTION_IRQ(0x6, 14)),         /* EINT14 */
-       SUNXI_PIN(SUNXI_PINCTRL_PIN_PE1,
+       SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 1),
                  SUNXI_FUNCTION(0x0, "gpio_in"),
                  SUNXI_FUNCTION(0x2, "ts0"),           /* ERR */
                  SUNXI_FUNCTION(0x3, "csi0"),          /* CK */
                  SUNXI_FUNCTION(0x4, "spi2"),          /* CLK */
                  SUNXI_FUNCTION_IRQ(0x6, 15)),         /* EINT15 */
-       SUNXI_PIN(SUNXI_PINCTRL_PIN_PE2,
+       SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 2),
                  SUNXI_FUNCTION(0x0, "gpio_in"),
                  SUNXI_FUNCTION(0x2, "ts0"),           /* SYNC */
                  SUNXI_FUNCTION(0x3, "csi0"),          /* HSYNC */
                  SUNXI_FUNCTION(0x4, "spi2")),         /* MOSI */
-       SUNXI_PIN(SUNXI_PINCTRL_PIN_PE3,
+       SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 3),
                  SUNXI_FUNCTION(0x0, "gpio_in"),
                  SUNXI_FUNCTION(0x1, "gpio_out"),
                  SUNXI_FUNCTION(0x2, "ts0"),           /* DVLD */
                  SUNXI_FUNCTION(0x3, "csi0"),          /* VSYNC */
                  SUNXI_FUNCTION(0x4, "spi2")),         /* MISO */
-       SUNXI_PIN(SUNXI_PINCTRL_PIN_PE4,
+       SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 4),
                  SUNXI_FUNCTION(0x0, "gpio_in"),
                  SUNXI_FUNCTION(0x1, "gpio_out"),
                  SUNXI_FUNCTION(0x2, "ts0"),           /* D0 */
                  SUNXI_FUNCTION(0x3, "csi0"),          /* D0 */
                  SUNXI_FUNCTION(0x4, "mmc2")),         /* D0 */
-       SUNXI_PIN(SUNXI_PINCTRL_PIN_PE5,
+       SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 5),
                  SUNXI_FUNCTION(0x0, "gpio_in"),
                  SUNXI_FUNCTION(0x1, "gpio_out"),
                  SUNXI_FUNCTION(0x2, "ts0"),           /* D1 */
                  SUNXI_FUNCTION(0x3, "csi0"),          /* D1 */
                  SUNXI_FUNCTION(0x4, "mmc2")),         /* D1 */
-       SUNXI_PIN(SUNXI_PINCTRL_PIN_PE6,
+       SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 6),
                  SUNXI_FUNCTION(0x0, "gpio_in"),
                  SUNXI_FUNCTION(0x1, "gpio_out"),
                  SUNXI_FUNCTION(0x2, "ts0"),           /* D2 */
                  SUNXI_FUNCTION(0x3, "csi0"),          /* D2 */
                  SUNXI_FUNCTION(0x4, "mmc2")),         /* D2 */
-       SUNXI_PIN(SUNXI_PINCTRL_PIN_PE7,
+       SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 7),
                  SUNXI_FUNCTION(0x0, "gpio_in"),
                  SUNXI_FUNCTION(0x1, "gpio_out"),
                  SUNXI_FUNCTION(0x2, "ts0"),           /* D3 */
                  SUNXI_FUNCTION(0x3, "csi0"),          /* D3 */
                  SUNXI_FUNCTION(0x4, "mmc2")),         /* D3 */
-       SUNXI_PIN(SUNXI_PINCTRL_PIN_PE8,
+       SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 8),
                  SUNXI_FUNCTION(0x0, "gpio_in"),
                  SUNXI_FUNCTION(0x1, "gpio_out"),
                  SUNXI_FUNCTION(0x2, "ts0"),           /* D4 */
                  SUNXI_FUNCTION(0x3, "csi0"),          /* D4 */
                  SUNXI_FUNCTION(0x4, "mmc2")),         /* CMD */
-       SUNXI_PIN(SUNXI_PINCTRL_PIN_PE9,
+       SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 9),
                  SUNXI_FUNCTION(0x0, "gpio_in"),
                  SUNXI_FUNCTION(0x1, "gpio_out"),
                  SUNXI_FUNCTION(0x2, "ts0"),           /* D5 */
                  SUNXI_FUNCTION(0x3, "csi0"),          /* D5 */
                  SUNXI_FUNCTION(0x4, "mmc2")),         /* CLK */
-       SUNXI_PIN(SUNXI_PINCTRL_PIN_PE10,
+       SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 10),
                  SUNXI_FUNCTION(0x0, "gpio_in"),
                  SUNXI_FUNCTION(0x1, "gpio_out"),
                  SUNXI_FUNCTION(0x2, "ts0"),           /* D6 */
                  SUNXI_FUNCTION(0x3, "csi0"),          /* D6 */
                  SUNXI_FUNCTION(0x4, "uart1")),        /* TX */
-       SUNXI_PIN(SUNXI_PINCTRL_PIN_PE11,
+       SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 11),
                  SUNXI_FUNCTION(0x0, "gpio_in"),
                  SUNXI_FUNCTION(0x1, "gpio_out"),
                  SUNXI_FUNCTION(0x2, "ts0"),           /* D7 */
                  SUNXI_FUNCTION(0x3, "csi0"),          /* D7 */
                  SUNXI_FUNCTION(0x4, "uart1")),        /* RX */
        /* Hole */
-       SUNXI_PIN(SUNXI_PINCTRL_PIN_PF0,
+       SUNXI_PIN(SUNXI_PINCTRL_PIN(F, 0),
                  SUNXI_FUNCTION(0x0, "gpio_in"),
                  SUNXI_FUNCTION(0x1, "gpio_out"),
                  SUNXI_FUNCTION(0x2, "mmc0"),          /* D1 */
                  SUNXI_FUNCTION(0x4, "jtag")),         /* MS1 */
-       SUNXI_PIN(SUNXI_PINCTRL_PIN_PF1,
+       SUNXI_PIN(SUNXI_PINCTRL_PIN(F, 1),
                  SUNXI_FUNCTION(0x0, "gpio_in"),
                  SUNXI_FUNCTION(0x1, "gpio_out"),
                  SUNXI_FUNCTION(0x2, "mmc0"),          /* D0 */
                  SUNXI_FUNCTION(0x4, "jtag")),         /* DI1 */
-       SUNXI_PIN(SUNXI_PINCTRL_PIN_PF2,
+       SUNXI_PIN(SUNXI_PINCTRL_PIN(F, 2),
                  SUNXI_FUNCTION(0x0, "gpio_in"),
                  SUNXI_FUNCTION(0x1, "gpio_out"),
                  SUNXI_FUNCTION(0x2, "mmc0"),          /* CLK */
                  SUNXI_FUNCTION(0x4, "uart0")),        /* TX */
-       SUNXI_PIN(SUNXI_PINCTRL_PIN_PF3,
+       SUNXI_PIN(SUNXI_PINCTRL_PIN(F, 3),
                  SUNXI_FUNCTION(0x0, "gpio_in"),
                  SUNXI_FUNCTION(0x1, "gpio_out"),
                  SUNXI_FUNCTION(0x2, "mmc0"),          /* CMD */
                  SUNXI_FUNCTION(0x4, "jtag")),         /* DO1 */
-       SUNXI_PIN(SUNXI_PINCTRL_PIN_PF4,
+       SUNXI_PIN(SUNXI_PINCTRL_PIN(F, 4),
                  SUNXI_FUNCTION(0x0, "gpio_in"),
                  SUNXI_FUNCTION(0x1, "gpio_out"),
                  SUNXI_FUNCTION(0x2, "mmc0"),          /* D3 */
                  SUNXI_FUNCTION(0x4, "uart0")),        /* RX */
-       SUNXI_PIN(SUNXI_PINCTRL_PIN_PF5,
+       SUNXI_PIN(SUNXI_PINCTRL_PIN(F, 5),
                  SUNXI_FUNCTION(0x0, "gpio_in"),
                  SUNXI_FUNCTION(0x1, "gpio_out"),
                  SUNXI_FUNCTION(0x2, "mmc0"),          /* D2 */
                  SUNXI_FUNCTION(0x4, "jtag")),         /* CK1 */
        /* Hole */
-       SUNXI_PIN(SUNXI_PINCTRL_PIN_PG0,
+       SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 0),
                  SUNXI_FUNCTION(0x0, "gpio_in"),
                  SUNXI_FUNCTION(0x2, "gps"),           /* CLK */
                  SUNXI_FUNCTION_IRQ(0x6, 0)),          /* EINT0 */
-       SUNXI_PIN(SUNXI_PINCTRL_PIN_PG1,
+       SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 1),
                  SUNXI_FUNCTION(0x0, "gpio_in"),
                  SUNXI_FUNCTION(0x2, "gps"),           /* SIGN */
                  SUNXI_FUNCTION_IRQ(0x6, 1)),          /* EINT1 */
-       SUNXI_PIN(SUNXI_PINCTRL_PIN_PG2,
+       SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 2),
                  SUNXI_FUNCTION(0x0, "gpio_in"),
                  SUNXI_FUNCTION(0x2, "gps"),           /* MAG */
                  SUNXI_FUNCTION_IRQ(0x6, 2)),          /* EINT2 */
-       SUNXI_PIN(SUNXI_PINCTRL_PIN_PG3,
+       SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 3),
                  SUNXI_FUNCTION(0x0, "gpio_in"),
                  SUNXI_FUNCTION(0x1, "gpio_out"),
                  SUNXI_FUNCTION(0x2, "mmc1"),          /* CMD */
                  SUNXI_FUNCTION(0x4, "uart1"),         /* TX */
                  SUNXI_FUNCTION_IRQ(0x6, 3)),          /* EINT3 */
-       SUNXI_PIN(SUNXI_PINCTRL_PIN_PG4,
+       SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 4),
                  SUNXI_FUNCTION(0x0, "gpio_in"),
                  SUNXI_FUNCTION(0x1, "gpio_out"),
                  SUNXI_FUNCTION(0x2, "mmc1"),          /* CLK */
                  SUNXI_FUNCTION(0x4, "uart1"),         /* RX */
                  SUNXI_FUNCTION_IRQ(0x6, 4)),          /* EINT4 */
-       SUNXI_PIN(SUNXI_PINCTRL_PIN_PG5,
+       SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 5),
                  SUNXI_FUNCTION(0x0, "gpio_in"),
                  SUNXI_FUNCTION(0x1, "gpio_out"),
                  SUNXI_FUNCTION(0x2, "mmc1"),          /* DO */
                  SUNXI_FUNCTION(0x4, "uart1"),         /* CTS */
                  SUNXI_FUNCTION_IRQ(0x6, 5)),          /* EINT5 */
-       SUNXI_PIN(SUNXI_PINCTRL_PIN_PG6,
+       SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 6),
                  SUNXI_FUNCTION(0x0, "gpio_in"),
                  SUNXI_FUNCTION(0x1, "gpio_out"),
                  SUNXI_FUNCTION(0x2, "mmc1"),          /* D1 */
                  SUNXI_FUNCTION(0x4, "uart1"),         /* RTS */
                  SUNXI_FUNCTION(0x5, "uart2"),         /* RTS */
                  SUNXI_FUNCTION_IRQ(0x6, 6)),          /* EINT6 */
-       SUNXI_PIN(SUNXI_PINCTRL_PIN_PG7,
+       SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 7),
                  SUNXI_FUNCTION(0x0, "gpio_in"),
                  SUNXI_FUNCTION(0x1, "gpio_out"),
                  SUNXI_FUNCTION(0x2, "mmc1"),          /* D2 */
                  SUNXI_FUNCTION(0x5, "uart2"),         /* TX */
                  SUNXI_FUNCTION_IRQ(0x6, 7)),          /* EINT7 */
-       SUNXI_PIN(SUNXI_PINCTRL_PIN_PG8,
+       SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 8),
                  SUNXI_FUNCTION(0x0, "gpio_in"),
                  SUNXI_FUNCTION(0x1, "gpio_out"),
                  SUNXI_FUNCTION(0x2, "mmc1"),          /* D3 */
                  SUNXI_FUNCTION(0x5, "uart2"),         /* RX */
                  SUNXI_FUNCTION_IRQ(0x6, 8)),          /* EINT8 */
-       SUNXI_PIN(SUNXI_PINCTRL_PIN_PG9,
+       SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 9),
                  SUNXI_FUNCTION(0x0, "gpio_in"),
                  SUNXI_FUNCTION(0x1, "gpio_out"),
                  SUNXI_FUNCTION(0x2, "spi1"),          /* CS0 */
                  SUNXI_FUNCTION(0x3, "uart3"),         /* TX */
                  SUNXI_FUNCTION_IRQ(0x6, 9)),          /* EINT9 */
-       SUNXI_PIN(SUNXI_PINCTRL_PIN_PG10,
+       SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 10),
                  SUNXI_FUNCTION(0x0, "gpio_in"),
                  SUNXI_FUNCTION(0x1, "gpio_out"),
                  SUNXI_FUNCTION(0x2, "spi1"),          /* CLK */
                  SUNXI_FUNCTION(0x3, "uart3"),         /* RX */
                  SUNXI_FUNCTION_IRQ(0x6, 10)),         /* EINT10 */
-       SUNXI_PIN(SUNXI_PINCTRL_PIN_PG11,
+       SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 11),
                  SUNXI_FUNCTION(0x0, "gpio_in"),
                  SUNXI_FUNCTION(0x1, "gpio_out"),
                  SUNXI_FUNCTION(0x2, "spi1"),          /* MOSI */
                  SUNXI_FUNCTION(0x3, "uart3"),         /* CTS */
                  SUNXI_FUNCTION_IRQ(0x6, 11)),         /* EINT11 */
-       SUNXI_PIN(SUNXI_PINCTRL_PIN_PG12,
+       SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 12),
                  SUNXI_FUNCTION(0x0, "gpio_in"),
                  SUNXI_FUNCTION(0x1, "gpio_out"),
                  SUNXI_FUNCTION(0x2, "spi1"),          /* MISO */
                  SUNXI_FUNCTION(0x3, "uart3"),         /* RTS */
                  SUNXI_FUNCTION_IRQ(0x6, 12)),         /* EINT12 */
-       SUNXI_PIN(SUNXI_PINCTRL_PIN_PG13,
+       SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 13),
                  SUNXI_FUNCTION(0x0, "gpio_in"),
                  SUNXI_FUNCTION(0x1, "gpio_out"),
                  SUNXI_FUNCTION(0x2, "spi1"),          /* CS1 */
@@ -1646,358 +1646,358 @@ static const struct sunxi_desc_pin sun5i_a10s_pins[] = {
 
 static const struct sunxi_desc_pin sun5i_a13_pins[] = {
        /* Hole */
-       SUNXI_PIN(SUNXI_PINCTRL_PIN_PB0,
+       SUNXI_PIN(SUNXI_PINCTRL_PIN(B, 0),
                  SUNXI_FUNCTION(0x0, "gpio_in"),
                  SUNXI_FUNCTION(0x1, "gpio_out"),
                  SUNXI_FUNCTION(0x2, "i2c0")),         /* SCK */
-       SUNXI_PIN(SUNXI_PINCTRL_PIN_PB1,
+       SUNXI_PIN(SUNXI_PINCTRL_PIN(B, 1),
                  SUNXI_FUNCTION(0x0, "gpio_in"),
                  SUNXI_FUNCTION(0x1, "gpio_out"),
                  SUNXI_FUNCTION(0x2, "i2c0")),         /* SDA */
-       SUNXI_PIN(SUNXI_PINCTRL_PIN_PB2,
+       SUNXI_PIN(SUNXI_PINCTRL_PIN(B, 2),
                  SUNXI_FUNCTION(0x0, "gpio_in"),
                  SUNXI_FUNCTION(0x1, "gpio_out"),
                  SUNXI_FUNCTION(0x2, "pwm"),
                  SUNXI_FUNCTION_IRQ(0x6, 16)),         /* EINT16 */
-       SUNXI_PIN(SUNXI_PINCTRL_PIN_PB3,
+       SUNXI_PIN(SUNXI_PINCTRL_PIN(B, 3),
                  SUNXI_FUNCTION(0x0, "gpio_in"),
                  SUNXI_FUNCTION(0x1, "gpio_out"),
                  SUNXI_FUNCTION(0x2, "ir0"),           /* TX */
                  SUNXI_FUNCTION_IRQ(0x6, 17)),         /* EINT17 */
-       SUNXI_PIN(SUNXI_PINCTRL_PIN_PB4,
+       SUNXI_PIN(SUNXI_PINCTRL_PIN(B, 4),
                  SUNXI_FUNCTION(0x0, "gpio_in"),
                  SUNXI_FUNCTION(0x1, "gpio_out"),
                  SUNXI_FUNCTION(0x2, "ir0"),           /* RX */
                  SUNXI_FUNCTION_IRQ(0x6, 18)),         /* EINT18 */
        /* Hole */
-       SUNXI_PIN(SUNXI_PINCTRL_PIN_PB10,
+       SUNXI_PIN(SUNXI_PINCTRL_PIN(B, 10),
                  SUNXI_FUNCTION(0x0, "gpio_in"),
                  SUNXI_FUNCTION(0x1, "gpio_out"),
                  SUNXI_FUNCTION(0x2, "spi2"),          /* CS1 */
                  SUNXI_FUNCTION_IRQ(0x6, 24)),         /* EINT24 */
        /* Hole */
-       SUNXI_PIN(SUNXI_PINCTRL_PIN_PB15,
+       SUNXI_PIN(SUNXI_PINCTRL_PIN(B, 15),
                  SUNXI_FUNCTION(0x0, "gpio_in"),
                  SUNXI_FUNCTION(0x1, "gpio_out"),
                  SUNXI_FUNCTION(0x2, "i2c1")),         /* SCK */
-       SUNXI_PIN(SUNXI_PINCTRL_PIN_PB16,
+       SUNXI_PIN(SUNXI_PINCTRL_PIN(B, 16),
                  SUNXI_FUNCTION(0x0, "gpio_in"),
                  SUNXI_FUNCTION(0x1, "gpio_out"),
                  SUNXI_FUNCTION(0x2, "i2c1")),         /* SDA */
-       SUNXI_PIN(SUNXI_PINCTRL_PIN_PB17,
+       SUNXI_PIN(SUNXI_PINCTRL_PIN(B, 17),
                  SUNXI_FUNCTION(0x0, "gpio_in"),
                  SUNXI_FUNCTION(0x1, "gpio_out"),
                  SUNXI_FUNCTION(0x2, "i2c2")),         /* SCK */
-       SUNXI_PIN(SUNXI_PINCTRL_PIN_PB18,
+       SUNXI_PIN(SUNXI_PINCTRL_PIN(B, 18),
                  SUNXI_FUNCTION(0x0, "gpio_in"),
                  SUNXI_FUNCTION(0x1, "gpio_out"),
                  SUNXI_FUNCTION(0x2, "i2c2")),         /* SDA */
        /* Hole */
-       SUNXI_PIN(SUNXI_PINCTRL_PIN_PC0,
+       SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 0),
                  SUNXI_FUNCTION(0x0, "gpio_in"),
                  SUNXI_FUNCTION(0x1, "gpio_out"),
                  SUNXI_FUNCTION(0x2, "nand0"),         /* NWE */
                  SUNXI_FUNCTION(0x3, "spi0")),         /* MOSI */
-       SUNXI_PIN(SUNXI_PINCTRL_PIN_PC1,
+       SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 1),
                  SUNXI_FUNCTION(0x0, "gpio_in"),
                  SUNXI_FUNCTION(0x1, "gpio_out"),
                  SUNXI_FUNCTION(0x2, "nand0"),         /* NALE */
                  SUNXI_FUNCTION(0x3, "spi0")),         /* MISO */
-       SUNXI_PIN(SUNXI_PINCTRL_PIN_PC2,
+       SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 2),
                  SUNXI_FUNCTION(0x0, "gpio_in"),
                  SUNXI_FUNCTION(0x1, "gpio_out"),
                  SUNXI_FUNCTION(0x2, "nand0"),         /* NCLE */
                  SUNXI_FUNCTION(0x3, "spi0")),         /* CLK */
-       SUNXI_PIN(SUNXI_PINCTRL_PIN_PC3,
+       SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 3),
                  SUNXI_FUNCTION(0x0, "gpio_in"),
                  SUNXI_FUNCTION(0x1, "gpio_out"),
                  SUNXI_FUNCTION(0x2, "nand0"),         /* NCE1 */
                  SUNXI_FUNCTION(0x3, "spi0")),         /* CS0 */
-       SUNXI_PIN(SUNXI_PINCTRL_PIN_PC4,
+       SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 4),
                  SUNXI_FUNCTION(0x0, "gpio_in"),
                  SUNXI_FUNCTION(0x1, "gpio_out"),
                  SUNXI_FUNCTION(0x2, "nand0")),        /* NCE0 */
-       SUNXI_PIN(SUNXI_PINCTRL_PIN_PC5,
+       SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 5),
                  SUNXI_FUNCTION(0x0, "gpio_in"),
                  SUNXI_FUNCTION(0x1, "gpio_out"),
                  SUNXI_FUNCTION(0x2, "nand0")),        /* NRE */
-       SUNXI_PIN(SUNXI_PINCTRL_PIN_PC6,
+       SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 6),
                  SUNXI_FUNCTION(0x0, "gpio_in"),
                  SUNXI_FUNCTION(0x1, "gpio_out"),
                  SUNXI_FUNCTION(0x2, "nand0"),         /* NRB0 */
                  SUNXI_FUNCTION(0x3, "mmc2")),         /* CMD */
-       SUNXI_PIN(SUNXI_PINCTRL_PIN_PC7,
+       SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 7),
                  SUNXI_FUNCTION(0x0, "gpio_in"),
                  SUNXI_FUNCTION(0x1, "gpio_out"),
                  SUNXI_FUNCTION(0x2, "nand0"),         /* NRB1 */
                  SUNXI_FUNCTION(0x3, "mmc2")),         /* CLK */
-       SUNXI_PIN(SUNXI_PINCTRL_PIN_PC8,
+       SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 8),
                  SUNXI_FUNCTION(0x0, "gpio_in"),
                  SUNXI_FUNCTION(0x1, "gpio_out"),
                  SUNXI_FUNCTION(0x2, "nand0"),         /* NDQ0 */
                  SUNXI_FUNCTION(0x3, "mmc2")),         /* D0 */
-       SUNXI_PIN(SUNXI_PINCTRL_PIN_PC9,
+       SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 9),
                  SUNXI_FUNCTION(0x0, "gpio_in"),
                  SUNXI_FUNCTION(0x1, "gpio_out"),
                  SUNXI_FUNCTION(0x2, "nand0"),         /* NDQ1 */
                  SUNXI_FUNCTION(0x3, "mmc2")),         /* D1 */
-       SUNXI_PIN(SUNXI_PINCTRL_PIN_PC10,
+       SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 10),
                  SUNXI_FUNCTION(0x0, "gpio_in"),
                  SUNXI_FUNCTION(0x1, "gpio_out"),
                  SUNXI_FUNCTION(0x2, "nand0"),         /* NDQ2 */
                  SUNXI_FUNCTION(0x3, "mmc2")),         /* D2 */
-       SUNXI_PIN(SUNXI_PINCTRL_PIN_PC11,
+       SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 11),
                  SUNXI_FUNCTION(0x0, "gpio_in"),
                  SUNXI_FUNCTION(0x1, "gpio_out"),
                  SUNXI_FUNCTION(0x2, "nand0"),         /* NDQ3 */
                  SUNXI_FUNCTION(0x3, "mmc2")),         /* D3 */
-       SUNXI_PIN(SUNXI_PINCTRL_PIN_PC12,
+       SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 12),
                  SUNXI_FUNCTION(0x0, "gpio_in"),
                  SUNXI_FUNCTION(0x1, "gpio_out"),
                  SUNXI_FUNCTION(0x2, "nand0"),         /* NDQ4 */
                  SUNXI_FUNCTION(0x3, "mmc2")),         /* D4 */
-       SUNXI_PIN(SUNXI_PINCTRL_PIN_PC13,
+       SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 13),
                  SUNXI_FUNCTION(0x0, "gpio_in"),
                  SUNXI_FUNCTION(0x1, "gpio_out"),
                  SUNXI_FUNCTION(0x2, "nand0"),         /* NDQ5 */
                  SUNXI_FUNCTION(0x3, "mmc2")),         /* D5 */
-       SUNXI_PIN(SUNXI_PINCTRL_PIN_PC14,
+       SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 14),
                  SUNXI_FUNCTION(0x0, "gpio_in"),
                  SUNXI_FUNCTION(0x1, "gpio_out"),
                  SUNXI_FUNCTION(0x2, "nand0"),         /* NDQ6 */
                  SUNXI_FUNCTION(0x3, "mmc2")),         /* D6 */
-       SUNXI_PIN(SUNXI_PINCTRL_PIN_PC15,
+       SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 15),
                  SUNXI_FUNCTION(0x0, "gpio_in"),
                  SUNXI_FUNCTION(0x1, "gpio_out"),
                  SUNXI_FUNCTION(0x2, "nand0"),         /* NDQ7 */
                  SUNXI_FUNCTION(0x3, "mmc2")),         /* D7 */
        /* Hole */
-       SUNXI_PIN(SUNXI_PINCTRL_PIN_PC19,
+       SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 19),
                  SUNXI_FUNCTION(0x0, "gpio_in"),
                  SUNXI_FUNCTION(0x1, "gpio_out"),
                  SUNXI_FUNCTION(0x2, "nand0"),         /* NDQS */
                  SUNXI_FUNCTION(0x4, "uart3")),        /* RTS */
        /* Hole */
-       SUNXI_PIN(SUNXI_PINCTRL_PIN_PD2,
+       SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 2),
                  SUNXI_FUNCTION(0x0, "gpio_in"),
                  SUNXI_FUNCTION(0x1, "gpio_out"),
                  SUNXI_FUNCTION(0x2, "lcd0")),         /* D2 */
-       SUNXI_PIN(SUNXI_PINCTRL_PIN_PD3,
+       SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 3),
                  SUNXI_FUNCTION(0x0, "gpio_in"),
                  SUNXI_FUNCTION(0x1, "gpio_out"),
                  SUNXI_FUNCTION(0x2, "lcd0")),         /* D3 */
-       SUNXI_PIN(SUNXI_PINCTRL_PIN_PD4,
+       SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 4),
                  SUNXI_FUNCTION(0x0, "gpio_in"),
                  SUNXI_FUNCTION(0x1, "gpio_out"),
                  SUNXI_FUNCTION(0x2, "lcd0")),         /* D4 */
-       SUNXI_PIN(SUNXI_PINCTRL_PIN_PD5,
+       SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 5),
                  SUNXI_FUNCTION(0x0, "gpio_in"),
                  SUNXI_FUNCTION(0x1, "gpio_out"),
                  SUNXI_FUNCTION(0x2, "lcd0")),         /* D5 */
-       SUNXI_PIN(SUNXI_PINCTRL_PIN_PD6,
+       SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 6),
                  SUNXI_FUNCTION(0x0, "gpio_in"),
                  SUNXI_FUNCTION(0x1, "gpio_out"),
                  SUNXI_FUNCTION(0x2, "lcd0")),         /* D6 */
-       SUNXI_PIN(SUNXI_PINCTRL_PIN_PD7,
+       SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 7),
                  SUNXI_FUNCTION(0x0, "gpio_in"),
                  SUNXI_FUNCTION(0x1, "gpio_out"),
                  SUNXI_FUNCTION(0x2, "lcd0")),         /* D7 */
        /* Hole */
-       SUNXI_PIN(SUNXI_PINCTRL_PIN_PD10,
+       SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 10),
                  SUNXI_FUNCTION(0x0, "gpio_in"),
                  SUNXI_FUNCTION(0x1, "gpio_out"),
                  SUNXI_FUNCTION(0x2, "lcd0")),         /* D10 */
-       SUNXI_PIN(SUNXI_PINCTRL_PIN_PD11,
+       SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 11),
                  SUNXI_FUNCTION(0x0, "gpio_in"),
                  SUNXI_FUNCTION(0x1, "gpio_out"),
                  SUNXI_FUNCTION(0x2, "lcd0")),         /* D11 */
-       SUNXI_PIN(SUNXI_PINCTRL_PIN_PD12,
+       SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 12),
                  SUNXI_FUNCTION(0x0, "gpio_in"),
                  SUNXI_FUNCTION(0x1, "gpio_out"),
                  SUNXI_FUNCTION(0x2, "lcd0")),         /* D12 */
-       SUNXI_PIN(SUNXI_PINCTRL_PIN_PD13,
+       SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 13),
                  SUNXI_FUNCTION(0x0, "gpio_in"),
                  SUNXI_FUNCTION(0x1, "gpio_out"),
                  SUNXI_FUNCTION(0x2, "lcd0")),         /* D13 */
-       SUNXI_PIN(SUNXI_PINCTRL_PIN_PD14,
+       SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 14),
                  SUNXI_FUNCTION(0x0, "gpio_in"),
                  SUNXI_FUNCTION(0x1, "gpio_out"),
                  SUNXI_FUNCTION(0x2, "lcd0")),         /* D14 */
-       SUNXI_PIN(SUNXI_PINCTRL_PIN_PD15,
+       SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 15),
                  SUNXI_FUNCTION(0x0, "gpio_in"),
                  SUNXI_FUNCTION(0x1, "gpio_out"),
                  SUNXI_FUNCTION(0x2, "lcd0")),         /* D15 */
        /* Hole */
-       SUNXI_PIN(SUNXI_PINCTRL_PIN_PD18,
+       SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 18),
                  SUNXI_FUNCTION(0x0, "gpio_in"),
                  SUNXI_FUNCTION(0x1, "gpio_out"),
                  SUNXI_FUNCTION(0x2, "lcd0")),         /* D18 */
-       SUNXI_PIN(SUNXI_PINCTRL_PIN_PD19,
+       SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 19),
                  SUNXI_FUNCTION(0x0, "gpio_in"),
                  SUNXI_FUNCTION(0x1, "gpio_out"),
                  SUNXI_FUNCTION(0x2, "lcd0")),         /* D19 */
-       SUNXI_PIN(SUNXI_PINCTRL_PIN_PD20,
+       SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 20),
                  SUNXI_FUNCTION(0x0, "gpio_in"),
                  SUNXI_FUNCTION(0x1, "gpio_out"),
                  SUNXI_FUNCTION(0x2, "lcd0")),         /* D20 */
-       SUNXI_PIN(SUNXI_PINCTRL_PIN_PD21,
+       SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 21),
                  SUNXI_FUNCTION(0x0, "gpio_in"),
                  SUNXI_FUNCTION(0x1, "gpio_out"),
                  SUNXI_FUNCTION(0x2, "lcd0")),         /* D21 */
-       SUNXI_PIN(SUNXI_PINCTRL_PIN_PD22,
+       SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 22),
                  SUNXI_FUNCTION(0x0, "gpio_in"),
                  SUNXI_FUNCTION(0x1, "gpio_out"),
                  SUNXI_FUNCTION(0x2, "lcd0")),         /* D22 */
-       SUNXI_PIN(SUNXI_PINCTRL_PIN_PD23,
+       SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 23),
                  SUNXI_FUNCTION(0x0, "gpio_in"),
                  SUNXI_FUNCTION(0x1, "gpio_out"),
                  SUNXI_FUNCTION(0x2, "lcd0")),         /* D23 */
-       SUNXI_PIN(SUNXI_PINCTRL_PIN_PD24,
+       SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 24),
                  SUNXI_FUNCTION(0x0, "gpio_in"),
                  SUNXI_FUNCTION(0x1, "gpio_out"),
                  SUNXI_FUNCTION(0x2, "lcd0")),         /* CLK */
-       SUNXI_PIN(SUNXI_PINCTRL_PIN_PD25,
+       SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 25),
                  SUNXI_FUNCTION(0x0, "gpio_in"),
                  SUNXI_FUNCTION(0x1, "gpio_out"),
                  SUNXI_FUNCTION(0x2, "lcd0")),         /* DE */
-       SUNXI_PIN(SUNXI_PINCTRL_PIN_PD26,
+       SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 26),
                  SUNXI_FUNCTION(0x0, "gpio_in"),
                  SUNXI_FUNCTION(0x1, "gpio_out"),
                  SUNXI_FUNCTION(0x2, "lcd0")),         /* HSYNC */
-       SUNXI_PIN(SUNXI_PINCTRL_PIN_PD27,
+       SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 27),
                  SUNXI_FUNCTION(0x0, "gpio_in"),
                  SUNXI_FUNCTION(0x1, "gpio_out"),
                  SUNXI_FUNCTION(0x2, "lcd0")),         /* VSYNC */
        /* Hole */
-       SUNXI_PIN(SUNXI_PINCTRL_PIN_PE0,
+       SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 0),
                  SUNXI_FUNCTION(0x0, "gpio_in"),
                  SUNXI_FUNCTION(0x3, "csi0"),          /* PCLK */
                  SUNXI_FUNCTION(0x4, "spi2"),          /* CS0 */
                  SUNXI_FUNCTION_IRQ(0x6, 14)),         /* EINT14 */
-       SUNXI_PIN(SUNXI_PINCTRL_PIN_PE1,
+       SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 1),
                  SUNXI_FUNCTION(0x0, "gpio_in"),
                  SUNXI_FUNCTION(0x3, "csi0"),          /* MCLK */
                  SUNXI_FUNCTION(0x4, "spi2"),          /* CLK */
                  SUNXI_FUNCTION_IRQ(0x6, 15)),         /* EINT15 */
-       SUNXI_PIN(SUNXI_PINCTRL_PIN_PE2,
+       SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 2),
                  SUNXI_FUNCTION(0x0, "gpio_in"),
                  SUNXI_FUNCTION(0x3, "csi0"),          /* HSYNC */
                  SUNXI_FUNCTION(0x4, "spi2")),         /* MOSI */
-       SUNXI_PIN(SUNXI_PINCTRL_PIN_PE3,
+       SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 3),
                  SUNXI_FUNCTION(0x0, "gpio_in"),
                  SUNXI_FUNCTION(0x1, "gpio_out"),
                  SUNXI_FUNCTION(0x3, "csi0"),          /* VSYNC */
                  SUNXI_FUNCTION(0x4, "spi2")),         /* MISO */
-       SUNXI_PIN(SUNXI_PINCTRL_PIN_PE4,
+       SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 4),
                  SUNXI_FUNCTION(0x0, "gpio_in"),
                  SUNXI_FUNCTION(0x1, "gpio_out"),
                  SUNXI_FUNCTION(0x3, "csi0"),          /* D0 */
                  SUNXI_FUNCTION(0x4, "mmc2")),         /* D0 */
-       SUNXI_PIN(SUNXI_PINCTRL_PIN_PE5,
+       SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 5),
                  SUNXI_FUNCTION(0x0, "gpio_in"),
                  SUNXI_FUNCTION(0x1, "gpio_out"),
                  SUNXI_FUNCTION(0x3, "csi0"),          /* D1 */
                  SUNXI_FUNCTION(0x4, "mmc2")),         /* D1 */
-       SUNXI_PIN(SUNXI_PINCTRL_PIN_PE6,
+       SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 6),
                  SUNXI_FUNCTION(0x0, "gpio_in"),
                  SUNXI_FUNCTION(0x1, "gpio_out"),
                  SUNXI_FUNCTION(0x3, "csi0"),          /* D2 */
                  SUNXI_FUNCTION(0x4, "mmc2")),         /* D2 */
-       SUNXI_PIN(SUNXI_PINCTRL_PIN_PE7,
+       SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 7),
                  SUNXI_FUNCTION(0x0, "gpio_in"),
                  SUNXI_FUNCTION(0x1, "gpio_out"),
                  SUNXI_FUNCTION(0x3, "csi0"),          /* D3 */
                  SUNXI_FUNCTION(0x4, "mmc2")),         /* D3 */
-       SUNXI_PIN(SUNXI_PINCTRL_PIN_PE8,
+       SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 8),
                  SUNXI_FUNCTION(0x0, "gpio_in"),
                  SUNXI_FUNCTION(0x1, "gpio_out"),
                  SUNXI_FUNCTION(0x3, "csi0"),          /* D4 */
                  SUNXI_FUNCTION(0x4, "mmc2")),         /* CMD */
-       SUNXI_PIN(SUNXI_PINCTRL_PIN_PE9,
+       SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 9),
                  SUNXI_FUNCTION(0x0, "gpio_in"),
                  SUNXI_FUNCTION(0x1, "gpio_out"),
                  SUNXI_FUNCTION(0x3, "csi0"),          /* D5 */
                  SUNXI_FUNCTION(0x4, "mmc2")),         /* CLK */
-       SUNXI_PIN(SUNXI_PINCTRL_PIN_PE10,
+       SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 10),
                  SUNXI_FUNCTION(0x0, "gpio_in"),
                  SUNXI_FUNCTION(0x1, "gpio_out"),
                  SUNXI_FUNCTION(0x3, "csi0"),          /* D6 */
                  SUNXI_FUNCTION(0x4, "uart1")),        /* TX */
-       SUNXI_PIN(SUNXI_PINCTRL_PIN_PE11,
+       SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 11),
                  SUNXI_FUNCTION(0x0, "gpio_in"),
                  SUNXI_FUNCTION(0x1, "gpio_out"),
                  SUNXI_FUNCTION(0x3, "csi0"),          /* D7 */
                  SUNXI_FUNCTION(0x4, "uart1")),        /* RX */
        /* Hole */
-       SUNXI_PIN(SUNXI_PINCTRL_PIN_PF0,
+       SUNXI_PIN(SUNXI_PINCTRL_PIN(F, 0),
                  SUNXI_FUNCTION(0x0, "gpio_in"),
                  SUNXI_FUNCTION(0x1, "gpio_out"),
                  SUNXI_FUNCTION(0x2, "mmc0")),         /* D1 */
-       SUNXI_PIN(SUNXI_PINCTRL_PIN_PF1,
+       SUNXI_PIN(SUNXI_PINCTRL_PIN(F, 1),
                  SUNXI_FUNCTION(0x0, "gpio_in"),
                  SUNXI_FUNCTION(0x1, "gpio_out"),
                  SUNXI_FUNCTION(0x2, "mmc0")),         /* D0 */
-       SUNXI_PIN(SUNXI_PINCTRL_PIN_PF2,
+       SUNXI_PIN(SUNXI_PINCTRL_PIN(F, 2),
                  SUNXI_FUNCTION(0x0, "gpio_in"),
                  SUNXI_FUNCTION(0x1, "gpio_out"),
                  SUNXI_FUNCTION(0x2, "mmc0")),         /* CLK */
-       SUNXI_PIN(SUNXI_PINCTRL_PIN_PF3,
+       SUNXI_PIN(SUNXI_PINCTRL_PIN(F, 3),
                  SUNXI_FUNCTION(0x0, "gpio_in"),
                  SUNXI_FUNCTION(0x1, "gpio_out"),
                  SUNXI_FUNCTION(0x2, "mmc0")),         /* CMD */
-       SUNXI_PIN(SUNXI_PINCTRL_PIN_PF4,
+       SUNXI_PIN(SUNXI_PINCTRL_PIN(F, 4),
                  SUNXI_FUNCTION(0x0, "gpio_in"),
                  SUNXI_FUNCTION(0x1, "gpio_out"),
                  SUNXI_FUNCTION(0x2, "mmc0")),         /* D3 */
-       SUNXI_PIN(SUNXI_PINCTRL_PIN_PF5,
+       SUNXI_PIN(SUNXI_PINCTRL_PIN(F, 5),
                  SUNXI_FUNCTION(0x0, "gpio_in"),
                  SUNXI_FUNCTION(0x1, "gpio_out"),
                  SUNXI_FUNCTION(0x2, "mmc0")),         /* D2 */
        /* Hole */
-       SUNXI_PIN(SUNXI_PINCTRL_PIN_PG0,
+       SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 0),
                  SUNXI_FUNCTION(0x0, "gpio_in"),
                  SUNXI_FUNCTION(0x1, "gpio_out"),
                  SUNXI_FUNCTION_IRQ(0x6, 0)),          /* EINT0 */
-       SUNXI_PIN(SUNXI_PINCTRL_PIN_PG1,
+       SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 1),
                  SUNXI_FUNCTION(0x0, "gpio_in"),
                  SUNXI_FUNCTION(0x1, "gpio_out"),
                  SUNXI_FUNCTION_IRQ(0x6, 1)),          /* EINT1 */
-       SUNXI_PIN(SUNXI_PINCTRL_PIN_PG2,
+       SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 2),
                  SUNXI_FUNCTION(0x0, "gpio_in"),
                  SUNXI_FUNCTION(0x1, "gpio_out"),
                  SUNXI_FUNCTION_IRQ(0x6, 2)),          /* EINT2 */
-       SUNXI_PIN(SUNXI_PINCTRL_PIN_PG3,
+       SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 3),
                  SUNXI_FUNCTION(0x0, "gpio_in"),
                  SUNXI_FUNCTION(0x1, "gpio_out"),
                  SUNXI_FUNCTION(0x2, "mmc1"),          /* CMD */
                  SUNXI_FUNCTION(0x4, "uart1"),         /* TX */
                  SUNXI_FUNCTION_IRQ(0x6, 3)),          /* EINT3 */
-       SUNXI_PIN(SUNXI_PINCTRL_PIN_PG4,
+       SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 4),
                  SUNXI_FUNCTION(0x0, "gpio_in"),
                  SUNXI_FUNCTION(0x1, "gpio_out"),
                  SUNXI_FUNCTION(0x2, "mmc1"),          /* CLK */
                  SUNXI_FUNCTION(0x4, "uart1"),         /* RX */
                  SUNXI_FUNCTION_IRQ(0x6, 4)),          /* EINT4 */
        /* Hole */
-       SUNXI_PIN(SUNXI_PINCTRL_PIN_PG9,
+       SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 9),
                  SUNXI_FUNCTION(0x0, "gpio_in"),
                  SUNXI_FUNCTION(0x1, "gpio_out"),
                  SUNXI_FUNCTION(0x2, "spi1"),          /* CS0 */
                  SUNXI_FUNCTION(0x3, "uart3"),         /* TX */
                  SUNXI_FUNCTION_IRQ(0x6, 9)),          /* EINT9 */
-       SUNXI_PIN(SUNXI_PINCTRL_PIN_PG10,
+       SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 10),
                  SUNXI_FUNCTION(0x0, "gpio_in"),
                  SUNXI_FUNCTION(0x1, "gpio_out"),
                  SUNXI_FUNCTION(0x2, "spi1"),          /* CLK */
                  SUNXI_FUNCTION(0x3, "uart3"),         /* RX */
                  SUNXI_FUNCTION_IRQ(0x6, 10)),         /* EINT10 */
-       SUNXI_PIN(SUNXI_PINCTRL_PIN_PG11,
+       SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 11),
                  SUNXI_FUNCTION(0x0, "gpio_in"),
                  SUNXI_FUNCTION(0x1, "gpio_out"),
                  SUNXI_FUNCTION(0x2, "spi1"),          /* MOSI */
                  SUNXI_FUNCTION(0x3, "uart3"),         /* CTS */
                  SUNXI_FUNCTION_IRQ(0x6, 11)),         /* EINT11 */
-       SUNXI_PIN(SUNXI_PINCTRL_PIN_PG12,
+       SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 12),
                  SUNXI_FUNCTION(0x0, "gpio_in"),
                  SUNXI_FUNCTION(0x1, "gpio_out"),
                  SUNXI_FUNCTION(0x2, "spi1"),          /* MISO */
@@ -2006,981 +2006,981 @@ static const struct sunxi_desc_pin sun5i_a13_pins[] = {
 };
 
 static const struct sunxi_desc_pin sun6i_a31_pins[] = {
-       SUNXI_PIN(SUNXI_PINCTRL_PIN_PA0,
+       SUNXI_PIN(SUNXI_PINCTRL_PIN(A, 0),
                  SUNXI_FUNCTION(0x0, "gpio_in"),
                  SUNXI_FUNCTION(0x1, "gpio_out"),
                  SUNXI_FUNCTION(0x2, "gmac"),          /* TXD0 */
                  SUNXI_FUNCTION(0x3, "lcd1"),          /* D0 */
                  SUNXI_FUNCTION(0x4, "uart1")),        /* DTR */
-       SUNXI_PIN(SUNXI_PINCTRL_PIN_PA1,
+       SUNXI_PIN(SUNXI_PINCTRL_PIN(A, 1),
                  SUNXI_FUNCTION(0x0, "gpio_in"),
                  SUNXI_FUNCTION(0x1, "gpio_out"),
                  SUNXI_FUNCTION(0x2, "gmac"),          /* TXD1 */
                  SUNXI_FUNCTION(0x3, "lcd1"),          /* D1 */
                  SUNXI_FUNCTION(0x4, "uart1")),        /* DSR */
-       SUNXI_PIN(SUNXI_PINCTRL_PIN_PA2,
+       SUNXI_PIN(SUNXI_PINCTRL_PIN(A, 2),
                  SUNXI_FUNCTION(0x0, "gpio_in"),
                  SUNXI_FUNCTION(0x1, "gpio_out"),
                  SUNXI_FUNCTION(0x2, "gmac"),          /* TXD2 */
                  SUNXI_FUNCTION(0x3, "lcd1"),          /* D2 */
                  SUNXI_FUNCTION(0x4, "uart1")),        /* DCD */
-       SUNXI_PIN(SUNXI_PINCTRL_PIN_PA3,
+       SUNXI_PIN(SUNXI_PINCTRL_PIN(A, 3),
                  SUNXI_FUNCTION(0x0, "gpio_in"),
                  SUNXI_FUNCTION(0x1, "gpio_out"),
                  SUNXI_FUNCTION(0x2, "gmac"),          /* TXD3 */
                  SUNXI_FUNCTION(0x3, "lcd1"),          /* D3 */
                  SUNXI_FUNCTION(0x4, "uart1")),        /* RING */
-       SUNXI_PIN(SUNXI_PINCTRL_PIN_PA4,
+       SUNXI_PIN(SUNXI_PINCTRL_PIN(A, 4),
                  SUNXI_FUNCTION(0x0, "gpio_in"),
                  SUNXI_FUNCTION(0x1, "gpio_out"),
                  SUNXI_FUNCTION(0x2, "gmac"),          /* TXD4 */
                  SUNXI_FUNCTION(0x3, "lcd1"),          /* D4 */
                  SUNXI_FUNCTION(0x4, "uart1")),        /* TX */
-       SUNXI_PIN(SUNXI_PINCTRL_PIN_PA5,
+       SUNXI_PIN(SUNXI_PINCTRL_PIN(A, 5),
                  SUNXI_FUNCTION(0x0, "gpio_in"),
                  SUNXI_FUNCTION(0x1, "gpio_out"),
                  SUNXI_FUNCTION(0x2, "gmac"),          /* TXD5 */
                  SUNXI_FUNCTION(0x3, "lcd1"),          /* D5 */
                  SUNXI_FUNCTION(0x4, "uart1")),        /* RX */
-       SUNXI_PIN(SUNXI_PINCTRL_PIN_PA6,
+       SUNXI_PIN(SUNXI_PINCTRL_PIN(A, 6),
                  SUNXI_FUNCTION(0x0, "gpio_in"),
                  SUNXI_FUNCTION(0x1, "gpio_out"),
                  SUNXI_FUNCTION(0x2, "gmac"),          /* TXD6 */
                  SUNXI_FUNCTION(0x3, "lcd1"),          /* D6 */
                  SUNXI_FUNCTION(0x4, "uart1")),        /* RTS */
-       SUNXI_PIN(SUNXI_PINCTRL_PIN_PA7,
+       SUNXI_PIN(SUNXI_PINCTRL_PIN(A, 7),
                  SUNXI_FUNCTION(0x0, "gpio_in"),
                  SUNXI_FUNCTION(0x1, "gpio_out"),
                  SUNXI_FUNCTION(0x2, "gmac"),          /* TXD7 */
                  SUNXI_FUNCTION(0x3, "lcd1"),          /* D7 */
                  SUNXI_FUNCTION(0x4, "uart1")),        /* CTS */
-       SUNXI_PIN(SUNXI_PINCTRL_PIN_PA8,
+       SUNXI_PIN(SUNXI_PINCTRL_PIN(A, 8),
                  SUNXI_FUNCTION(0x0, "gpio_in"),
                  SUNXI_FUNCTION(0x1, "gpio_out"),
                  SUNXI_FUNCTION(0x2, "gmac"),          /* TXCLK */
                  SUNXI_FUNCTION(0x3, "lcd1")),         /* D8 */
-       SUNXI_PIN(SUNXI_PINCTRL_PIN_PA9,
+       SUNXI_PIN(SUNXI_PINCTRL_PIN(A, 9),
                  SUNXI_FUNCTION(0x0, "gpio_in"),
                  SUNXI_FUNCTION(0x1, "gpio_out"),
                  SUNXI_FUNCTION(0x2, "gmac"),          /* TXEN */
                  SUNXI_FUNCTION(0x3, "lcd1"),          /* D9 */
                  SUNXI_FUNCTION(0x4, "mmc3"),          /* CMD */
                  SUNXI_FUNCTION(0x5, "mmc2")),         /* CMD */
-       SUNXI_PIN(SUNXI_PINCTRL_PIN_PA10,
+       SUNXI_PIN(SUNXI_PINCTRL_PIN(A, 10),
                  SUNXI_FUNCTION(0x0, "gpio_in"),
                  SUNXI_FUNCTION(0x1, "gpio_out"),
                  SUNXI_FUNCTION(0x2, "gmac"),          /* GTXCLK */
                  SUNXI_FUNCTION(0x3, "lcd1"),          /* D10 */
                  SUNXI_FUNCTION(0x4, "mmc3"),          /* CLK */
                  SUNXI_FUNCTION(0x5, "mmc2")),         /* CLK */
-       SUNXI_PIN(SUNXI_PINCTRL_PIN_PA11,
+       SUNXI_PIN(SUNXI_PINCTRL_PIN(A, 11),
                  SUNXI_FUNCTION(0x0, "gpio_in"),
                  SUNXI_FUNCTION(0x1, "gpio_out"),
                  SUNXI_FUNCTION(0x2, "gmac"),          /* RXD0 */
                  SUNXI_FUNCTION(0x3, "lcd1"),          /* D11 */
                  SUNXI_FUNCTION(0x4, "mmc3"),          /* D0 */
                  SUNXI_FUNCTION(0x5, "mmc2")),         /* D0 */
-       SUNXI_PIN(SUNXI_PINCTRL_PIN_PA12,
+       SUNXI_PIN(SUNXI_PINCTRL_PIN(A, 12),
                  SUNXI_FUNCTION(0x0, "gpio_in"),
                  SUNXI_FUNCTION(0x1, "gpio_out"),
                  SUNXI_FUNCTION(0x2, "gmac"),          /* RXD1 */
                  SUNXI_FUNCTION(0x3, "lcd1"),          /* D12 */
                  SUNXI_FUNCTION(0x4, "mmc3"),          /* D1 */
                  SUNXI_FUNCTION(0x5, "mmc2")),         /* D1 */
-       SUNXI_PIN(SUNXI_PINCTRL_PIN_PA13,
+       SUNXI_PIN(SUNXI_PINCTRL_PIN(A, 13),
                  SUNXI_FUNCTION(0x0, "gpio_in"),
                  SUNXI_FUNCTION(0x1, "gpio_out"),
                  SUNXI_FUNCTION(0x2, "gmac"),          /* RXD2 */
                  SUNXI_FUNCTION(0x3, "lcd1"),          /* D13 */
                  SUNXI_FUNCTION(0x4, "mmc3"),          /* D2 */
                  SUNXI_FUNCTION(0x5, "mmc2")),         /* D2 */
-       SUNXI_PIN(SUNXI_PINCTRL_PIN_PA14,
+       SUNXI_PIN(SUNXI_PINCTRL_PIN(A, 14),
                  SUNXI_FUNCTION(0x0, "gpio_in"),
                  SUNXI_FUNCTION(0x1, "gpio_out"),
                  SUNXI_FUNCTION(0x2, "gmac"),          /* RXD3 */
                  SUNXI_FUNCTION(0x3, "lcd1"),          /* D14 */
                  SUNXI_FUNCTION(0x4, "mmc3"),          /* D3 */
                  SUNXI_FUNCTION(0x5, "mmc2")),         /* D3 */
-       SUNXI_PIN(SUNXI_PINCTRL_PIN_PA15,
+       SUNXI_PIN(SUNXI_PINCTRL_PIN(A, 15),
                  SUNXI_FUNCTION(0x0, "gpio_in"),
                  SUNXI_FUNCTION(0x1, "gpio_out"),
                  SUNXI_FUNCTION(0x2, "gmac"),          /* RXD4 */
                  SUNXI_FUNCTION(0x3, "lcd1")),         /* D15 */
-       SUNXI_PIN(SUNXI_PINCTRL_PIN_PA16,
+       SUNXI_PIN(SUNXI_PINCTRL_PIN(A, 16),
                  SUNXI_FUNCTION(0x0, "gpio_in"),
                  SUNXI_FUNCTION(0x1, "gpio_out"),
                  SUNXI_FUNCTION(0x2, "gmac"),          /* RXD5 */
                  SUNXI_FUNCTION(0x3, "lcd1")),         /* D16 */
-       SUNXI_PIN(SUNXI_PINCTRL_PIN_PA17,
+       SUNXI_PIN(SUNXI_PINCTRL_PIN(A, 17),
                  SUNXI_FUNCTION(0x0, "gpio_in"),
                  SUNXI_FUNCTION(0x1, "gpio_out"),
                  SUNXI_FUNCTION(0x2, "gmac"),          /* RXD6 */
                  SUNXI_FUNCTION(0x3, "lcd1")),         /* D17 */
-       SUNXI_PIN(SUNXI_PINCTRL_PIN_PA18,
+       SUNXI_PIN(SUNXI_PINCTRL_PIN(A, 18),
                  SUNXI_FUNCTION(0x0, "gpio_in"),
                  SUNXI_FUNCTION(0x1, "gpio_out"),
                  SUNXI_FUNCTION(0x2, "gmac"),          /* RXD7 */
                  SUNXI_FUNCTION(0x3, "lcd1")),         /* D18 */
-       SUNXI_PIN(SUNXI_PINCTRL_PIN_PA19,
+       SUNXI_PIN(SUNXI_PINCTRL_PIN(A, 19),
                  SUNXI_FUNCTION(0x0, "gpio_in"),
                  SUNXI_FUNCTION(0x1, "gpio_out"),
                  SUNXI_FUNCTION(0x2, "gmac"),          /* RXDV */
                  SUNXI_FUNCTION(0x3, "lcd1"),          /* D19 */
                  SUNXI_FUNCTION(0x4, "pwm3")),         /* Positive */
-       SUNXI_PIN(SUNXI_PINCTRL_PIN_PA20,
+       SUNXI_PIN(SUNXI_PINCTRL_PIN(A, 20),
                  SUNXI_FUNCTION(0x0, "gpio_in"),
                  SUNXI_FUNCTION(0x1, "gpio_out"),
                  SUNXI_FUNCTION(0x2, "gmac"),          /* RXCLK */
                  SUNXI_FUNCTION(0x3, "lcd1"),          /* D20 */
                  SUNXI_FUNCTION(0x4, "pwm3")),         /* Negative */
-       SUNXI_PIN(SUNXI_PINCTRL_PIN_PA21,
+       SUNXI_PIN(SUNXI_PINCTRL_PIN(A, 21),
                  SUNXI_FUNCTION(0x0, "gpio_in"),
                  SUNXI_FUNCTION(0x1, "gpio_out"),
                  SUNXI_FUNCTION(0x2, "gmac"),          /* TXERR */
                  SUNXI_FUNCTION(0x3, "lcd1"),          /* D21 */
                  SUNXI_FUNCTION(0x4, "spi3")),         /* CS0 */
-       SUNXI_PIN(SUNXI_PINCTRL_PIN_PA22,
+       SUNXI_PIN(SUNXI_PINCTRL_PIN(A, 22),
                  SUNXI_FUNCTION(0x0, "gpio_in"),
                  SUNXI_FUNCTION(0x1, "gpio_out"),
                  SUNXI_FUNCTION(0x2, "gmac"),          /* RXERR */
                  SUNXI_FUNCTION(0x3, "lcd1"),          /* D22 */
                  SUNXI_FUNCTION(0x4, "spi3")),         /* CLK */
-       SUNXI_PIN(SUNXI_PINCTRL_PIN_PA23,
+       SUNXI_PIN(SUNXI_PINCTRL_PIN(A, 23),
                  SUNXI_FUNCTION(0x0, "gpio_in"),
                  SUNXI_FUNCTION(0x1, "gpio_out"),
                  SUNXI_FUNCTION(0x2, "gmac"),          /* COL */
                  SUNXI_FUNCTION(0x3, "lcd1"),          /* D23 */
                  SUNXI_FUNCTION(0x4, "spi3")),         /* MOSI */
-       SUNXI_PIN(SUNXI_PINCTRL_PIN_PA24,
+       SUNXI_PIN(SUNXI_PINCTRL_PIN(A, 24),
                  SUNXI_FUNCTION(0x0, "gpio_in"),
                  SUNXI_FUNCTION(0x1, "gpio_out"),
                  SUNXI_FUNCTION(0x2, "gmac"),          /* CRS */
                  SUNXI_FUNCTION(0x3, "lcd1"),          /* CLK */
                  SUNXI_FUNCTION(0x4, "spi3")),         /* MISO */
-       SUNXI_PIN(SUNXI_PINCTRL_PIN_PA25,
+       SUNXI_PIN(SUNXI_PINCTRL_PIN(A, 25),
                  SUNXI_FUNCTION(0x0, "gpio_in"),
                  SUNXI_FUNCTION(0x1, "gpio_out"),
                  SUNXI_FUNCTION(0x2, "gmac"),          /* CLKIN */
                  SUNXI_FUNCTION(0x3, "lcd1"),          /* DE */
                  SUNXI_FUNCTION(0x4, "spi3")),         /* CS1 */
-       SUNXI_PIN(SUNXI_PINCTRL_PIN_PA26,
+       SUNXI_PIN(SUNXI_PINCTRL_PIN(A, 26),
                  SUNXI_FUNCTION(0x0, "gpio_in"),
                  SUNXI_FUNCTION(0x1, "gpio_out"),
                  SUNXI_FUNCTION(0x2, "gmac"),          /* MDC */
                  SUNXI_FUNCTION(0x3, "lcd1")),         /* HSYNC */
-       SUNXI_PIN(SUNXI_PINCTRL_PIN_PA27,
+       SUNXI_PIN(SUNXI_PINCTRL_PIN(A, 27),
                  SUNXI_FUNCTION(0x0, "gpio_in"),
                  SUNXI_FUNCTION(0x1, "gpio_out"),
                  SUNXI_FUNCTION(0x2, "gmac"),          /* MDIO */
                  SUNXI_FUNCTION(0x3, "lcd1")),         /* VSYNC */
        /* Hole */
-       SUNXI_PIN(SUNXI_PINCTRL_PIN_PB0,
+       SUNXI_PIN(SUNXI_PINCTRL_PIN(B, 0),
                  SUNXI_FUNCTION(0x0, "gpio_in"),
                  SUNXI_FUNCTION(0x1, "gpio_out"),
                  SUNXI_FUNCTION(0x2, "i2s0"),          /* MCLK */
                  SUNXI_FUNCTION(0x3, "uart3"),         /* CTS */
                  SUNXI_FUNCTION(0x4, "csi")),          /* MCLK1 */
-       SUNXI_PIN(SUNXI_PINCTRL_PIN_PB1,
+       SUNXI_PIN(SUNXI_PINCTRL_PIN(B, 1),
                  SUNXI_FUNCTION(0x0, "gpio_in"),
                  SUNXI_FUNCTION(0x1, "gpio_out"),
                  SUNXI_FUNCTION(0x2, "i2s0")),         /* BCLK */
-       SUNXI_PIN(SUNXI_PINCTRL_PIN_PB2,
+       SUNXI_PIN(SUNXI_PINCTRL_PIN(B, 2),
                  SUNXI_FUNCTION(0x0, "gpio_in"),
                  SUNXI_FUNCTION(0x1, "gpio_out"),
                  SUNXI_FUNCTION(0x2, "i2s0")),         /* LRCK */
-       SUNXI_PIN(SUNXI_PINCTRL_PIN_PB3,
+       SUNXI_PIN(SUNXI_PINCTRL_PIN(B, 3),
                  SUNXI_FUNCTION(0x0, "gpio_in"),
                  SUNXI_FUNCTION(0x1, "gpio_out"),
                  SUNXI_FUNCTION(0x2, "i2s0")),         /* DO0 */
-       SUNXI_PIN(SUNXI_PINCTRL_PIN_PB4,
+       SUNXI_PIN(SUNXI_PINCTRL_PIN(B, 4),
                  SUNXI_FUNCTION(0x0, "gpio_in"),
                  SUNXI_FUNCTION(0x1, "gpio_out"),
                  SUNXI_FUNCTION(0x2, "i2s0"),          /* DO1 */
                  SUNXI_FUNCTION(0x3, "uart3")),        /* RTS */
-       SUNXI_PIN(SUNXI_PINCTRL_PIN_PB5,
+       SUNXI_PIN(SUNXI_PINCTRL_PIN(B, 5),
                  SUNXI_FUNCTION(0x0, "gpio_in"),
                  SUNXI_FUNCTION(0x1, "gpio_out"),
                  SUNXI_FUNCTION(0x2, "i2s0"),          /* DO2 */
                  SUNXI_FUNCTION(0x3, "uart3"),         /* TX */
                  SUNXI_FUNCTION(0x4, "i2c3")),         /* SCK */
-       SUNXI_PIN(SUNXI_PINCTRL_PIN_PB6,
+       SUNXI_PIN(SUNXI_PINCTRL_PIN(B, 6),
                  SUNXI_FUNCTION(0x0, "gpio_in"),
                  SUNXI_FUNCTION(0x1, "gpio_out"),
                  SUNXI_FUNCTION(0x2, "i2s0"),          /* DO3 */
                  SUNXI_FUNCTION(0x3, "uart3"),         /* RX */
                  SUNXI_FUNCTION(0x4, "i2c3")),         /* SDA */
-       SUNXI_PIN(SUNXI_PINCTRL_PIN_PB7,
+       SUNXI_PIN(SUNXI_PINCTRL_PIN(B, 7),
                  SUNXI_FUNCTION(0x0, "gpio_in"),
                  SUNXI_FUNCTION(0x1, "gpio_out"),
                  SUNXI_FUNCTION(0x3, "i2s0")),         /* DI */
        /* Hole */
-       SUNXI_PIN(SUNXI_PINCTRL_PIN_PC0,
+       SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 0),
                  SUNXI_FUNCTION(0x0, "gpio_in"),
                  SUNXI_FUNCTION(0x1, "gpio_out"),
                  SUNXI_FUNCTION(0x2, "nand0"),         /* WE */
                  SUNXI_FUNCTION(0x3, "spi0")),         /* MOSI */
-       SUNXI_PIN(SUNXI_PINCTRL_PIN_PC1,
+       SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 1),
                  SUNXI_FUNCTION(0x0, "gpio_in"),
                  SUNXI_FUNCTION(0x1, "gpio_out"),
                  SUNXI_FUNCTION(0x2, "nand0"),         /* ALE */
                  SUNXI_FUNCTION(0x3, "spi0")),         /* MISO */
-       SUNXI_PIN(SUNXI_PINCTRL_PIN_PC2,
+       SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 2),
                  SUNXI_FUNCTION(0x0, "gpio_in"),
                  SUNXI_FUNCTION(0x1, "gpio_out"),
                  SUNXI_FUNCTION(0x2, "nand0"),         /* CLE */
                  SUNXI_FUNCTION(0x3, "spi0")),         /* CLK */
-       SUNXI_PIN(SUNXI_PINCTRL_PIN_PC3,
+       SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 3),
                  SUNXI_FUNCTION(0x0, "gpio_in"),
                  SUNXI_FUNCTION(0x1, "gpio_out"),
                  SUNXI_FUNCTION(0x2, "nand0")),        /* CE1 */
-       SUNXI_PIN(SUNXI_PINCTRL_PIN_PC4,
+       SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 4),
                  SUNXI_FUNCTION(0x0, "gpio_in"),
                  SUNXI_FUNCTION(0x1, "gpio_out"),
                  SUNXI_FUNCTION(0x2, "nand0")),        /* CE0 */
-       SUNXI_PIN(SUNXI_PINCTRL_PIN_PC5,
+       SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 5),
                  SUNXI_FUNCTION(0x0, "gpio_in"),
                  SUNXI_FUNCTION(0x1, "gpio_out"),
                  SUNXI_FUNCTION(0x2, "nand0")),        /* RE */
-       SUNXI_PIN(SUNXI_PINCTRL_PIN_PC6,
+       SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 6),
                  SUNXI_FUNCTION(0x0, "gpio_in"),
                  SUNXI_FUNCTION(0x1, "gpio_out"),
                  SUNXI_FUNCTION(0x2, "nand0"),         /* RB0 */
                  SUNXI_FUNCTION(0x3, "mmc2"),          /* CMD */
                  SUNXI_FUNCTION(0x4, "mmc3")),         /* CMD */
-       SUNXI_PIN(SUNXI_PINCTRL_PIN_PC7,
+       SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 7),
                  SUNXI_FUNCTION(0x0, "gpio_in"),
                  SUNXI_FUNCTION(0x1, "gpio_out"),
                  SUNXI_FUNCTION(0x2, "nand0"),         /* RB1 */
                  SUNXI_FUNCTION(0x3, "mmc2"),          /* CLK */
                  SUNXI_FUNCTION(0x4, "mmc3")),         /* CLK */
-       SUNXI_PIN(SUNXI_PINCTRL_PIN_PC8,
+       SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 8),
                  SUNXI_FUNCTION(0x0, "gpio_in"),
                  SUNXI_FUNCTION(0x1, "gpio_out"),
                  SUNXI_FUNCTION(0x2, "nand0"),         /* DQ0 */
                  SUNXI_FUNCTION(0x3, "mmc2"),          /* D0 */
                  SUNXI_FUNCTION(0x4, "mmc3")),         /* D0 */
-       SUNXI_PIN(SUNXI_PINCTRL_PIN_PC9,
+       SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 9),
                  SUNXI_FUNCTION(0x0, "gpio_in"),
                  SUNXI_FUNCTION(0x1, "gpio_out"),
                  SUNXI_FUNCTION(0x2, "nand0"),         /* DQ1 */
                  SUNXI_FUNCTION(0x3, "mmc2"),          /* D1 */
                  SUNXI_FUNCTION(0x4, "mmc3")),         /* D1 */
-       SUNXI_PIN(SUNXI_PINCTRL_PIN_PC10,
+       SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 10),
                  SUNXI_FUNCTION(0x0, "gpio_in"),
                  SUNXI_FUNCTION(0x1, "gpio_out"),
                  SUNXI_FUNCTION(0x2, "nand0"),         /* DQ2 */
                  SUNXI_FUNCTION(0x3, "mmc2"),          /* D2 */
                  SUNXI_FUNCTION(0x4, "mmc3")),         /* D2 */
-       SUNXI_PIN(SUNXI_PINCTRL_PIN_PC11,
+       SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 11),
                  SUNXI_FUNCTION(0x0, "gpio_in"),
                  SUNXI_FUNCTION(0x1, "gpio_out"),
                  SUNXI_FUNCTION(0x2, "nand0"),         /* DQ3 */
                  SUNXI_FUNCTION(0x3, "mmc2"),          /* D3 */
                  SUNXI_FUNCTION(0x4, "mmc3")),         /* D3 */
-       SUNXI_PIN(SUNXI_PINCTRL_PIN_PC12,
+       SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 12),
                  SUNXI_FUNCTION(0x0, "gpio_in"),
                  SUNXI_FUNCTION(0x1, "gpio_out"),
                  SUNXI_FUNCTION(0x2, "nand0"),         /* DQ4 */
                  SUNXI_FUNCTION(0x3, "mmc2"),          /* D4 */
                  SUNXI_FUNCTION(0x4, "mmc3")),         /* D4 */
-       SUNXI_PIN(SUNXI_PINCTRL_PIN_PC13,
+       SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 13),
                  SUNXI_FUNCTION(0x0, "gpio_in"),
                  SUNXI_FUNCTION(0x1, "gpio_out"),
                  SUNXI_FUNCTION(0x2, "nand0"),         /* DQ5 */
                  SUNXI_FUNCTION(0x3, "mmc2"),          /* D5 */
                  SUNXI_FUNCTION(0x4, "mmc3")),         /* D5 */
-       SUNXI_PIN(SUNXI_PINCTRL_PIN_PC14,
+       SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 14),
                  SUNXI_FUNCTION(0x0, "gpio_in"),
                  SUNXI_FUNCTION(0x1, "gpio_out"),
                  SUNXI_FUNCTION(0x2, "nand0"),         /* DQ6 */
                  SUNXI_FUNCTION(0x3, "mmc2"),          /* D6 */
                  SUNXI_FUNCTION(0x4, "mmc3")),         /* D6 */
-       SUNXI_PIN(SUNXI_PINCTRL_PIN_PC15,
+       SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 15),
                  SUNXI_FUNCTION(0x0, "gpio_in"),
                  SUNXI_FUNCTION(0x1, "gpio_out"),
                  SUNXI_FUNCTION(0x2, "nand0"),         /* DQ7 */
                  SUNXI_FUNCTION(0x3, "mmc2"),          /* D7 */
                  SUNXI_FUNCTION(0x4, "mmc3")),         /* D7 */
-       SUNXI_PIN(SUNXI_PINCTRL_PIN_PC16,
+       SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 16),
                  SUNXI_FUNCTION(0x0, "gpio_in"),
                  SUNXI_FUNCTION(0x1, "gpio_out"),
                  SUNXI_FUNCTION(0x2, "nand0"),         /* DQ8 */
                  SUNXI_FUNCTION(0x3, "nand1")),        /* DQ0 */
-       SUNXI_PIN(SUNXI_PINCTRL_PIN_PC17,
+       SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 17),
                  SUNXI_FUNCTION(0x0, "gpio_in"),
                  SUNXI_FUNCTION(0x1, "gpio_out"),
                  SUNXI_FUNCTION(0x2, "nand0"),         /* DQ9 */
                  SUNXI_FUNCTION(0x3, "nand1")),        /* DQ1 */
-       SUNXI_PIN(SUNXI_PINCTRL_PIN_PC18,
+       SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 18),
                  SUNXI_FUNCTION(0x0, "gpio_in"),
                  SUNXI_FUNCTION(0x1, "gpio_out"),
                  SUNXI_FUNCTION(0x2, "nand0"),         /* DQ10 */
                  SUNXI_FUNCTION(0x3, "nand1")),        /* DQ2 */
-       SUNXI_PIN(SUNXI_PINCTRL_PIN_PC19,
+       SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 19),
                  SUNXI_FUNCTION(0x0, "gpio_in"),
                  SUNXI_FUNCTION(0x1, "gpio_out"),
                  SUNXI_FUNCTION(0x2, "nand0"),         /* DQ11 */
                  SUNXI_FUNCTION(0x3, "nand1")),        /* DQ3 */
-       SUNXI_PIN(SUNXI_PINCTRL_PIN_PC20,
+       SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 20),
                  SUNXI_FUNCTION(0x0, "gpio_in"),
                  SUNXI_FUNCTION(0x1, "gpio_out"),
                  SUNXI_FUNCTION(0x2, "nand0"),         /* DQ12 */
                  SUNXI_FUNCTION(0x3, "nand1")),        /* DQ4 */
-       SUNXI_PIN(SUNXI_PINCTRL_PIN_PC21,
+       SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 21),
                  SUNXI_FUNCTION(0x0, "gpio_in"),
                  SUNXI_FUNCTION(0x1, "gpio_out"),
                  SUNXI_FUNCTION(0x2, "nand0"),         /* DQ13 */
                  SUNXI_FUNCTION(0x3, "nand1")),        /* DQ5 */
-       SUNXI_PIN(SUNXI_PINCTRL_PIN_PC22,
+       SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 22),
                  SUNXI_FUNCTION(0x0, "gpio_in"),
                  SUNXI_FUNCTION(0x1, "gpio_out"),
                  SUNXI_FUNCTION(0x2, "nand0"),         /* DQ14 */
                  SUNXI_FUNCTION(0x3, "nand1")),        /* DQ6 */
-       SUNXI_PIN(SUNXI_PINCTRL_PIN_PC23,
+       SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 23),
                  SUNXI_FUNCTION(0x0, "gpio_in"),
                  SUNXI_FUNCTION(0x1, "gpio_out"),
                  SUNXI_FUNCTION(0x2, "nand0"),         /* DQ15 */
                  SUNXI_FUNCTION(0x3, "nand1")),        /* DQ7 */
-       SUNXI_PIN(SUNXI_PINCTRL_PIN_PC24,
+       SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 24),
                  SUNXI_FUNCTION(0x0, "gpio_in"),
                  SUNXI_FUNCTION(0x1, "gpio_out"),
                  SUNXI_FUNCTION(0x2, "nand0"),         /* DQS */
                  SUNXI_FUNCTION(0x3, "mmc2"),          /* RST */
                  SUNXI_FUNCTION(0x4, "mmc3")),         /* RST */
-       SUNXI_PIN(SUNXI_PINCTRL_PIN_PC25,
+       SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 25),
                  SUNXI_FUNCTION(0x0, "gpio_in"),
                  SUNXI_FUNCTION(0x1, "gpio_out"),
                  SUNXI_FUNCTION(0x2, "nand0")),        /* CE2 */
-       SUNXI_PIN(SUNXI_PINCTRL_PIN_PC26,
+       SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 26),
                  SUNXI_FUNCTION(0x0, "gpio_in"),
                  SUNXI_FUNCTION(0x1, "gpio_out"),
                  SUNXI_FUNCTION(0x2, "nand0")),        /* CE3 */
-       SUNXI_PIN(SUNXI_PINCTRL_PIN_PC27,
+       SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 27),
                  SUNXI_FUNCTION(0x0, "gpio_in"),
                  SUNXI_FUNCTION(0x1, "gpio_out"),
                  SUNXI_FUNCTION(0x3, "spi0")),         /* CS0 */
        /* Hole */
-       SUNXI_PIN(SUNXI_PINCTRL_PIN_PD0,
+       SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 0),
                  SUNXI_FUNCTION(0x0, "gpio_in"),
                  SUNXI_FUNCTION(0x1, "gpio_out"),
                  SUNXI_FUNCTION(0x2, "lcd0"),          /* D0 */
                  SUNXI_FUNCTION(0x3, "lvds0")),        /* VP0 */
-       SUNXI_PIN(SUNXI_PINCTRL_PIN_PD1,
+       SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 1),
                  SUNXI_FUNCTION(0x0, "gpio_in"),
                  SUNXI_FUNCTION(0x1, "gpio_out"),
                  SUNXI_FUNCTION(0x2, "lcd0"),          /* D1 */
                  SUNXI_FUNCTION(0x3, "lvds0")),        /* VN0 */
-       SUNXI_PIN(SUNXI_PINCTRL_PIN_PD2,
+       SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 2),
                  SUNXI_FUNCTION(0x0, "gpio_in"),
                  SUNXI_FUNCTION(0x1, "gpio_out"),
                  SUNXI_FUNCTION(0x2, "lcd0"),          /* D2 */
                  SUNXI_FUNCTION(0x3, "lvds0")),        /* VP1 */
-       SUNXI_PIN(SUNXI_PINCTRL_PIN_PD3,
+       SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 3),
                  SUNXI_FUNCTION(0x0, "gpio_in"),
                  SUNXI_FUNCTION(0x1, "gpio_out"),
                  SUNXI_FUNCTION(0x2, "lcd0"),          /* D3 */
                  SUNXI_FUNCTION(0x3, "lvds0")),        /* VN1 */
-       SUNXI_PIN(SUNXI_PINCTRL_PIN_PD4,
+       SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 4),
                  SUNXI_FUNCTION(0x0, "gpio_in"),
                  SUNXI_FUNCTION(0x1, "gpio_out"),
                  SUNXI_FUNCTION(0x2, "lcd0"),          /* D4 */
                  SUNXI_FUNCTION(0x3, "lvds0")),        /* VP2 */
-       SUNXI_PIN(SUNXI_PINCTRL_PIN_PD5,
+       SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 5),
                  SUNXI_FUNCTION(0x0, "gpio_in"),
                  SUNXI_FUNCTION(0x1, "gpio_out"),
                  SUNXI_FUNCTION(0x2, "lcd0"),          /* D5 */
                  SUNXI_FUNCTION(0x3, "lvds0")),        /* VN2 */
-       SUNXI_PIN(SUNXI_PINCTRL_PIN_PD6,
+       SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 6),
                  SUNXI_FUNCTION(0x0, "gpio_in"),
                  SUNXI_FUNCTION(0x1, "gpio_out"),
                  SUNXI_FUNCTION(0x2, "lcd0"),          /* D6 */
                  SUNXI_FUNCTION(0x3, "lvds0")),        /* VPC */
-       SUNXI_PIN(SUNXI_PINCTRL_PIN_PD7,
+       SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 7),
                  SUNXI_FUNCTION(0x0, "gpio_in"),
                  SUNXI_FUNCTION(0x1, "gpio_out"),
                  SUNXI_FUNCTION(0x2, "lcd0"),          /* D7 */
                  SUNXI_FUNCTION(0x3, "lvds0")),        /* VNC */
-       SUNXI_PIN(SUNXI_PINCTRL_PIN_PD8,
+       SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 8),
                  SUNXI_FUNCTION(0x0, "gpio_in"),
                  SUNXI_FUNCTION(0x1, "gpio_out"),
                  SUNXI_FUNCTION(0x2, "lcd0"),          /* D8 */
                  SUNXI_FUNCTION(0x3, "lvds0")),        /* VP3 */
-       SUNXI_PIN(SUNXI_PINCTRL_PIN_PD9,
+       SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 9),
                  SUNXI_FUNCTION(0x0, "gpio_in"),
                  SUNXI_FUNCTION(0x1, "gpio_out"),
                  SUNXI_FUNCTION(0x2, "lcd0"),          /* D9 */
                  SUNXI_FUNCTION(0x3, "lvds0")),        /* VN3 */
-       SUNXI_PIN(SUNXI_PINCTRL_PIN_PD10,
+       SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 10),
                  SUNXI_FUNCTION(0x0, "gpio_in"),
                  SUNXI_FUNCTION(0x1, "gpio_out"),
                  SUNXI_FUNCTION(0x2, "lcd0"),          /* D10 */
                  SUNXI_FUNCTION(0x3, "lvds1")),        /* VP0 */
-       SUNXI_PIN(SUNXI_PINCTRL_PIN_PD11,
+       SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 11),
                  SUNXI_FUNCTION(0x0, "gpio_in"),
                  SUNXI_FUNCTION(0x1, "gpio_out"),
                  SUNXI_FUNCTION(0x2, "lcd0"),          /* D11 */
                  SUNXI_FUNCTION(0x3, "lvds1")),        /* VN0 */
-       SUNXI_PIN(SUNXI_PINCTRL_PIN_PD12,
+       SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 12),
                  SUNXI_FUNCTION(0x0, "gpio_in"),
                  SUNXI_FUNCTION(0x1, "gpio_out"),
                  SUNXI_FUNCTION(0x2, "lcd0"),          /* D12 */
                  SUNXI_FUNCTION(0x3, "lvds1")),        /* VP1 */
-       SUNXI_PIN(SUNXI_PINCTRL_PIN_PD13,
+       SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 13),
                  SUNXI_FUNCTION(0x0, "gpio_in"),
                  SUNXI_FUNCTION(0x1, "gpio_out"),
                  SUNXI_FUNCTION(0x2, "lcd0"),          /* D13 */
                  SUNXI_FUNCTION(0x3, "lvds1")),        /* VN1 */
-       SUNXI_PIN(SUNXI_PINCTRL_PIN_PD14,
+       SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 14),
                  SUNXI_FUNCTION(0x0, "gpio_in"),
                  SUNXI_FUNCTION(0x1, "gpio_out"),
                  SUNXI_FUNCTION(0x2, "lcd0"),          /* D14 */
                  SUNXI_FUNCTION(0x3, "lvds1")),        /* VP2 */
-       SUNXI_PIN(SUNXI_PINCTRL_PIN_PD15,
+       SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 15),
                  SUNXI_FUNCTION(0x0, "gpio_in"),
                  SUNXI_FUNCTION(0x1, "gpio_out"),
                  SUNXI_FUNCTION(0x2, "lcd0"),          /* D15 */
                  SUNXI_FUNCTION(0x3, "lvds1")),        /* VN2 */
-       SUNXI_PIN(SUNXI_PINCTRL_PIN_PD16,
+       SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 16),
                  SUNXI_FUNCTION(0x0, "gpio_in"),
                  SUNXI_FUNCTION(0x1, "gpio_out"),
                  SUNXI_FUNCTION(0x2, "lcd0"),          /* D16 */
                  SUNXI_FUNCTION(0x3, "lvds1")),        /* VPC */
-       SUNXI_PIN(SUNXI_PINCTRL_PIN_PD17,
+       SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 17),
                  SUNXI_FUNCTION(0x0, "gpio_in"),
                  SUNXI_FUNCTION(0x1, "gpio_out"),
                  SUNXI_FUNCTION(0x2, "lcd0"),          /* D17 */
                  SUNXI_FUNCTION(0x3, "lvds1")),        /* VNC */
-       SUNXI_PIN(SUNXI_PINCTRL_PIN_PD18,
+       SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 18),
                  SUNXI_FUNCTION(0x0, "gpio_in"),
                  SUNXI_FUNCTION(0x1, "gpio_out"),
                  SUNXI_FUNCTION(0x2, "lcd0"),          /* D18 */
                  SUNXI_FUNCTION(0x3, "lvds1")),        /* VP3 */
-       SUNXI_PIN(SUNXI_PINCTRL_PIN_PD19,
+       SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 19),
                  SUNXI_FUNCTION(0x0, "gpio_in"),
                  SUNXI_FUNCTION(0x1, "gpio_out"),
                  SUNXI_FUNCTION(0x2, "lcd0"),          /* D19 */
                  SUNXI_FUNCTION(0x3, "lvds1")),        /* VN3 */
-       SUNXI_PIN(SUNXI_PINCTRL_PIN_PD20,
+       SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 20),
                  SUNXI_FUNCTION(0x0, "gpio_in"),
                  SUNXI_FUNCTION(0x1, "gpio_out"),
                  SUNXI_FUNCTION(0x2, "lcd0")),         /* D20 */
-       SUNXI_PIN(SUNXI_PINCTRL_PIN_PD21,
+       SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 21),
                  SUNXI_FUNCTION(0x0, "gpio_in"),
                  SUNXI_FUNCTION(0x1, "gpio_out"),
                  SUNXI_FUNCTION(0x2, "lcd0")),         /* D21 */
-       SUNXI_PIN(SUNXI_PINCTRL_PIN_PD22,
+       SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 22),
                  SUNXI_FUNCTION(0x0, "gpio_in"),
                  SUNXI_FUNCTION(0x1, "gpio_out"),
                  SUNXI_FUNCTION(0x2, "lcd0")),         /* D22 */
-       SUNXI_PIN(SUNXI_PINCTRL_PIN_PD23,
+       SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 23),
                  SUNXI_FUNCTION(0x0, "gpio_in"),
                  SUNXI_FUNCTION(0x1, "gpio_out"),
                  SUNXI_FUNCTION(0x2, "lcd0")),         /* D23 */
-       SUNXI_PIN(SUNXI_PINCTRL_PIN_PD24,
+       SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 24),
                  SUNXI_FUNCTION(0x0, "gpio_in"),
                  SUNXI_FUNCTION(0x1, "gpio_out"),
                  SUNXI_FUNCTION(0x2, "lcd0")),         /* CLK */
-       SUNXI_PIN(SUNXI_PINCTRL_PIN_PD25,
+       SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 25),
                  SUNXI_FUNCTION(0x0, "gpio_in"),
                  SUNXI_FUNCTION(0x1, "gpio_out"),
                  SUNXI_FUNCTION(0x2, "lcd0")),         /* DE */
-       SUNXI_PIN(SUNXI_PINCTRL_PIN_PD26,
+       SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 26),
                  SUNXI_FUNCTION(0x0, "gpio_in"),
                  SUNXI_FUNCTION(0x1, "gpio_out"),
                  SUNXI_FUNCTION(0x2, "lcd0")),         /* HSYNC */
-       SUNXI_PIN(SUNXI_PINCTRL_PIN_PD27,
+       SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 27),
                  SUNXI_FUNCTION(0x0, "gpio_in"),
                  SUNXI_FUNCTION(0x1, "gpio_out"),
                  SUNXI_FUNCTION(0x2, "lcd0")),         /* VSYNC */
        /* Hole */
-       SUNXI_PIN(SUNXI_PINCTRL_PIN_PE0,
+       SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 0),
                  SUNXI_FUNCTION(0x0, "gpio_in"),
                  SUNXI_FUNCTION(0x1, "gpio_out"),
                  SUNXI_FUNCTION(0x2, "csi"),           /* PCLK */
                  SUNXI_FUNCTION(0x3, "ts")),           /* CLK */
-       SUNXI_PIN(SUNXI_PINCTRL_PIN_PE1,
+       SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 1),
                  SUNXI_FUNCTION(0x0, "gpio_in"),
                  SUNXI_FUNCTION(0x1, "gpio_out"),
                  SUNXI_FUNCTION(0x2, "csi"),           /* MCLK */
                  SUNXI_FUNCTION(0x3, "ts")),           /* ERR */
-       SUNXI_PIN(SUNXI_PINCTRL_PIN_PE2,
+       SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 2),
                  SUNXI_FUNCTION(0x0, "gpio_in"),
                  SUNXI_FUNCTION(0x1, "gpio_out"),
                  SUNXI_FUNCTION(0x2, "csi"),           /* HSYNC */
                  SUNXI_FUNCTION(0x3, "ts")),           /* SYNC */
-       SUNXI_PIN(SUNXI_PINCTRL_PIN_PE3,
+       SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 3),
                  SUNXI_FUNCTION(0x0, "gpio_in"),
                  SUNXI_FUNCTION(0x1, "gpio_out"),
                  SUNXI_FUNCTION(0x2, "csi"),           /* VSYNC */
                  SUNXI_FUNCTION(0x3, "ts")),           /* DVLD */
-       SUNXI_PIN(SUNXI_PINCTRL_PIN_PE4,
+       SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 4),
                  SUNXI_FUNCTION(0x0, "gpio_in"),
                  SUNXI_FUNCTION(0x1, "gpio_out"),
                  SUNXI_FUNCTION(0x2, "csi"),           /* D0 */
                  SUNXI_FUNCTION(0x3, "uart5")),        /* TX */
-       SUNXI_PIN(SUNXI_PINCTRL_PIN_PE5,
+       SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 5),
                  SUNXI_FUNCTION(0x0, "gpio_in"),
                  SUNXI_FUNCTION(0x1, "gpio_out"),
                  SUNXI_FUNCTION(0x2, "csi"),           /* D1 */
                  SUNXI_FUNCTION(0x3, "uart5")),        /* RX */
-       SUNXI_PIN(SUNXI_PINCTRL_PIN_PE6,
+       SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 6),
                  SUNXI_FUNCTION(0x0, "gpio_in"),
                  SUNXI_FUNCTION(0x1, "gpio_out"),
                  SUNXI_FUNCTION(0x2, "csi"),           /* D2 */
                  SUNXI_FUNCTION(0x3, "uart5")),        /* RTS */
-       SUNXI_PIN(SUNXI_PINCTRL_PIN_PE7,
+       SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 7),
                  SUNXI_FUNCTION(0x0, "gpio_in"),
                  SUNXI_FUNCTION(0x1, "gpio_out"),
                  SUNXI_FUNCTION(0x2, "csi"),           /* D3 */
                  SUNXI_FUNCTION(0x3, "uart5")),        /* CTS */
-       SUNXI_PIN(SUNXI_PINCTRL_PIN_PE8,
+       SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 8),
                  SUNXI_FUNCTION(0x0, "gpio_in"),
                  SUNXI_FUNCTION(0x1, "gpio_out"),
                  SUNXI_FUNCTION(0x2, "csi"),           /* D4 */
                  SUNXI_FUNCTION(0x3, "ts")),           /* D0 */
-       SUNXI_PIN(SUNXI_PINCTRL_PIN_PE9,
+       SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 9),
                  SUNXI_FUNCTION(0x0, "gpio_in"),
                  SUNXI_FUNCTION(0x1, "gpio_out"),
                  SUNXI_FUNCTION(0x2, "csi"),           /* D5 */
                  SUNXI_FUNCTION(0x3, "ts")),           /* D1 */
-       SUNXI_PIN(SUNXI_PINCTRL_PIN_PE10,
+       SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 10),
                  SUNXI_FUNCTION(0x0, "gpio_in"),
                  SUNXI_FUNCTION(0x1, "gpio_out"),
                  SUNXI_FUNCTION(0x2, "csi"),           /* D6 */
                  SUNXI_FUNCTION(0x3, "ts")),           /* D2 */
-       SUNXI_PIN(SUNXI_PINCTRL_PIN_PE11,
+       SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 11),
                  SUNXI_FUNCTION(0x0, "gpio_in"),
                  SUNXI_FUNCTION(0x1, "gpio_out"),
                  SUNXI_FUNCTION(0x2, "csi"),           /* D7 */
                  SUNXI_FUNCTION(0x3, "ts")),           /* D3 */
-       SUNXI_PIN(SUNXI_PINCTRL_PIN_PE12,
+       SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 12),
                  SUNXI_FUNCTION(0x0, "gpio_in"),
                  SUNXI_FUNCTION(0x1, "gpio_out"),
                  SUNXI_FUNCTION(0x2, "csi"),           /* D8 */
                  SUNXI_FUNCTION(0x3, "ts")),           /* D4 */
-       SUNXI_PIN(SUNXI_PINCTRL_PIN_PE13,
+       SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 13),
                  SUNXI_FUNCTION(0x0, "gpio_in"),
                  SUNXI_FUNCTION(0x1, "gpio_out"),
                  SUNXI_FUNCTION(0x2, "csi"),           /* D9 */
                  SUNXI_FUNCTION(0x3, "ts")),           /* D5 */
-       SUNXI_PIN(SUNXI_PINCTRL_PIN_PE14,
+       SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 14),
                  SUNXI_FUNCTION(0x0, "gpio_in"),
                  SUNXI_FUNCTION(0x1, "gpio_out"),
                  SUNXI_FUNCTION(0x2, "csi"),           /* D10 */
                  SUNXI_FUNCTION(0x3, "ts")),           /* D6 */
-       SUNXI_PIN(SUNXI_PINCTRL_PIN_PE15,
+       SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 15),
                  SUNXI_FUNCTION(0x0, "gpio_in"),
                  SUNXI_FUNCTION(0x1, "gpio_out"),
                  SUNXI_FUNCTION(0x2, "csi"),           /* D11 */
                  SUNXI_FUNCTION(0x3, "ts")),           /* D7 */
-       SUNXI_PIN(SUNXI_PINCTRL_PIN_PE16,
+       SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 16),
                  SUNXI_FUNCTION(0x0, "gpio_in"),
                  SUNXI_FUNCTION(0x1, "gpio_out"),
                  SUNXI_FUNCTION(0x2, "csi")),          /* MIPI CSI MCLK */
        /* Hole */
-       SUNXI_PIN(SUNXI_PINCTRL_PIN_PF0,
+       SUNXI_PIN(SUNXI_PINCTRL_PIN(F, 0),
                  SUNXI_FUNCTION(0x0, "gpio_in"),
                  SUNXI_FUNCTION(0x1, "gpio_out"),
                  SUNXI_FUNCTION(0x2, "mmc0"),          /* D1 */
                  SUNXI_FUNCTION(0x4, "jtag")),         /* MS1 */
-       SUNXI_PIN(SUNXI_PINCTRL_PIN_PF1,
+       SUNXI_PIN(SUNXI_PINCTRL_PIN(F, 1),
                  SUNXI_FUNCTION(0x0, "gpio_in"),
                  SUNXI_FUNCTION(0x1, "gpio_out"),
                  SUNXI_FUNCTION(0x2, "mmc0"),          /* D0 */
                  SUNXI_FUNCTION(0x4, "jtag")),         /* DI1 */
-       SUNXI_PIN(SUNXI_PINCTRL_PIN_PF2,
+       SUNXI_PIN(SUNXI_PINCTRL_PIN(F, 2),
                  SUNXI_FUNCTION(0x0, "gpio_in"),
                  SUNXI_FUNCTION(0x1, "gpio_out"),
                  SUNXI_FUNCTION(0x2, "mmc0"),          /* CLK */
                  SUNXI_FUNCTION(0x4, "uart0")),        /* TX */
-       SUNXI_PIN(SUNXI_PINCTRL_PIN_PF3,
+       SUNXI_PIN(SUNXI_PINCTRL_PIN(F, 3),
                  SUNXI_FUNCTION(0x0, "gpio_in"),
                  SUNXI_FUNCTION(0x1, "gpio_out"),
                  SUNXI_FUNCTION(0x2, "mmc0"),          /* CMD */
                  SUNXI_FUNCTION(0x4, "jtag")),         /* DO1 */
-       SUNXI_PIN(SUNXI_PINCTRL_PIN_PF4,
+       SUNXI_PIN(SUNXI_PINCTRL_PIN(F, 4),
                  SUNXI_FUNCTION(0x0, "gpio_in"),
                  SUNXI_FUNCTION(0x1, "gpio_out"),
                  SUNXI_FUNCTION(0x2, "mmc0"),          /* D3 */
                  SUNXI_FUNCTION(0x4, "uart0")),        /* RX */
-       SUNXI_PIN(SUNXI_PINCTRL_PIN_PF5,
+       SUNXI_PIN(SUNXI_PINCTRL_PIN(F, 5),
                  SUNXI_FUNCTION(0x0, "gpio_in"),
                  SUNXI_FUNCTION(0x1, "gpio_out"),
                  SUNXI_FUNCTION(0x2, "mmc0"),          /* D2 */
                  SUNXI_FUNCTION(0x4, "jtag")),         /* CK1 */
        /* Hole */
-       SUNXI_PIN(SUNXI_PINCTRL_PIN_PG0,
+       SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 0),
                  SUNXI_FUNCTION(0x0, "gpio_in"),
                  SUNXI_FUNCTION(0x1, "gpio_out"),
                  SUNXI_FUNCTION(0x2, "mmc1")),         /* CLK */
-       SUNXI_PIN(SUNXI_PINCTRL_PIN_PG1,
+       SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 1),
                  SUNXI_FUNCTION(0x0, "gpio_in"),
                  SUNXI_FUNCTION(0x1, "gpio_out"),
                  SUNXI_FUNCTION(0x2, "mmc1")),         /* CMD */
-       SUNXI_PIN(SUNXI_PINCTRL_PIN_PG2,
+       SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 2),
                  SUNXI_FUNCTION(0x0, "gpio_in"),
                  SUNXI_FUNCTION(0x1, "gpio_out"),
                  SUNXI_FUNCTION(0x2, "mmc1")),         /* D0 */
-       SUNXI_PIN(SUNXI_PINCTRL_PIN_PG3,
+       SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 3),
                  SUNXI_FUNCTION(0x0, "gpio_in"),
                  SUNXI_FUNCTION(0x1, "gpio_out"),
                  SUNXI_FUNCTION(0x2, "mmc1")),         /* D1 */
-       SUNXI_PIN(SUNXI_PINCTRL_PIN_PG4,
+       SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 4),
                  SUNXI_FUNCTION(0x0, "gpio_in"),
                  SUNXI_FUNCTION(0x1, "gpio_out"),
                  SUNXI_FUNCTION(0x2, "mmc1")),         /* D2 */
-       SUNXI_PIN(SUNXI_PINCTRL_PIN_PG5,
+       SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 5),
                  SUNXI_FUNCTION(0x0, "gpio_in"),
                  SUNXI_FUNCTION(0x1, "gpio_out"),
                  SUNXI_FUNCTION(0x2, "mmc1")),         /* D3 */
-       SUNXI_PIN(SUNXI_PINCTRL_PIN_PG6,
+       SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 6),
                  SUNXI_FUNCTION(0x0, "gpio_in"),
                  SUNXI_FUNCTION(0x1, "gpio_out"),
                  SUNXI_FUNCTION(0x2, "uart2")),        /* TX */
-       SUNXI_PIN(SUNXI_PINCTRL_PIN_PG7,
+       SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 7),
                  SUNXI_FUNCTION(0x0, "gpio_in"),
                  SUNXI_FUNCTION(0x1, "gpio_out"),
                  SUNXI_FUNCTION(0x2, "uart2")),        /* RX */
-       SUNXI_PIN(SUNXI_PINCTRL_PIN_PG8,
+       SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 8),
                  SUNXI_FUNCTION(0x0, "gpio_in"),
                  SUNXI_FUNCTION(0x1, "gpio_out"),
                  SUNXI_FUNCTION(0x2, "uart2")),        /* RTS */
-       SUNXI_PIN(SUNXI_PINCTRL_PIN_PG9,
+       SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 9),
                  SUNXI_FUNCTION(0x0, "gpio_in"),
                  SUNXI_FUNCTION(0x1, "gpio_out"),
                  SUNXI_FUNCTION(0x2, "uart2")),        /* CTS */
-       SUNXI_PIN(SUNXI_PINCTRL_PIN_PG10,
+       SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 10),
                  SUNXI_FUNCTION(0x0, "gpio_in"),
                  SUNXI_FUNCTION(0x1, "gpio_out"),
                  SUNXI_FUNCTION(0x2, "i2c3"),          /* SCK */
                  SUNXI_FUNCTION(0x3, "usb")),          /* DP3 */
-       SUNXI_PIN(SUNXI_PINCTRL_PIN_PG11,
+       SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 11),
                  SUNXI_FUNCTION(0x0, "gpio_in"),
                  SUNXI_FUNCTION(0x1, "gpio_out"),
                  SUNXI_FUNCTION(0x2, "i2c3"),          /* SDA */
                  SUNXI_FUNCTION(0x3, "usb")),          /* DM3 */
-       SUNXI_PIN(SUNXI_PINCTRL_PIN_PG12,
+       SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 12),
                  SUNXI_FUNCTION(0x0, "gpio_in"),
                  SUNXI_FUNCTION(0x1, "gpio_out"),
                  SUNXI_FUNCTION(0x2, "spi1"),          /* CS1 */
                  SUNXI_FUNCTION(0x3, "i2s1")),         /* MCLK */
-       SUNXI_PIN(SUNXI_PINCTRL_PIN_PG13,
+       SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 13),
                  SUNXI_FUNCTION(0x0, "gpio_in"),
                  SUNXI_FUNCTION(0x1, "gpio_out"),
                  SUNXI_FUNCTION(0x2, "spi1"),          /* CS0 */
                  SUNXI_FUNCTION(0x3, "i2s1")),         /* BCLK */
-       SUNXI_PIN(SUNXI_PINCTRL_PIN_PG14,
+       SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 14),
                  SUNXI_FUNCTION(0x0, "gpio_in"),
                  SUNXI_FUNCTION(0x1, "gpio_out"),
                  SUNXI_FUNCTION(0x2, "spi1"),          /* CLK */
                  SUNXI_FUNCTION(0x3, "i2s1")),         /* LRCK */
-       SUNXI_PIN(SUNXI_PINCTRL_PIN_PG15,
+       SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 15),
                  SUNXI_FUNCTION(0x0, "gpio_in"),
                  SUNXI_FUNCTION(0x1, "gpio_out"),
                  SUNXI_FUNCTION(0x2, "spi1"),          /* MOSI */
                  SUNXI_FUNCTION(0x3, "i2s1")),         /* DIN */
-       SUNXI_PIN(SUNXI_PINCTRL_PIN_PG16,
+       SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 16),
                  SUNXI_FUNCTION(0x0, "gpio_in"),
                  SUNXI_FUNCTION(0x1, "gpio_out"),
                  SUNXI_FUNCTION(0x2, "spi1"),          /* MISO */
                  SUNXI_FUNCTION(0x3, "i2s1")),         /* DOUT */
-       SUNXI_PIN(SUNXI_PINCTRL_PIN_PG17,
+       SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 17),
                  SUNXI_FUNCTION(0x0, "gpio_in"),
                  SUNXI_FUNCTION(0x1, "gpio_out"),
                  SUNXI_FUNCTION(0x2, "uart4")),        /* TX */
-       SUNXI_PIN(SUNXI_PINCTRL_PIN_PG18,
+       SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 18),
                  SUNXI_FUNCTION(0x0, "gpio_in"),
                  SUNXI_FUNCTION(0x1, "gpio_out"),
                  SUNXI_FUNCTION(0x2, "uart4")),        /* RX */
        /* Hole */
-       SUNXI_PIN(SUNXI_PINCTRL_PIN_PH0,
+       SUNXI_PIN(SUNXI_PINCTRL_PIN(H, 0),
                  SUNXI_FUNCTION(0x0, "gpio_in"),
                  SUNXI_FUNCTION(0x1, "gpio_out"),
                  SUNXI_FUNCTION(0x2, "nand1")),        /* WE */
-       SUNXI_PIN(SUNXI_PINCTRL_PIN_PH1,
+       SUNXI_PIN(SUNXI_PINCTRL_PIN(H, 1),
                  SUNXI_FUNCTION(0x0, "gpio_in"),
                  SUNXI_FUNCTION(0x1, "gpio_out"),
                  SUNXI_FUNCTION(0x2, "nand1")),        /* ALE */
-       SUNXI_PIN(SUNXI_PINCTRL_PIN_PH2,
+       SUNXI_PIN(SUNXI_PINCTRL_PIN(H, 2),
                  SUNXI_FUNCTION(0x0, "gpio_in"),
                  SUNXI_FUNCTION(0x1, "gpio_out"),
                  SUNXI_FUNCTION(0x2, "nand1")),        /* CLE */
-       SUNXI_PIN(SUNXI_PINCTRL_PIN_PH3,
+       SUNXI_PIN(SUNXI_PINCTRL_PIN(H, 3),
                  SUNXI_FUNCTION(0x0, "gpio_in"),
                  SUNXI_FUNCTION(0x1, "gpio_out"),
                  SUNXI_FUNCTION(0x2, "nand1")),        /* CE1 */
-       SUNXI_PIN(SUNXI_PINCTRL_PIN_PH4,
+       SUNXI_PIN(SUNXI_PINCTRL_PIN(H, 4),
                  SUNXI_FUNCTION(0x0, "gpio_in"),
                  SUNXI_FUNCTION(0x1, "gpio_out"),
                  SUNXI_FUNCTION(0x2, "nand1")),        /* CE0 */
-       SUNXI_PIN(SUNXI_PINCTRL_PIN_PH5,
+       SUNXI_PIN(SUNXI_PINCTRL_PIN(H, 5),
                  SUNXI_FUNCTION(0x0, "gpio_in"),
                  SUNXI_FUNCTION(0x1, "gpio_out"),
                  SUNXI_FUNCTION(0x2, "nand1")),        /* RE */
-       SUNXI_PIN(SUNXI_PINCTRL_PIN_PH6,
+       SUNXI_PIN(SUNXI_PINCTRL_PIN(H, 6),
                  SUNXI_FUNCTION(0x0, "gpio_in"),
                  SUNXI_FUNCTION(0x1, "gpio_out"),
                  SUNXI_FUNCTION(0x2, "nand1")),        /* RB0 */
-       SUNXI_PIN(SUNXI_PINCTRL_PIN_PH7,
+       SUNXI_PIN(SUNXI_PINCTRL_PIN(H, 7),
                  SUNXI_FUNCTION(0x0, "gpio_in"),
                  SUNXI_FUNCTION(0x1, "gpio_out"),
                  SUNXI_FUNCTION(0x2, "nand1")),        /* RB1 */
-       SUNXI_PIN(SUNXI_PINCTRL_PIN_PH8,
+       SUNXI_PIN(SUNXI_PINCTRL_PIN(H, 8),
                  SUNXI_FUNCTION(0x0, "gpio_in"),
                  SUNXI_FUNCTION(0x1, "gpio_out"),
                  SUNXI_FUNCTION(0x2, "nand1")),        /* DQS */
-       SUNXI_PIN(SUNXI_PINCTRL_PIN_PH9,
+       SUNXI_PIN(SUNXI_PINCTRL_PIN(H, 9),
                  SUNXI_FUNCTION(0x0, "gpio_in"),
                  SUNXI_FUNCTION(0x1, "gpio_out"),
                  SUNXI_FUNCTION(0x2, "spi2"),          /* CS0 */
                  SUNXI_FUNCTION(0x3, "jtag"),          /* MS0 */
                  SUNXI_FUNCTION(0x4, "pwm1")),         /* Positive */
-       SUNXI_PIN(SUNXI_PINCTRL_PIN_PH10,
+       SUNXI_PIN(SUNXI_PINCTRL_PIN(H, 10),
                  SUNXI_FUNCTION(0x0, "gpio_in"),
                  SUNXI_FUNCTION(0x1, "gpio_out"),
                  SUNXI_FUNCTION(0x2, "spi2"),          /* CLK */
                  SUNXI_FUNCTION(0x3, "jtag"),          /* CK0 */
                  SUNXI_FUNCTION(0x4, "pwm1")),         /* Negative */
-       SUNXI_PIN(SUNXI_PINCTRL_PIN_PH11,
+       SUNXI_PIN(SUNXI_PINCTRL_PIN(H, 11),
                  SUNXI_FUNCTION(0x0, "gpio_in"),
                  SUNXI_FUNCTION(0x1, "gpio_out"),
                  SUNXI_FUNCTION(0x2, "spi2"),          /* MOSI */
                  SUNXI_FUNCTION(0x3, "jtag"),          /* DO0 */
                  SUNXI_FUNCTION(0x4, "pwm2")),         /* Positive */
-       SUNXI_PIN(SUNXI_PINCTRL_PIN_PH12,
+       SUNXI_PIN(SUNXI_PINCTRL_PIN(H, 12),
                  SUNXI_FUNCTION(0x0, "gpio_in"),
                  SUNXI_FUNCTION(0x1, "gpio_out"),
                  SUNXI_FUNCTION(0x2, "spi2"),          /* MISO */
                  SUNXI_FUNCTION(0x3, "jtag"),          /* DI0 */
                  SUNXI_FUNCTION(0x4, "pwm2")),         /* Negative */
-       SUNXI_PIN(SUNXI_PINCTRL_PIN_PH13,
+       SUNXI_PIN(SUNXI_PINCTRL_PIN(H, 13),
                  SUNXI_FUNCTION(0x0, "gpio_in"),
                  SUNXI_FUNCTION(0x1, "gpio_out"),
                  SUNXI_FUNCTION(0x2, "pwm0")),
-       SUNXI_PIN(SUNXI_PINCTRL_PIN_PH14,
+       SUNXI_PIN(SUNXI_PINCTRL_PIN(H, 14),
                  SUNXI_FUNCTION(0x0, "gpio_in"),
                  SUNXI_FUNCTION(0x1, "gpio_out"),
                  SUNXI_FUNCTION(0x2, "i2c0")),         /* SCK */
-       SUNXI_PIN(SUNXI_PINCTRL_PIN_PH15,
+       SUNXI_PIN(SUNXI_PINCTRL_PIN(H, 15),
                  SUNXI_FUNCTION(0x0, "gpio_in"),
                  SUNXI_FUNCTION(0x1, "gpio_out"),
                  SUNXI_FUNCTION(0x2, "i2c0")),         /* SDA */
-       SUNXI_PIN(SUNXI_PINCTRL_PIN_PH16,
+       SUNXI_PIN(SUNXI_PINCTRL_PIN(H, 16),
                  SUNXI_FUNCTION(0x0, "gpio_in"),
                  SUNXI_FUNCTION(0x1, "gpio_out"),
                  SUNXI_FUNCTION(0x2, "i2c1")),         /* SCK */
-       SUNXI_PIN(SUNXI_PINCTRL_PIN_PH17,
+       SUNXI_PIN(SUNXI_PINCTRL_PIN(H, 17),
                  SUNXI_FUNCTION(0x0, "gpio_in"),
                  SUNXI_FUNCTION(0x1, "gpio_out"),
                  SUNXI_FUNCTION(0x2, "i2c1")),         /* SDA */
-       SUNXI_PIN(SUNXI_PINCTRL_PIN_PH18,
+       SUNXI_PIN(SUNXI_PINCTRL_PIN(H, 18),
                  SUNXI_FUNCTION(0x0, "gpio_in"),
                  SUNXI_FUNCTION(0x1, "gpio_out"),
                  SUNXI_FUNCTION(0x2, "i2c2")),         /* SCK */
-       SUNXI_PIN(SUNXI_PINCTRL_PIN_PH19,
+       SUNXI_PIN(SUNXI_PINCTRL_PIN(H, 19),
                  SUNXI_FUNCTION(0x0, "gpio_in"),
                  SUNXI_FUNCTION(0x1, "gpio_out"),
                  SUNXI_FUNCTION(0x2, "i2c2")),         /* SDA */
-       SUNXI_PIN(SUNXI_PINCTRL_PIN_PH20,
+       SUNXI_PIN(SUNXI_PINCTRL_PIN(H, 20),
                  SUNXI_FUNCTION(0x0, "gpio_in"),
                  SUNXI_FUNCTION(0x1, "gpio_out"),
                  SUNXI_FUNCTION(0x2, "uart0")),        /* TX */
-       SUNXI_PIN(SUNXI_PINCTRL_PIN_PH21,
+       SUNXI_PIN(SUNXI_PINCTRL_PIN(H, 21),
                  SUNXI_FUNCTION(0x0, "gpio_in"),
                  SUNXI_FUNCTION(0x1, "gpio_out"),
                  SUNXI_FUNCTION(0x2, "uart0")),        /* RX */
-       SUNXI_PIN(SUNXI_PINCTRL_PIN_PH22,
+       SUNXI_PIN(SUNXI_PINCTRL_PIN(H, 22),
                  SUNXI_FUNCTION(0x0, "gpio_in"),
                  SUNXI_FUNCTION(0x1, "gpio_out")),
-       SUNXI_PIN(SUNXI_PINCTRL_PIN_PH23,
+       SUNXI_PIN(SUNXI_PINCTRL_PIN(H, 23),
                  SUNXI_FUNCTION(0x0, "gpio_in"),
                  SUNXI_FUNCTION(0x1, "gpio_out")),
-       SUNXI_PIN(SUNXI_PINCTRL_PIN_PH24,
+       SUNXI_PIN(SUNXI_PINCTRL_PIN(H, 24),
                  SUNXI_FUNCTION(0x0, "gpio_in"),
                  SUNXI_FUNCTION(0x1, "gpio_out")),
-       SUNXI_PIN(SUNXI_PINCTRL_PIN_PH25,
+       SUNXI_PIN(SUNXI_PINCTRL_PIN(H, 25),
                  SUNXI_FUNCTION(0x0, "gpio_in"),
                  SUNXI_FUNCTION(0x1, "gpio_out")),
-       SUNXI_PIN(SUNXI_PINCTRL_PIN_PH26,
+       SUNXI_PIN(SUNXI_PINCTRL_PIN(H, 26),
                  SUNXI_FUNCTION(0x0, "gpio_in"),
                  SUNXI_FUNCTION(0x1, "gpio_out")),
-       SUNXI_PIN(SUNXI_PINCTRL_PIN_PH27,
+       SUNXI_PIN(SUNXI_PINCTRL_PIN(H, 27),
                  SUNXI_FUNCTION(0x0, "gpio_in"),
                  SUNXI_FUNCTION(0x1, "gpio_out")),
-       SUNXI_PIN(SUNXI_PINCTRL_PIN_PH28,
+       SUNXI_PIN(SUNXI_PINCTRL_PIN(H, 28),
                  SUNXI_FUNCTION(0x0, "gpio_in"),
                  SUNXI_FUNCTION(0x1, "gpio_out")),
-       SUNXI_PIN(SUNXI_PINCTRL_PIN_PH29,
+       SUNXI_PIN(SUNXI_PINCTRL_PIN(H, 29),
                  SUNXI_FUNCTION(0x0, "gpio_in"),
                  SUNXI_FUNCTION(0x1, "gpio_out"),
                  SUNXI_FUNCTION(0x2, "nand1")),        /* CE2 */
-       SUNXI_PIN(SUNXI_PINCTRL_PIN_PH30,
+       SUNXI_PIN(SUNXI_PINCTRL_PIN(H, 30),
                  SUNXI_FUNCTION(0x0, "gpio_in"),
                  SUNXI_FUNCTION(0x1, "gpio_out"),
                  SUNXI_FUNCTION(0x2, "nand1")),        /* CE3 */
 };
 
 static const struct sunxi_desc_pin sun6i_a31_r_pins[] = {
-       SUNXI_PIN(SUNXI_PINCTRL_PIN_PL0,
+       SUNXI_PIN(SUNXI_PINCTRL_PIN(L, 0),
                  SUNXI_FUNCTION(0x0, "gpio_in"),
                  SUNXI_FUNCTION(0x1, "gpio_out"),
                  SUNXI_FUNCTION(0x2, "s_twi"),         /* SCK */
                  SUNXI_FUNCTION(0x3, "s_p2wi")),       /* SCK */
-       SUNXI_PIN(SUNXI_PINCTRL_PIN_PL1,
+       SUNXI_PIN(SUNXI_PINCTRL_PIN(L, 1),
                  SUNXI_FUNCTION(0x0, "gpio_in"),
                  SUNXI_FUNCTION(0x1, "gpio_out"),
                  SUNXI_FUNCTION(0x2, "s_twi"),         /* SDA */
                  SUNXI_FUNCTION(0x3, "s_p2wi")),       /* SDA */
-       SUNXI_PIN(SUNXI_PINCTRL_PIN_PL2,
+       SUNXI_PIN(SUNXI_PINCTRL_PIN(L, 2),
                  SUNXI_FUNCTION(0x0, "gpio_in"),
                  SUNXI_FUNCTION(0x1, "gpio_out"),
                  SUNXI_FUNCTION(0x2, "s_uart")),       /* TX */
-       SUNXI_PIN(SUNXI_PINCTRL_PIN_PL3,
+       SUNXI_PIN(SUNXI_PINCTRL_PIN(L, 3),
                  SUNXI_FUNCTION(0x0, "gpio_in"),
                  SUNXI_FUNCTION(0x1, "gpio_out"),
                  SUNXI_FUNCTION(0x2, "s_uart")),       /* RX */
-       SUNXI_PIN(SUNXI_PINCTRL_PIN_PL4,
+       SUNXI_PIN(SUNXI_PINCTRL_PIN(L, 4),
                  SUNXI_FUNCTION(0x0, "gpio_in"),
                  SUNXI_FUNCTION(0x1, "gpio_out"),
                  SUNXI_FUNCTION(0x2, "s_ir")),         /* RX */
-       SUNXI_PIN(SUNXI_PINCTRL_PIN_PL5,
+       SUNXI_PIN(SUNXI_PINCTRL_PIN(L, 5),
                  SUNXI_FUNCTION(0x0, "gpio_in"),
                  SUNXI_FUNCTION(0x1, "gpio_out"),
                  SUNXI_FUNCTION(0x3, "s_jtag")),       /* MS */
-       SUNXI_PIN(SUNXI_PINCTRL_PIN_PL6,
+       SUNXI_PIN(SUNXI_PINCTRL_PIN(L, 6),
                  SUNXI_FUNCTION(0x0, "gpio_in"),
                  SUNXI_FUNCTION(0x1, "gpio_out"),
                  SUNXI_FUNCTION(0x3, "s_jtag")),       /* CK */
-       SUNXI_PIN(SUNXI_PINCTRL_PIN_PL7,
+       SUNXI_PIN(SUNXI_PINCTRL_PIN(L, 7),
                  SUNXI_FUNCTION(0x0, "gpio_in"),
                  SUNXI_FUNCTION(0x1, "gpio_out"),
                  SUNXI_FUNCTION(0x3, "s_jtag")),       /* DO */
-       SUNXI_PIN(SUNXI_PINCTRL_PIN_PL8,
+       SUNXI_PIN(SUNXI_PINCTRL_PIN(L, 8),
                  SUNXI_FUNCTION(0x0, "gpio_in"),
                  SUNXI_FUNCTION(0x1, "gpio_out"),
                  SUNXI_FUNCTION(0x3, "s_jtag")),       /* DI */
        /* Hole */
-       SUNXI_PIN(SUNXI_PINCTRL_PIN_PM0,
+       SUNXI_PIN(SUNXI_PINCTRL_PIN(M, 0),
                  SUNXI_FUNCTION(0x0, "gpio_in"),
                  SUNXI_FUNCTION(0x1, "gpio_out")),
-       SUNXI_PIN(SUNXI_PINCTRL_PIN_PM1,
+       SUNXI_PIN(SUNXI_PINCTRL_PIN(M, 1),
                  SUNXI_FUNCTION(0x0, "gpio_in"),
                  SUNXI_FUNCTION(0x1, "gpio_out")),
-       SUNXI_PIN(SUNXI_PINCTRL_PIN_PM2,
+       SUNXI_PIN(SUNXI_PINCTRL_PIN(M, 2),
                  SUNXI_FUNCTION(0x0, "gpio_in"),
                  SUNXI_FUNCTION(0x1, "gpio_out"),
                  SUNXI_FUNCTION(0x3, "1wire")),
-       SUNXI_PIN(SUNXI_PINCTRL_PIN_PM3,
+       SUNXI_PIN(SUNXI_PINCTRL_PIN(M, 3),
                  SUNXI_FUNCTION(0x0, "gpio_in"),
                  SUNXI_FUNCTION(0x1, "gpio_out")),
-       SUNXI_PIN(SUNXI_PINCTRL_PIN_PM4,
+       SUNXI_PIN(SUNXI_PINCTRL_PIN(M, 4),
                  SUNXI_FUNCTION(0x0, "gpio_in"),
                  SUNXI_FUNCTION(0x1, "gpio_out")),
-       SUNXI_PIN(SUNXI_PINCTRL_PIN_PM5,
+       SUNXI_PIN(SUNXI_PINCTRL_PIN(M, 5),
                  SUNXI_FUNCTION(0x0, "gpio_in"),
                  SUNXI_FUNCTION(0x1, "gpio_out")),
-       SUNXI_PIN(SUNXI_PINCTRL_PIN_PM6,
+       SUNXI_PIN(SUNXI_PINCTRL_PIN(M, 6),
                  SUNXI_FUNCTION(0x0, "gpio_in"),
                  SUNXI_FUNCTION(0x1, "gpio_out")),
-       SUNXI_PIN(SUNXI_PINCTRL_PIN_PM7,
+       SUNXI_PIN(SUNXI_PINCTRL_PIN(M, 7),
                  SUNXI_FUNCTION(0x0, "gpio_in"),
                  SUNXI_FUNCTION(0x1, "gpio_out"),
                  SUNXI_FUNCTION(0x3, "rtc")),          /* CLKO */
 };
 
 static const struct sunxi_desc_pin sun7i_a20_pins[] = {
-       SUNXI_PIN(SUNXI_PINCTRL_PIN_PA0,
+       SUNXI_PIN(SUNXI_PINCTRL_PIN(A, 0),
                  SUNXI_FUNCTION(0x0, "gpio_in"),
                  SUNXI_FUNCTION(0x1, "gpio_out"),
                  SUNXI_FUNCTION(0x2, "emac"),          /* ERXD3 */
                  SUNXI_FUNCTION(0x3, "spi1"),          /* CS0 */
                  SUNXI_FUNCTION(0x4, "uart2"),         /* RTS */
                  SUNXI_FUNCTION(0x5, "gmac")),         /* GRXD3 */
-       SUNXI_PIN(SUNXI_PINCTRL_PIN_PA1,
+       SUNXI_PIN(SUNXI_PINCTRL_PIN(A, 1),
                  SUNXI_FUNCTION(0x0, "gpio_in"),
                  SUNXI_FUNCTION(0x1, "gpio_out"),
                  SUNXI_FUNCTION(0x2, "emac"),          /* ERXD2 */
                  SUNXI_FUNCTION(0x3, "spi1"),          /* CLK */
                  SUNXI_FUNCTION(0x4, "uart2"),         /* CTS */
                  SUNXI_FUNCTION(0x5, "gmac")),         /* GRXD2 */
-       SUNXI_PIN(SUNXI_PINCTRL_PIN_PA2,
+       SUNXI_PIN(SUNXI_PINCTRL_PIN(A, 2),
                  SUNXI_FUNCTION(0x0, "gpio_in"),
                  SUNXI_FUNCTION(0x1, "gpio_out"),
                  SUNXI_FUNCTION(0x2, "emac"),          /* ERXD1 */
                  SUNXI_FUNCTION(0x3, "spi1"),          /* MOSI */
                  SUNXI_FUNCTION(0x4, "uart2"),         /* TX */
                  SUNXI_FUNCTION(0x5, "gmac")),         /* GRXD1 */
-       SUNXI_PIN(SUNXI_PINCTRL_PIN_PA3,
+       SUNXI_PIN(SUNXI_PINCTRL_PIN(A, 3),
                  SUNXI_FUNCTION(0x0, "gpio_in"),
                  SUNXI_FUNCTION(0x1, "gpio_out"),
                  SUNXI_FUNCTION(0x2, "emac"),          /* ERXD0 */
                  SUNXI_FUNCTION(0x3, "spi1"),          /* MISO */
                  SUNXI_FUNCTION(0x4, "uart2"),         /* RX */
                  SUNXI_FUNCTION(0x5, "gmac")),         /* GRXD0 */
-       SUNXI_PIN(SUNXI_PINCTRL_PIN_PA4,
+       SUNXI_PIN(SUNXI_PINCTRL_PIN(A, 4),
                  SUNXI_FUNCTION(0x0, "gpio_in"),
                  SUNXI_FUNCTION(0x1, "gpio_out"),
                  SUNXI_FUNCTION(0x2, "emac"),          /* ETXD3 */
                  SUNXI_FUNCTION(0x3, "spi1"),          /* CS1 */
                  SUNXI_FUNCTION(0x5, "gmac")),         /* GTXD3 */
-       SUNXI_PIN(SUNXI_PINCTRL_PIN_PA5,
+       SUNXI_PIN(SUNXI_PINCTRL_PIN(A, 5),
                  SUNXI_FUNCTION(0x0, "gpio_in"),
                  SUNXI_FUNCTION(0x1, "gpio_out"),
                  SUNXI_FUNCTION(0x2, "emac"),          /* ETXD2 */
                  SUNXI_FUNCTION(0x3, "spi3"),          /* CS0 */
                  SUNXI_FUNCTION(0x5, "gmac")),         /* GTXD2 */
-       SUNXI_PIN(SUNXI_PINCTRL_PIN_PA6,
+       SUNXI_PIN(SUNXI_PINCTRL_PIN(A, 6),
                  SUNXI_FUNCTION(0x0, "gpio_in"),
                  SUNXI_FUNCTION(0x1, "gpio_out"),
                  SUNXI_FUNCTION(0x2, "emac"),          /* ETXD1 */
                  SUNXI_FUNCTION(0x3, "spi3"),          /* CLK */
                  SUNXI_FUNCTION(0x5, "gmac")),         /* GTXD1 */
-       SUNXI_PIN(SUNXI_PINCTRL_PIN_PA7,
+       SUNXI_PIN(SUNXI_PINCTRL_PIN(A, 7),
                  SUNXI_FUNCTION(0x0, "gpio_in"),
                  SUNXI_FUNCTION(0x1, "gpio_out"),
                  SUNXI_FUNCTION(0x2, "emac"),          /* ETXD0 */
                  SUNXI_FUNCTION(0x3, "spi3"),          /* MOSI */
                  SUNXI_FUNCTION(0x5, "gmac")),         /* GTXD0 */
-       SUNXI_PIN(SUNXI_PINCTRL_PIN_PA8,
+       SUNXI_PIN(SUNXI_PINCTRL_PIN(A, 8),
                  SUNXI_FUNCTION(0x0, "gpio_in"),
                  SUNXI_FUNCTION(0x1, "gpio_out"),
                  SUNXI_FUNCTION(0x2, "emac"),          /* ERXCK */
                  SUNXI_FUNCTION(0x3, "spi3"),          /* MISO */
                  SUNXI_FUNCTION(0x5, "gmac")),         /* GRXCK */
-       SUNXI_PIN(SUNXI_PINCTRL_PIN_PA9,
+       SUNXI_PIN(SUNXI_PINCTRL_PIN(A, 9),
                  SUNXI_FUNCTION(0x0, "gpio_in"),
                  SUNXI_FUNCTION(0x1, "gpio_out"),
                  SUNXI_FUNCTION(0x2, "emac"),          /* ERXERR */
                  SUNXI_FUNCTION(0x3, "spi3"),          /* CS1 */
                  SUNXI_FUNCTION(0x5, "gmac"),          /* GNULL / ERXERR */
                  SUNXI_FUNCTION(0x6, "i2s1")),         /* MCLK */
-       SUNXI_PIN(SUNXI_PINCTRL_PIN_PA10,
+       SUNXI_PIN(SUNXI_PINCTRL_PIN(A, 10),
                  SUNXI_FUNCTION(0x0, "gpio_in"),
                  SUNXI_FUNCTION(0x1, "gpio_out"),
                  SUNXI_FUNCTION(0x2, "emac"),          /* ERXDV */
                  SUNXI_FUNCTION(0x4, "uart1"),         /* TX */
                  SUNXI_FUNCTION(0x5, "gmac")),         /* GRXCTL / ERXDV */
-       SUNXI_PIN(SUNXI_PINCTRL_PIN_PA11,
+       SUNXI_PIN(SUNXI_PINCTRL_PIN(A, 11),
                  SUNXI_FUNCTION(0x0, "gpio_in"),
                  SUNXI_FUNCTION(0x1, "gpio_out"),
                  SUNXI_FUNCTION(0x2, "emac"),          /* EMDC */
                  SUNXI_FUNCTION(0x4, "uart1"),         /* RX */
                  SUNXI_FUNCTION(0x5, "gmac")),         /* EMDC */
-       SUNXI_PIN(SUNXI_PINCTRL_PIN_PA12,
+       SUNXI_PIN(SUNXI_PINCTRL_PIN(A, 12),
                  SUNXI_FUNCTION(0x0, "gpio_in"),
                  SUNXI_FUNCTION(0x1, "gpio_out"),
                  SUNXI_FUNCTION(0x2, "emac"),          /* EMDIO */
                  SUNXI_FUNCTION(0x3, "uart6"),         /* TX */
                  SUNXI_FUNCTION(0x4, "uart1"),         /* RTS */
                  SUNXI_FUNCTION(0x5, "gmac")),         /* EMDIO */
-       SUNXI_PIN(SUNXI_PINCTRL_PIN_PA13,
+       SUNXI_PIN(SUNXI_PINCTRL_PIN(A, 13),
                  SUNXI_FUNCTION(0x0, "gpio_in"),
                  SUNXI_FUNCTION(0x1, "gpio_out"),
                  SUNXI_FUNCTION(0x2, "emac"),          /* ETXEN */
                  SUNXI_FUNCTION(0x3, "uart6"),         /* RX */
                  SUNXI_FUNCTION(0x4, "uart1"),         /* CTS */
                  SUNXI_FUNCTION(0x5, "gmac")),         /* GTXCTL / ETXEN */
-       SUNXI_PIN(SUNXI_PINCTRL_PIN_PA14,
+       SUNXI_PIN(SUNXI_PINCTRL_PIN(A, 14),
                  SUNXI_FUNCTION(0x0, "gpio_in"),
                  SUNXI_FUNCTION(0x1, "gpio_out"),
                  SUNXI_FUNCTION(0x2, "emac"),          /* ETXCK */
@@ -2988,7 +2988,7 @@ static const struct sunxi_desc_pin sun7i_a20_pins[] = {
                  SUNXI_FUNCTION(0x4, "uart1"),         /* DTR */
                  SUNXI_FUNCTION(0x5, "gmac"),          /* GNULL / ETXCK */
                  SUNXI_FUNCTION(0x6, "i2s1")),         /* BCLK */
-       SUNXI_PIN(SUNXI_PINCTRL_PIN_PA15,
+       SUNXI_PIN(SUNXI_PINCTRL_PIN(A, 15),
                  SUNXI_FUNCTION(0x0, "gpio_in"),
                  SUNXI_FUNCTION(0x1, "gpio_out"),
                  SUNXI_FUNCTION(0x2, "emac"),          /* ECRS */
@@ -2996,7 +2996,7 @@ static const struct sunxi_desc_pin sun7i_a20_pins[] = {
                  SUNXI_FUNCTION(0x4, "uart1"),         /* DSR */
                  SUNXI_FUNCTION(0x5, "gmac"),          /* GTXCK / ECRS */
                  SUNXI_FUNCTION(0x6, "i2s1")),         /* LRCK */
-       SUNXI_PIN(SUNXI_PINCTRL_PIN_PA16,
+       SUNXI_PIN(SUNXI_PINCTRL_PIN(A, 16),
                  SUNXI_FUNCTION(0x0, "gpio_in"),
                  SUNXI_FUNCTION(0x1, "gpio_out"),
                  SUNXI_FUNCTION(0x2, "emac"),          /* ECOL */
@@ -3004,7 +3004,7 @@ static const struct sunxi_desc_pin sun7i_a20_pins[] = {
                  SUNXI_FUNCTION(0x4, "uart1"),         /* DCD */
                  SUNXI_FUNCTION(0x5, "gmac"),          /* GCLKIN / ECOL */
                  SUNXI_FUNCTION(0x6, "i2s1")),         /* DO */
-       SUNXI_PIN(SUNXI_PINCTRL_PIN_PA17,
+       SUNXI_PIN(SUNXI_PINCTRL_PIN(A, 17),
                  SUNXI_FUNCTION(0x0, "gpio_in"),
                  SUNXI_FUNCTION(0x1, "gpio_out"),
                  SUNXI_FUNCTION(0x2, "emac"),          /* ETXERR */
@@ -3013,543 +3013,543 @@ static const struct sunxi_desc_pin sun7i_a20_pins[] = {
                  SUNXI_FUNCTION(0x5, "gmac"),          /* GNULL / ETXERR */
                  SUNXI_FUNCTION(0x6, "i2s1")),         /* LRCK */
        /* Hole */
-       SUNXI_PIN(SUNXI_PINCTRL_PIN_PB0,
+       SUNXI_PIN(SUNXI_PINCTRL_PIN(B, 0),
                  SUNXI_FUNCTION(0x0, "gpio_in"),
                  SUNXI_FUNCTION(0x1, "gpio_out"),
                  SUNXI_FUNCTION(0x2, "i2c0")),         /* SCK */
-       SUNXI_PIN(SUNXI_PINCTRL_PIN_PB1,
+       SUNXI_PIN(SUNXI_PINCTRL_PIN(B, 1),
                  SUNXI_FUNCTION(0x0, "gpio_in"),
                  SUNXI_FUNCTION(0x1, "gpio_out"),
                  SUNXI_FUNCTION(0x2, "i2c0")),         /* SDA */
-       SUNXI_PIN(SUNXI_PINCTRL_PIN_PB2,
+       SUNXI_PIN(SUNXI_PINCTRL_PIN(B, 2),
                  SUNXI_FUNCTION(0x0, "gpio_in"),
                  SUNXI_FUNCTION(0x1, "gpio_out"),
                  SUNXI_FUNCTION(0x2, "pwm")),          /* PWM0 */
-       SUNXI_PIN(SUNXI_PINCTRL_PIN_PB3,
+       SUNXI_PIN(SUNXI_PINCTRL_PIN(B, 3),
                  SUNXI_FUNCTION(0x0, "gpio_in"),
                  SUNXI_FUNCTION(0x1, "gpio_out"),
                  SUNXI_FUNCTION(0x2, "ir0"),           /* TX */
                  SUNXI_FUNCTION(0x4, "spdif")),        /* MCLK */
-       SUNXI_PIN(SUNXI_PINCTRL_PIN_PB4,
+       SUNXI_PIN(SUNXI_PINCTRL_PIN(B, 4),
                  SUNXI_FUNCTION(0x0, "gpio_in"),
                  SUNXI_FUNCTION(0x1, "gpio_out"),
                  SUNXI_FUNCTION(0x2, "ir0")),          /* RX */
-       SUNXI_PIN(SUNXI_PINCTRL_PIN_PB5,
+       SUNXI_PIN(SUNXI_PINCTRL_PIN(B, 5),
                  SUNXI_FUNCTION(0x0, "gpio_in"),
                  SUNXI_FUNCTION(0x1, "gpio_out"),
                  SUNXI_FUNCTION(0x2, "i2s0"),          /* MCLK */
                  SUNXI_FUNCTION(0x3, "ac97")),         /* MCLK */
-       SUNXI_PIN(SUNXI_PINCTRL_PIN_PB6,
+       SUNXI_PIN(SUNXI_PINCTRL_PIN(B, 6),
                  SUNXI_FUNCTION(0x0, "gpio_in"),
                  SUNXI_FUNCTION(0x1, "gpio_out"),
                  SUNXI_FUNCTION(0x2, "i2s0"),          /* BCLK */
                  SUNXI_FUNCTION(0x3, "ac97")),         /* BCLK */
-       SUNXI_PIN(SUNXI_PINCTRL_PIN_PB7,
+       SUNXI_PIN(SUNXI_PINCTRL_PIN(B, 7),
                  SUNXI_FUNCTION(0x0, "gpio_in"),
                  SUNXI_FUNCTION(0x1, "gpio_out"),
                  SUNXI_FUNCTION(0x2, "i2s0"),          /* LRCK */
                  SUNXI_FUNCTION(0x3, "ac97")),         /* SYNC */
-       SUNXI_PIN(SUNXI_PINCTRL_PIN_PB8,
+       SUNXI_PIN(SUNXI_PINCTRL_PIN(B, 8),
                  SUNXI_FUNCTION(0x0, "gpio_in"),
                  SUNXI_FUNCTION(0x1, "gpio_out"),
                  SUNXI_FUNCTION(0x2, "i2s0"),          /* DO0 */
                  SUNXI_FUNCTION(0x3, "ac97")),         /* DO */
-       SUNXI_PIN(SUNXI_PINCTRL_PIN_PB9,
+       SUNXI_PIN(SUNXI_PINCTRL_PIN(B, 9),
                  SUNXI_FUNCTION(0x0, "gpio_in"),
                  SUNXI_FUNCTION(0x1, "gpio_out"),
                  SUNXI_FUNCTION(0x2, "i2s0")),         /* DO1 */
-       SUNXI_PIN(SUNXI_PINCTRL_PIN_PB10,
+       SUNXI_PIN(SUNXI_PINCTRL_PIN(B, 10),
                  SUNXI_FUNCTION(0x0, "gpio_in"),
                  SUNXI_FUNCTION(0x1, "gpio_out"),
                  SUNXI_FUNCTION(0x2, "i2s0")),         /* DO2 */
-       SUNXI_PIN(SUNXI_PINCTRL_PIN_PB11,
+       SUNXI_PIN(SUNXI_PINCTRL_PIN(B, 11),
                  SUNXI_FUNCTION(0x0, "gpio_in"),
                  SUNXI_FUNCTION(0x1, "gpio_out"),
                  SUNXI_FUNCTION(0x2, "i2s0")),         /* DO3 */
-       SUNXI_PIN(SUNXI_PINCTRL_PIN_PB12,
+       SUNXI_PIN(SUNXI_PINCTRL_PIN(B, 12),
                  SUNXI_FUNCTION(0x0, "gpio_in"),
                  SUNXI_FUNCTION(0x1, "gpio_out"),
                  SUNXI_FUNCTION(0x2, "i2s0"),          /* DI */
                  SUNXI_FUNCTION(0x3, "ac97"),          /* DI */
                  SUNXI_FUNCTION(0x4, "spdif")),        /* DI */
-       SUNXI_PIN(SUNXI_PINCTRL_PIN_PB13,
+       SUNXI_PIN(SUNXI_PINCTRL_PIN(B, 13),
                  SUNXI_FUNCTION(0x0, "gpio_in"),
                  SUNXI_FUNCTION(0x1, "gpio_out"),
                  SUNXI_FUNCTION(0x2, "spi2"),          /* CS1 */
                  SUNXI_FUNCTION(0x4, "spdif")),        /* DO */
-       SUNXI_PIN(SUNXI_PINCTRL_PIN_PB14,
+       SUNXI_PIN(SUNXI_PINCTRL_PIN(B, 14),
                  SUNXI_FUNCTION(0x0, "gpio_in"),
                  SUNXI_FUNCTION(0x1, "gpio_out"),
                  SUNXI_FUNCTION(0x2, "spi2"),          /* CS0 */
                  SUNXI_FUNCTION(0x3, "jtag")),         /* MS0 */
-       SUNXI_PIN(SUNXI_PINCTRL_PIN_PB15,
+       SUNXI_PIN(SUNXI_PINCTRL_PIN(B, 15),
                  SUNXI_FUNCTION(0x0, "gpio_in"),
                  SUNXI_FUNCTION(0x1, "gpio_out"),
                  SUNXI_FUNCTION(0x2, "spi2"),          /* CLK */
                  SUNXI_FUNCTION(0x3, "jtag")),         /* CK0 */
-       SUNXI_PIN(SUNXI_PINCTRL_PIN_PB16,
+       SUNXI_PIN(SUNXI_PINCTRL_PIN(B, 16),
                  SUNXI_FUNCTION(0x0, "gpio_in"),
                  SUNXI_FUNCTION(0x1, "gpio_out"),
                  SUNXI_FUNCTION(0x2, "spi2"),          /* MOSI */
                  SUNXI_FUNCTION(0x3, "jtag")),         /* DO0 */
-       SUNXI_PIN(SUNXI_PINCTRL_PIN_PB17,
+       SUNXI_PIN(SUNXI_PINCTRL_PIN(B, 17),
                  SUNXI_FUNCTION(0x0, "gpio_in"),
                  SUNXI_FUNCTION(0x1, "gpio_out"),
                  SUNXI_FUNCTION(0x2, "spi2"),          /* MISO */
                  SUNXI_FUNCTION(0x3, "jtag")),         /* DI0 */
-       SUNXI_PIN(SUNXI_PINCTRL_PIN_PB18,
+       SUNXI_PIN(SUNXI_PINCTRL_PIN(B, 18),
                  SUNXI_FUNCTION(0x0, "gpio_in"),
                  SUNXI_FUNCTION(0x1, "gpio_out"),
                  SUNXI_FUNCTION(0x2, "i2c1")),         /* SCK */
-       SUNXI_PIN(SUNXI_PINCTRL_PIN_PB19,
+       SUNXI_PIN(SUNXI_PINCTRL_PIN(B, 19),
                  SUNXI_FUNCTION(0x0, "gpio_in"),
                  SUNXI_FUNCTION(0x1, "gpio_out"),
                  SUNXI_FUNCTION(0x2, "i2c1")),         /* SDA */
-       SUNXI_PIN(SUNXI_PINCTRL_PIN_PB20,
+       SUNXI_PIN(SUNXI_PINCTRL_PIN(B, 20),
                  SUNXI_FUNCTION(0x0, "gpio_in"),
                  SUNXI_FUNCTION(0x1, "gpio_out"),
                  SUNXI_FUNCTION(0x2, "i2c2")),         /* SCK */
-       SUNXI_PIN(SUNXI_PINCTRL_PIN_PB21,
+       SUNXI_PIN(SUNXI_PINCTRL_PIN(B, 21),
                  SUNXI_FUNCTION(0x0, "gpio_in"),
                  SUNXI_FUNCTION(0x1, "gpio_out"),
                  SUNXI_FUNCTION(0x2, "i2c2")),         /* SDA */
-       SUNXI_PIN(SUNXI_PINCTRL_PIN_PB22,
+       SUNXI_PIN(SUNXI_PINCTRL_PIN(B, 22),
                  SUNXI_FUNCTION(0x0, "gpio_in"),
                  SUNXI_FUNCTION(0x1, "gpio_out"),
                  SUNXI_FUNCTION(0x2, "uart0"),         /* TX */
                  SUNXI_FUNCTION(0x3, "ir1")),          /* TX */
-       SUNXI_PIN(SUNXI_PINCTRL_PIN_PB23,
+       SUNXI_PIN(SUNXI_PINCTRL_PIN(B, 23),
                  SUNXI_FUNCTION(0x0, "gpio_in"),
                  SUNXI_FUNCTION(0x1, "gpio_out"),
                  SUNXI_FUNCTION(0x2, "uart0"),         /* RX */
                  SUNXI_FUNCTION(0x3, "ir1")),          /* RX */
        /* Hole */
-       SUNXI_PIN(SUNXI_PINCTRL_PIN_PC0,
+       SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 0),
                  SUNXI_FUNCTION(0x0, "gpio_in"),
                  SUNXI_FUNCTION(0x1, "gpio_out"),
                  SUNXI_FUNCTION(0x2, "nand0"),         /* NWE */
                  SUNXI_FUNCTION(0x3, "spi0")),         /* MOSI */
-       SUNXI_PIN(SUNXI_PINCTRL_PIN_PC1,
+       SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 1),
                  SUNXI_FUNCTION(0x0, "gpio_in"),
                  SUNXI_FUNCTION(0x1, "gpio_out"),
                  SUNXI_FUNCTION(0x2, "nand0"),         /* NALE */
                  SUNXI_FUNCTION(0x3, "spi0")),         /* MISO */
-       SUNXI_PIN(SUNXI_PINCTRL_PIN_PC2,
+       SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 2),
                  SUNXI_FUNCTION(0x0, "gpio_in"),
                  SUNXI_FUNCTION(0x1, "gpio_out"),
                  SUNXI_FUNCTION(0x2, "nand0"),         /* NCLE */
                  SUNXI_FUNCTION(0x3, "spi0")),         /* SCK */
-       SUNXI_PIN(SUNXI_PINCTRL_PIN_PC3,
+       SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 3),
                  SUNXI_FUNCTION(0x0, "gpio_in"),
                  SUNXI_FUNCTION(0x1, "gpio_out"),
                  SUNXI_FUNCTION(0x2, "nand0")),        /* NCE1 */
-       SUNXI_PIN(SUNXI_PINCTRL_PIN_PC4,
+       SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 4),
                  SUNXI_FUNCTION(0x0, "gpio_in"),
                  SUNXI_FUNCTION(0x1, "gpio_out"),
                  SUNXI_FUNCTION(0x2, "nand0")),        /* NCE0 */
-       SUNXI_PIN(SUNXI_PINCTRL_PIN_PC5,
+       SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 5),
                  SUNXI_FUNCTION(0x0, "gpio_in"),
                  SUNXI_FUNCTION(0x1, "gpio_out"),
                  SUNXI_FUNCTION(0x2, "nand0")),        /* NRE# */
-       SUNXI_PIN(SUNXI_PINCTRL_PIN_PC6,
+       SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 6),
                  SUNXI_FUNCTION(0x0, "gpio_in"),
                  SUNXI_FUNCTION(0x1, "gpio_out"),
                  SUNXI_FUNCTION(0x2, "nand0"),         /* NRB0 */
                  SUNXI_FUNCTION(0x3, "mmc2")),         /* CMD */
-       SUNXI_PIN(SUNXI_PINCTRL_PIN_PC7,
+       SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 7),
                  SUNXI_FUNCTION(0x0, "gpio_in"),
                  SUNXI_FUNCTION(0x1, "gpio_out"),
                  SUNXI_FUNCTION(0x2, "nand0"),         /* NRB1 */
                  SUNXI_FUNCTION(0x3, "mmc2")),         /* CLK */
-       SUNXI_PIN(SUNXI_PINCTRL_PIN_PC8,
+       SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 8),
                  SUNXI_FUNCTION(0x0, "gpio_in"),
                  SUNXI_FUNCTION(0x1, "gpio_out"),
                  SUNXI_FUNCTION(0x2, "nand0"),         /* NDQ0 */
                  SUNXI_FUNCTION(0x3, "mmc2")),         /* D0 */
-       SUNXI_PIN(SUNXI_PINCTRL_PIN_PC9,
+       SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 9),
                  SUNXI_FUNCTION(0x0, "gpio_in"),
                  SUNXI_FUNCTION(0x1, "gpio_out"),
                  SUNXI_FUNCTION(0x2, "nand0"),         /* NDQ1 */
                  SUNXI_FUNCTION(0x3, "mmc2")),         /* D1 */
-       SUNXI_PIN(SUNXI_PINCTRL_PIN_PC10,
+       SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 10),
                  SUNXI_FUNCTION(0x0, "gpio_in"),
                  SUNXI_FUNCTION(0x1, "gpio_out"),
                  SUNXI_FUNCTION(0x2, "nand0"),         /* NDQ2 */
                  SUNXI_FUNCTION(0x3, "mmc2")),         /* D2 */
-       SUNXI_PIN(SUNXI_PINCTRL_PIN_PC11,
+       SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 11),
                  SUNXI_FUNCTION(0x0, "gpio_in"),
                  SUNXI_FUNCTION(0x1, "gpio_out"),
                  SUNXI_FUNCTION(0x2, "nand0"),         /* NDQ3 */
                  SUNXI_FUNCTION(0x3, "mmc2")),         /* D3 */
-       SUNXI_PIN(SUNXI_PINCTRL_PIN_PC12,
+       SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 12),
                  SUNXI_FUNCTION(0x0, "gpio_in"),
                  SUNXI_FUNCTION(0x1, "gpio_out"),
                  SUNXI_FUNCTION(0x2, "nand0")),        /* NDQ4 */
-       SUNXI_PIN(SUNXI_PINCTRL_PIN_PC13,
+       SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 13),
                  SUNXI_FUNCTION(0x0, "gpio_in"),
                  SUNXI_FUNCTION(0x1, "gpio_out"),
                  SUNXI_FUNCTION(0x2, "nand0")),        /* NDQ5 */
-       SUNXI_PIN(SUNXI_PINCTRL_PIN_PC14,
+       SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 14),
                  SUNXI_FUNCTION(0x0, "gpio_in"),
                  SUNXI_FUNCTION(0x1, "gpio_out"),
                  SUNXI_FUNCTION(0x2, "nand0")),        /* NDQ6 */
-       SUNXI_PIN(SUNXI_PINCTRL_PIN_PC15,
+       SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 15),
                  SUNXI_FUNCTION(0x0, "gpio_in"),
                  SUNXI_FUNCTION(0x1, "gpio_out"),
                  SUNXI_FUNCTION(0x2, "nand0")),        /* NDQ7 */
-       SUNXI_PIN(SUNXI_PINCTRL_PIN_PC16,
+       SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 16),
                  SUNXI_FUNCTION(0x0, "gpio_in"),
                  SUNXI_FUNCTION(0x1, "gpio_out"),
                  SUNXI_FUNCTION(0x2, "nand0")),        /* NWP */
-       SUNXI_PIN(SUNXI_PINCTRL_PIN_PC17,
+       SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 17),
                  SUNXI_FUNCTION(0x0, "gpio_in"),
                  SUNXI_FUNCTION(0x1, "gpio_out"),
                  SUNXI_FUNCTION(0x2, "nand0")),        /* NCE2 */
-       SUNXI_PIN(SUNXI_PINCTRL_PIN_PC18,
+       SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 18),
                  SUNXI_FUNCTION(0x0, "gpio_in"),
                  SUNXI_FUNCTION(0x1, "gpio_out"),
                  SUNXI_FUNCTION(0x2, "nand0")),        /* NCE3 */
-       SUNXI_PIN(SUNXI_PINCTRL_PIN_PC19,
+       SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 19),
                  SUNXI_FUNCTION(0x0, "gpio_in"),
                  SUNXI_FUNCTION(0x1, "gpio_out"),
                  SUNXI_FUNCTION(0x2, "nand0"),         /* NCE4 */
                  SUNXI_FUNCTION(0x3, "spi2"),          /* CS0 */
                  SUNXI_FUNCTION_IRQ(0x6, 12)),         /* EINT12 */
-       SUNXI_PIN(SUNXI_PINCTRL_PIN_PC20,
+       SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 20),
                  SUNXI_FUNCTION(0x0, "gpio_in"),
                  SUNXI_FUNCTION(0x1, "gpio_out"),
                  SUNXI_FUNCTION(0x2, "nand0"),         /* NCE5 */
                  SUNXI_FUNCTION(0x3, "spi2"),          /* CLK */
                  SUNXI_FUNCTION_IRQ(0x6, 13)),         /* EINT13 */
-       SUNXI_PIN(SUNXI_PINCTRL_PIN_PC21,
+       SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 21),
                  SUNXI_FUNCTION(0x0, "gpio_in"),
                  SUNXI_FUNCTION(0x1, "gpio_out"),
                  SUNXI_FUNCTION(0x2, "nand0"),         /* NCE6 */
                  SUNXI_FUNCTION(0x3, "spi2"),          /* MOSI */
                  SUNXI_FUNCTION_IRQ(0x6, 14)),         /* EINT14 */
-       SUNXI_PIN(SUNXI_PINCTRL_PIN_PC22,
+       SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 22),
                  SUNXI_FUNCTION(0x0, "gpio_in"),
                  SUNXI_FUNCTION(0x1, "gpio_out"),
                  SUNXI_FUNCTION(0x2, "nand0"),         /* NCE7 */
                  SUNXI_FUNCTION(0x3, "spi2"),          /* MISO */
                  SUNXI_FUNCTION_IRQ(0x6, 15)),         /* EINT15 */
-       SUNXI_PIN(SUNXI_PINCTRL_PIN_PC23,
+       SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 23),
                  SUNXI_FUNCTION(0x0, "gpio_in"),
                  SUNXI_FUNCTION(0x1, "gpio_out"),
                  SUNXI_FUNCTION(0x3, "spi0")),         /* CS0 */
-       SUNXI_PIN(SUNXI_PINCTRL_PIN_PC24,
+       SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 24),
                  SUNXI_FUNCTION(0x0, "gpio_in"),
                  SUNXI_FUNCTION(0x1, "gpio_out"),
                  SUNXI_FUNCTION(0x2, "nand0")),        /* NDQS */
        /* Hole */
-       SUNXI_PIN(SUNXI_PINCTRL_PIN_PD0,
+       SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 0),
                  SUNXI_FUNCTION(0x0, "gpio_in"),
                  SUNXI_FUNCTION(0x1, "gpio_out"),
                  SUNXI_FUNCTION(0x2, "lcd0"),          /* D0 */
                  SUNXI_FUNCTION(0x3, "lvds0")),        /* VP0 */
-       SUNXI_PIN(SUNXI_PINCTRL_PIN_PD1,
+       SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 1),
                  SUNXI_FUNCTION(0x0, "gpio_in"),
                  SUNXI_FUNCTION(0x1, "gpio_out"),
                  SUNXI_FUNCTION(0x2, "lcd0"),          /* D1 */
                  SUNXI_FUNCTION(0x3, "lvds0")),        /* VN0 */
-       SUNXI_PIN(SUNXI_PINCTRL_PIN_PD2,
+       SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 2),
                  SUNXI_FUNCTION(0x0, "gpio_in"),
                  SUNXI_FUNCTION(0x1, "gpio_out"),
                  SUNXI_FUNCTION(0x2, "lcd0"),          /* D2 */
                  SUNXI_FUNCTION(0x3, "lvds0")),        /* VP1 */
-       SUNXI_PIN(SUNXI_PINCTRL_PIN_PD3,
+       SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 3),
                  SUNXI_FUNCTION(0x0, "gpio_in"),
                  SUNXI_FUNCTION(0x1, "gpio_out"),
                  SUNXI_FUNCTION(0x2, "lcd0"),          /* D3 */
                  SUNXI_FUNCTION(0x3, "lvds0")),        /* VN1 */
-       SUNXI_PIN(SUNXI_PINCTRL_PIN_PD4,
+       SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 4),
                  SUNXI_FUNCTION(0x0, "gpio_in"),
                  SUNXI_FUNCTION(0x1, "gpio_out"),
                  SUNXI_FUNCTION(0x2, "lcd0"),          /* D4 */
                  SUNXI_FUNCTION(0x3, "lvds0")),        /* VP2 */
-       SUNXI_PIN(SUNXI_PINCTRL_PIN_PD5,
+       SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 5),
                  SUNXI_FUNCTION(0x0, "gpio_in"),
                  SUNXI_FUNCTION(0x1, "gpio_out"),
                  SUNXI_FUNCTION(0x2, "lcd0"),          /* D5 */
                  SUNXI_FUNCTION(0x3, "lvds0")),        /* VN2 */
-       SUNXI_PIN(SUNXI_PINCTRL_PIN_PD6,
+       SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 6),
                  SUNXI_FUNCTION(0x0, "gpio_in"),
                  SUNXI_FUNCTION(0x1, "gpio_out"),
                  SUNXI_FUNCTION(0x2, "lcd0"),          /* D6 */
                  SUNXI_FUNCTION(0x3, "lvds0")),        /* VPC */
-       SUNXI_PIN(SUNXI_PINCTRL_PIN_PD7,
+       SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 7),
                  SUNXI_FUNCTION(0x0, "gpio_in"),
                  SUNXI_FUNCTION(0x1, "gpio_out"),
                  SUNXI_FUNCTION(0x2, "lcd0"),          /* D7 */
                  SUNXI_FUNCTION(0x3, "lvds0")),        /* VNC */
-       SUNXI_PIN(SUNXI_PINCTRL_PIN_PD8,
+       SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 8),
                  SUNXI_FUNCTION(0x0, "gpio_in"),
                  SUNXI_FUNCTION(0x1, "gpio_out"),
                  SUNXI_FUNCTION(0x2, "lcd0"),          /* D8 */
                  SUNXI_FUNCTION(0x3, "lvds0")),        /* VP3 */
-       SUNXI_PIN(SUNXI_PINCTRL_PIN_PD9,
+       SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 9),
                  SUNXI_FUNCTION(0x0, "gpio_in"),
                  SUNXI_FUNCTION(0x1, "gpio_out"),
                  SUNXI_FUNCTION(0x2, "lcd0"),          /* D9 */
                  SUNXI_FUNCTION(0x3, "lvds0")),        /* VM3 */
-       SUNXI_PIN(SUNXI_PINCTRL_PIN_PD10,
+       SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 10),
                  SUNXI_FUNCTION(0x0, "gpio_in"),
                  SUNXI_FUNCTION(0x1, "gpio_out"),
                  SUNXI_FUNCTION(0x2, "lcd0"),          /* D10 */
                  SUNXI_FUNCTION(0x3, "lvds1")),        /* VP0 */
-       SUNXI_PIN(SUNXI_PINCTRL_PIN_PD11,
+       SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 11),
                  SUNXI_FUNCTION(0x0, "gpio_in"),
                  SUNXI_FUNCTION(0x1, "gpio_out"),
                  SUNXI_FUNCTION(0x2, "lcd0"),          /* D11 */
                  SUNXI_FUNCTION(0x3, "lvds1")),        /* VN0 */
-       SUNXI_PIN(SUNXI_PINCTRL_PIN_PD12,
+       SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 12),
                  SUNXI_FUNCTION(0x0, "gpio_in"),
                  SUNXI_FUNCTION(0x1, "gpio_out"),
                  SUNXI_FUNCTION(0x2, "lcd0"),          /* D12 */
                  SUNXI_FUNCTION(0x3, "lvds1")),        /* VP1 */
-       SUNXI_PIN(SUNXI_PINCTRL_PIN_PD13,
+       SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 13),
                  SUNXI_FUNCTION(0x0, "gpio_in"),
                  SUNXI_FUNCTION(0x1, "gpio_out"),
                  SUNXI_FUNCTION(0x2, "lcd0"),          /* D13 */
                  SUNXI_FUNCTION(0x3, "lvds1")),        /* VN1 */
-       SUNXI_PIN(SUNXI_PINCTRL_PIN_PD14,
+       SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 14),
                  SUNXI_FUNCTION(0x0, "gpio_in"),
                  SUNXI_FUNCTION(0x1, "gpio_out"),
                  SUNXI_FUNCTION(0x2, "lcd0"),          /* D14 */
                  SUNXI_FUNCTION(0x3, "lvds1")),        /* VP2 */
-       SUNXI_PIN(SUNXI_PINCTRL_PIN_PD15,
+       SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 15),
                  SUNXI_FUNCTION(0x0, "gpio_in"),
                  SUNXI_FUNCTION(0x1, "gpio_out"),
                  SUNXI_FUNCTION(0x2, "lcd0"),          /* D15 */
                  SUNXI_FUNCTION(0x3, "lvds1")),        /* VN2 */
-       SUNXI_PIN(SUNXI_PINCTRL_PIN_PD16,
+       SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 16),
                  SUNXI_FUNCTION(0x0, "gpio_in"),
                  SUNXI_FUNCTION(0x1, "gpio_out"),
                  SUNXI_FUNCTION(0x2, "lcd0"),          /* D16 */
                  SUNXI_FUNCTION(0x3, "lvds1")),        /* VPC */
-       SUNXI_PIN(SUNXI_PINCTRL_PIN_PD17,
+       SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 17),
                  SUNXI_FUNCTION(0x0, "gpio_in"),
                  SUNXI_FUNCTION(0x1, "gpio_out"),
                  SUNXI_FUNCTION(0x2, "lcd0"),          /* D17 */
                  SUNXI_FUNCTION(0x3, "lvds1")),        /* VNC */
-       SUNXI_PIN(SUNXI_PINCTRL_PIN_PD18,
+       SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 18),
                  SUNXI_FUNCTION(0x0, "gpio_in"),
                  SUNXI_FUNCTION(0x1, "gpio_out"),
                  SUNXI_FUNCTION(0x2, "lcd0"),          /* D18 */
                  SUNXI_FUNCTION(0x3, "lvds1")),        /* VP3 */
-       SUNXI_PIN(SUNXI_PINCTRL_PIN_PD19,
+       SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 19),
                  SUNXI_FUNCTION(0x0, "gpio_in"),
                  SUNXI_FUNCTION(0x1, "gpio_out"),
                  SUNXI_FUNCTION(0x2, "lcd0"),          /* D19 */
                  SUNXI_FUNCTION(0x3, "lvds1")),        /* VN3 */
-       SUNXI_PIN(SUNXI_PINCTRL_PIN_PD20,
+       SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 20),
                  SUNXI_FUNCTION(0x0, "gpio_in"),
                  SUNXI_FUNCTION(0x1, "gpio_out"),
                  SUNXI_FUNCTION(0x2, "lcd0"),          /* D20 */
                  SUNXI_FUNCTION(0x3, "csi1")),         /* MCLK */
-       SUNXI_PIN(SUNXI_PINCTRL_PIN_PD21,
+       SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 21),
                  SUNXI_FUNCTION(0x0, "gpio_in"),
                  SUNXI_FUNCTION(0x1, "gpio_out"),
                  SUNXI_FUNCTION(0x2, "lcd0"),          /* D21 */
                  SUNXI_FUNCTION(0x3, "sim")),          /* VPPEN */
-       SUNXI_PIN(SUNXI_PINCTRL_PIN_PD22,
+       SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 22),
                  SUNXI_FUNCTION(0x0, "gpio_in"),
                  SUNXI_FUNCTION(0x1, "gpio_out"),
                  SUNXI_FUNCTION(0x2, "lcd0"),          /* D22 */
                  SUNXI_FUNCTION(0x3, "sim")),          /* VPPPP */
-       SUNXI_PIN(SUNXI_PINCTRL_PIN_PD23,
+       SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 23),
                  SUNXI_FUNCTION(0x0, "gpio_in"),
                  SUNXI_FUNCTION(0x1, "gpio_out"),
                  SUNXI_FUNCTION(0x2, "lcd0"),          /* D23 */
                  SUNXI_FUNCTION(0x3, "sim")),          /* DET */
-       SUNXI_PIN(SUNXI_PINCTRL_PIN_PD24,
+       SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 24),
                  SUNXI_FUNCTION(0x0, "gpio_in"),
                  SUNXI_FUNCTION(0x1, "gpio_out"),
                  SUNXI_FUNCTION(0x2, "lcd0"),          /* CLK */
                  SUNXI_FUNCTION(0x3, "sim")),          /* VCCEN */
-       SUNXI_PIN(SUNXI_PINCTRL_PIN_PD25,
+       SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 25),
                  SUNXI_FUNCTION(0x0, "gpio_in"),
                  SUNXI_FUNCTION(0x1, "gpio_out"),
                  SUNXI_FUNCTION(0x2, "lcd0"),          /* DE */
                  SUNXI_FUNCTION(0x3, "sim")),          /* RST */
-       SUNXI_PIN(SUNXI_PINCTRL_PIN_PD26,
+       SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 26),
                  SUNXI_FUNCTION(0x0, "gpio_in"),
                  SUNXI_FUNCTION(0x1, "gpio_out"),
                  SUNXI_FUNCTION(0x2, "lcd0"),          /* HSYNC */
                  SUNXI_FUNCTION(0x3, "sim")),          /* SCK */
-       SUNXI_PIN(SUNXI_PINCTRL_PIN_PD27,
+       SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 27),
                  SUNXI_FUNCTION(0x0, "gpio_in"),
                  SUNXI_FUNCTION(0x1, "gpio_out"),
                  SUNXI_FUNCTION(0x2, "lcd0"),          /* VSYNC */
                  SUNXI_FUNCTION(0x3, "sim")),          /* SDA */
        /* Hole */
-       SUNXI_PIN(SUNXI_PINCTRL_PIN_PE0,
+       SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 0),
                  SUNXI_FUNCTION(0x0, "gpio_in"),
                  SUNXI_FUNCTION(0x1, "gpio_out"),
                  SUNXI_FUNCTION(0x2, "ts0"),           /* CLK */
                  SUNXI_FUNCTION(0x3, "csi0")),         /* PCK */
-       SUNXI_PIN(SUNXI_PINCTRL_PIN_PE1,
+       SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 1),
                  SUNXI_FUNCTION(0x0, "gpio_in"),
                  SUNXI_FUNCTION(0x1, "gpio_out"),
                  SUNXI_FUNCTION(0x2, "ts0"),           /* ERR */
                  SUNXI_FUNCTION(0x3, "csi0")),         /* CK */
-       SUNXI_PIN(SUNXI_PINCTRL_PIN_PE2,
+       SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 2),
                  SUNXI_FUNCTION(0x0, "gpio_in"),
                  SUNXI_FUNCTION(0x1, "gpio_out"),
                  SUNXI_FUNCTION(0x2, "ts0"),           /* SYNC */
                  SUNXI_FUNCTION(0x3, "csi0")),         /* HSYNC */
-       SUNXI_PIN(SUNXI_PINCTRL_PIN_PE3,
+       SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 3),
                  SUNXI_FUNCTION(0x0, "gpio_in"),
                  SUNXI_FUNCTION(0x1, "gpio_out"),
                  SUNXI_FUNCTION(0x2, "ts0"),           /* DVLD */
                  SUNXI_FUNCTION(0x3, "csi0")),         /* VSYNC */
-       SUNXI_PIN(SUNXI_PINCTRL_PIN_PE4,
+       SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 4),
                  SUNXI_FUNCTION(0x0, "gpio_in"),
                  SUNXI_FUNCTION(0x1, "gpio_out"),
                  SUNXI_FUNCTION(0x2, "ts0"),           /* D0 */
                  SUNXI_FUNCTION(0x3, "csi0")),         /* D0 */
-       SUNXI_PIN(SUNXI_PINCTRL_PIN_PE5,
+       SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 5),
                  SUNXI_FUNCTION(0x0, "gpio_in"),
                  SUNXI_FUNCTION(0x1, "gpio_out"),
                  SUNXI_FUNCTION(0x2, "ts0"),           /* D1 */
                  SUNXI_FUNCTION(0x3, "csi0"),          /* D1 */
                  SUNXI_FUNCTION(0x4, "sim")),          /* VPPEN */
-       SUNXI_PIN(SUNXI_PINCTRL_PIN_PE6,
+       SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 6),
                  SUNXI_FUNCTION(0x0, "gpio_in"),
                  SUNXI_FUNCTION(0x1, "gpio_out"),
                  SUNXI_FUNCTION(0x2, "ts0"),           /* D2 */
                  SUNXI_FUNCTION(0x3, "csi0")),         /* D2 */
-       SUNXI_PIN(SUNXI_PINCTRL_PIN_PE7,
+       SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 7),
                  SUNXI_FUNCTION(0x0, "gpio_in"),
                  SUNXI_FUNCTION(0x1, "gpio_out"),
                  SUNXI_FUNCTION(0x2, "ts0"),           /* D3 */
                  SUNXI_FUNCTION(0x3, "csi0")),         /* D3 */
-       SUNXI_PIN(SUNXI_PINCTRL_PIN_PE8,
+       SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 8),
                  SUNXI_FUNCTION(0x0, "gpio_in"),
                  SUNXI_FUNCTION(0x1, "gpio_out"),
                  SUNXI_FUNCTION(0x2, "ts0"),           /* D4 */
                  SUNXI_FUNCTION(0x3, "csi0")),         /* D4 */
-       SUNXI_PIN(SUNXI_PINCTRL_PIN_PE9,
+       SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 9),
                  SUNXI_FUNCTION(0x0, "gpio_in"),
                  SUNXI_FUNCTION(0x1, "gpio_out"),
                  SUNXI_FUNCTION(0x2, "ts0"),           /* D5 */
                  SUNXI_FUNCTION(0x3, "csi0")),         /* D5 */
-       SUNXI_PIN(SUNXI_PINCTRL_PIN_PE10,
+       SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 10),
                  SUNXI_FUNCTION(0x0, "gpio_in"),
                  SUNXI_FUNCTION(0x1, "gpio_out"),
                  SUNXI_FUNCTION(0x2, "ts0"),           /* D6 */
                  SUNXI_FUNCTION(0x3, "csi0")),         /* D6 */
-       SUNXI_PIN(SUNXI_PINCTRL_PIN_PE11,
+       SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 11),
                  SUNXI_FUNCTION(0x0, "gpio_in"),
                  SUNXI_FUNCTION(0x1, "gpio_out"),
                  SUNXI_FUNCTION(0x2, "ts0"),           /* D7 */
                  SUNXI_FUNCTION(0x3, "csi0")),         /* D7 */
        /* Hole */
-       SUNXI_PIN(SUNXI_PINCTRL_PIN_PF0,
+       SUNXI_PIN(SUNXI_PINCTRL_PIN(F, 0),
                  SUNXI_FUNCTION(0x0, "gpio_in"),
                  SUNXI_FUNCTION(0x1, "gpio_out"),
                  SUNXI_FUNCTION(0x2, "mmc0"),          /* D1 */
                  SUNXI_FUNCTION(0x4, "jtag")),         /* MSI */
-       SUNXI_PIN(SUNXI_PINCTRL_PIN_PF1,
+       SUNXI_PIN(SUNXI_PINCTRL_PIN(F, 1),
                  SUNXI_FUNCTION(0x0, "gpio_in"),
                  SUNXI_FUNCTION(0x1, "gpio_out"),
                  SUNXI_FUNCTION(0x2, "mmc0"),          /* D0 */
                  SUNXI_FUNCTION(0x4, "jtag")),         /* DI1 */
-       SUNXI_PIN(SUNXI_PINCTRL_PIN_PF2,
+       SUNXI_PIN(SUNXI_PINCTRL_PIN(F, 2),
                  SUNXI_FUNCTION(0x0, "gpio_in"),
                  SUNXI_FUNCTION(0x1, "gpio_out"),
                  SUNXI_FUNCTION(0x2, "mmc0"),          /* CLK */
                  SUNXI_FUNCTION(0x4, "uart0")),        /* TX */
-       SUNXI_PIN(SUNXI_PINCTRL_PIN_PF3,
+       SUNXI_PIN(SUNXI_PINCTRL_PIN(F, 3),
                  SUNXI_FUNCTION(0x0, "gpio_in"),
                  SUNXI_FUNCTION(0x1, "gpio_out"),
                  SUNXI_FUNCTION(0x2, "mmc0"),          /* CMD */
                  SUNXI_FUNCTION(0x4, "jtag")),         /* DO1 */
-       SUNXI_PIN(SUNXI_PINCTRL_PIN_PF4,
+       SUNXI_PIN(SUNXI_PINCTRL_PIN(F, 4),
                  SUNXI_FUNCTION(0x0, "gpio_in"),
                  SUNXI_FUNCTION(0x1, "gpio_out"),
                  SUNXI_FUNCTION(0x2, "mmc0"),          /* D3 */
                  SUNXI_FUNCTION(0x4, "uart0")),        /* RX */
-       SUNXI_PIN(SUNXI_PINCTRL_PIN_PF5,
+       SUNXI_PIN(SUNXI_PINCTRL_PIN(F, 5),
                  SUNXI_FUNCTION(0x0, "gpio_in"),
                  SUNXI_FUNCTION(0x1, "gpio_out"),
                  SUNXI_FUNCTION(0x2, "mmc0"),          /* D2 */
                  SUNXI_FUNCTION(0x4, "jtag")),         /* CK1 */
        /* Hole */
-       SUNXI_PIN(SUNXI_PINCTRL_PIN_PG0,
+       SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 0),
                  SUNXI_FUNCTION(0x0, "gpio_in"),
                  SUNXI_FUNCTION(0x1, "gpio_out"),
                  SUNXI_FUNCTION(0x2, "ts1"),           /* CLK */
                  SUNXI_FUNCTION(0x3, "csi1"),          /* PCK */
                  SUNXI_FUNCTION(0x4, "mmc1")),         /* CMD */
-       SUNXI_PIN(SUNXI_PINCTRL_PIN_PG1,
+       SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 1),
                  SUNXI_FUNCTION(0x0, "gpio_in"),
                  SUNXI_FUNCTION(0x1, "gpio_out"),
                  SUNXI_FUNCTION(0x2, "ts1"),           /* ERR */
                  SUNXI_FUNCTION(0x3, "csi1"),          /* CK */
                  SUNXI_FUNCTION(0x4, "mmc1")),         /* CLK */
-       SUNXI_PIN(SUNXI_PINCTRL_PIN_PG2,
+       SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 2),
                  SUNXI_FUNCTION(0x0, "gpio_in"),
                  SUNXI_FUNCTION(0x1, "gpio_out"),
                  SUNXI_FUNCTION(0x2, "ts1"),           /* SYNC */
                  SUNXI_FUNCTION(0x3, "csi1"),          /* HSYNC */
                  SUNXI_FUNCTION(0x4, "mmc1")),         /* D0 */
-       SUNXI_PIN(SUNXI_PINCTRL_PIN_PG3,
+       SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 3),
                  SUNXI_FUNCTION(0x0, "gpio_in"),
                  SUNXI_FUNCTION(0x1, "gpio_out"),
                  SUNXI_FUNCTION(0x2, "ts1"),           /* DVLD */
                  SUNXI_FUNCTION(0x3, "csi1"),          /* VSYNC */
                  SUNXI_FUNCTION(0x4, "mmc1")),         /* D1 */
-       SUNXI_PIN(SUNXI_PINCTRL_PIN_PG4,
+       SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 4),
                  SUNXI_FUNCTION(0x0, "gpio_in"),
                  SUNXI_FUNCTION(0x1, "gpio_out"),
                  SUNXI_FUNCTION(0x2, "ts1"),           /* D0 */
                  SUNXI_FUNCTION(0x3, "csi1"),          /* D0 */
                  SUNXI_FUNCTION(0x4, "mmc1"),          /* D2 */
                  SUNXI_FUNCTION(0x5, "csi0")),         /* D8 */
-       SUNXI_PIN(SUNXI_PINCTRL_PIN_PG5,
+       SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 5),
                  SUNXI_FUNCTION(0x0, "gpio_in"),
                  SUNXI_FUNCTION(0x1, "gpio_out"),
                  SUNXI_FUNCTION(0x2, "ts1"),           /* D1 */
                  SUNXI_FUNCTION(0x3, "csi1"),          /* D1 */
                  SUNXI_FUNCTION(0x4, "mmc1"),          /* D3 */
                  SUNXI_FUNCTION(0x5, "csi0")),         /* D9 */
-       SUNXI_PIN(SUNXI_PINCTRL_PIN_PG6,
+       SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 6),
                  SUNXI_FUNCTION(0x0, "gpio_in"),
                  SUNXI_FUNCTION(0x1, "gpio_out"),
                  SUNXI_FUNCTION(0x2, "ts1"),           /* D2 */
                  SUNXI_FUNCTION(0x3, "csi1"),          /* D2 */
                  SUNXI_FUNCTION(0x4, "uart3"),         /* TX */
                  SUNXI_FUNCTION(0x5, "csi0")),         /* D10 */
-       SUNXI_PIN(SUNXI_PINCTRL_PIN_PG7,
+       SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 7),
                  SUNXI_FUNCTION(0x0, "gpio_in"),
                  SUNXI_FUNCTION(0x1, "gpio_out"),
                  SUNXI_FUNCTION(0x2, "ts1"),           /* D3 */
                  SUNXI_FUNCTION(0x3, "csi1"),          /* D3 */
                  SUNXI_FUNCTION(0x4, "uart3"),         /* RX */
                  SUNXI_FUNCTION(0x5, "csi0")),         /* D11 */
-       SUNXI_PIN(SUNXI_PINCTRL_PIN_PG8,
+       SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 8),
                  SUNXI_FUNCTION(0x0, "gpio_in"),
                  SUNXI_FUNCTION(0x1, "gpio_out"),
                  SUNXI_FUNCTION(0x2, "ts1"),           /* D4 */
                  SUNXI_FUNCTION(0x3, "csi1"),          /* D4 */
                  SUNXI_FUNCTION(0x4, "uart3"),         /* RTS */
                  SUNXI_FUNCTION(0x5, "csi0")),         /* D12 */
-       SUNXI_PIN(SUNXI_PINCTRL_PIN_PG9,
+       SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 9),
                  SUNXI_FUNCTION(0x0, "gpio_in"),
                  SUNXI_FUNCTION(0x1, "gpio_out"),
                  SUNXI_FUNCTION(0x2, "ts1"),           /* D5 */
                  SUNXI_FUNCTION(0x3, "csi1"),          /* D5 */
                  SUNXI_FUNCTION(0x4, "uart3"),         /* CTS */
                  SUNXI_FUNCTION(0x5, "csi0")),         /* D13 */
-       SUNXI_PIN(SUNXI_PINCTRL_PIN_PG10,
+       SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 10),
                  SUNXI_FUNCTION(0x0, "gpio_in"),
                  SUNXI_FUNCTION(0x1, "gpio_out"),
                  SUNXI_FUNCTION(0x2, "ts1"),           /* D6 */
                  SUNXI_FUNCTION(0x3, "csi1"),          /* D6 */
                  SUNXI_FUNCTION(0x4, "uart4"),         /* TX */
                  SUNXI_FUNCTION(0x5, "csi0")),         /* D14 */
-       SUNXI_PIN(SUNXI_PINCTRL_PIN_PG11,
+       SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 11),
                  SUNXI_FUNCTION(0x0, "gpio_in"),
                  SUNXI_FUNCTION(0x1, "gpio_out"),
                  SUNXI_FUNCTION(0x2, "ts1"),           /* D7 */
@@ -3557,49 +3557,49 @@ static const struct sunxi_desc_pin sun7i_a20_pins[] = {
                  SUNXI_FUNCTION(0x4, "uart4"),         /* RX */
                  SUNXI_FUNCTION(0x5, "csi0")),         /* D15 */
        /* Hole */
-       SUNXI_PIN(SUNXI_PINCTRL_PIN_PH0,
+       SUNXI_PIN(SUNXI_PINCTRL_PIN(H, 0),
                  SUNXI_FUNCTION(0x0, "gpio_in"),
                  SUNXI_FUNCTION(0x1, "gpio_out"),
                  SUNXI_FUNCTION(0x2, "lcd1"),          /* D0 */
                  SUNXI_FUNCTION(0x4, "uart3"),         /* TX */
                  SUNXI_FUNCTION_IRQ(0x6, 0),           /* EINT0 */
                  SUNXI_FUNCTION(0x7, "csi1")),         /* D0 */
-       SUNXI_PIN(SUNXI_PINCTRL_PIN_PH1,
+       SUNXI_PIN(SUNXI_PINCTRL_PIN(H, 1),
                  SUNXI_FUNCTION(0x0, "gpio_in"),
                  SUNXI_FUNCTION(0x1, "gpio_out"),
                  SUNXI_FUNCTION(0x2, "lcd1"),          /* D1 */
                  SUNXI_FUNCTION(0x4, "uart3"),         /* RX */
                  SUNXI_FUNCTION_IRQ(0x6, 1),           /* EINT1 */
                  SUNXI_FUNCTION(0x7, "csi1")),         /* D1 */
-       SUNXI_PIN(SUNXI_PINCTRL_PIN_PH2,
+       SUNXI_PIN(SUNXI_PINCTRL_PIN(H, 2),
                  SUNXI_FUNCTION(0x0, "gpio_in"),
                  SUNXI_FUNCTION(0x1, "gpio_out"),
                  SUNXI_FUNCTION(0x2, "lcd1"),          /* D2 */
                  SUNXI_FUNCTION(0x4, "uart3"),         /* RTS */
                  SUNXI_FUNCTION_IRQ(0x6, 2),           /* EINT2 */
                  SUNXI_FUNCTION(0x7, "csi1")),         /* D2 */
-       SUNXI_PIN(SUNXI_PINCTRL_PIN_PH3,
+       SUNXI_PIN(SUNXI_PINCTRL_PIN(H, 3),
                  SUNXI_FUNCTION(0x0, "gpio_in"),
                  SUNXI_FUNCTION(0x1, "gpio_out"),
                  SUNXI_FUNCTION(0x2, "lcd1"),          /* D3 */
                  SUNXI_FUNCTION(0x4, "uart3"),         /* CTS */
                  SUNXI_FUNCTION_IRQ(0x6, 3),           /* EINT3 */
                  SUNXI_FUNCTION(0x7, "csi1")),         /* D3 */
-       SUNXI_PIN(SUNXI_PINCTRL_PIN_PH4,
+       SUNXI_PIN(SUNXI_PINCTRL_PIN(H, 4),
                  SUNXI_FUNCTION(0x0, "gpio_in"),
                  SUNXI_FUNCTION(0x1, "gpio_out"),
                  SUNXI_FUNCTION(0x2, "lcd1"),          /* D4 */
                  SUNXI_FUNCTION(0x4, "uart4"),         /* TX */
                  SUNXI_FUNCTION_IRQ(0x6, 4),           /* EINT4 */
                  SUNXI_FUNCTION(0x7, "csi1")),         /* D4 */
-       SUNXI_PIN(SUNXI_PINCTRL_PIN_PH5,
+       SUNXI_PIN(SUNXI_PINCTRL_PIN(H, 5),
                  SUNXI_FUNCTION(0x0, "gpio_in"),
                  SUNXI_FUNCTION(0x1, "gpio_out"),
                  SUNXI_FUNCTION(0x2, "lcd1"),          /* D5 */
                  SUNXI_FUNCTION(0x4, "uart4"),         /* RX */
                  SUNXI_FUNCTION_IRQ(0x6, 5),           /* EINT5 */
                  SUNXI_FUNCTION(0x7, "csi1")),         /* D5 */
-       SUNXI_PIN(SUNXI_PINCTRL_PIN_PH6,
+       SUNXI_PIN(SUNXI_PINCTRL_PIN(H, 6),
                  SUNXI_FUNCTION(0x0, "gpio_in"),
                  SUNXI_FUNCTION(0x1, "gpio_out"),
                  SUNXI_FUNCTION(0x2, "lcd1"),          /* D6 */
@@ -3607,7 +3607,7 @@ static const struct sunxi_desc_pin sun7i_a20_pins[] = {
                  SUNXI_FUNCTION(0x5, "ms"),            /* BS */
                  SUNXI_FUNCTION_IRQ(0x6, 6),           /* EINT6 */
                  SUNXI_FUNCTION(0x7, "csi1")),         /* D6 */
-       SUNXI_PIN(SUNXI_PINCTRL_PIN_PH7,
+       SUNXI_PIN(SUNXI_PINCTRL_PIN(H, 7),
                  SUNXI_FUNCTION(0x0, "gpio_in"),
                  SUNXI_FUNCTION(0x1, "gpio_out"),
                  SUNXI_FUNCTION(0x2, "lcd1"),          /* D7 */
@@ -3615,7 +3615,7 @@ static const struct sunxi_desc_pin sun7i_a20_pins[] = {
                  SUNXI_FUNCTION(0x5, "ms"),            /* CLK */
                  SUNXI_FUNCTION_IRQ(0x6, 7),           /* EINT7 */
                  SUNXI_FUNCTION(0x7, "csi1")),         /* D7 */
-       SUNXI_PIN(SUNXI_PINCTRL_PIN_PH8,
+       SUNXI_PIN(SUNXI_PINCTRL_PIN(H, 8),
                  SUNXI_FUNCTION(0x0, "gpio_in"),
                  SUNXI_FUNCTION(0x1, "gpio_out"),
                  SUNXI_FUNCTION(0x2, "lcd1"),          /* D8 */
@@ -3624,7 +3624,7 @@ static const struct sunxi_desc_pin sun7i_a20_pins[] = {
                  SUNXI_FUNCTION(0x5, "ms"),            /* D0 */
                  SUNXI_FUNCTION_IRQ(0x6, 8),           /* EINT8 */
                  SUNXI_FUNCTION(0x7, "csi1")),         /* D8 */
-       SUNXI_PIN(SUNXI_PINCTRL_PIN_PH9,
+       SUNXI_PIN(SUNXI_PINCTRL_PIN(H, 9),
                  SUNXI_FUNCTION(0x0, "gpio_in"),
                  SUNXI_FUNCTION(0x1, "gpio_out"),
                  SUNXI_FUNCTION(0x2, "lcd1"),          /* D9 */
@@ -3633,7 +3633,7 @@ static const struct sunxi_desc_pin sun7i_a20_pins[] = {
                  SUNXI_FUNCTION(0x5, "ms"),            /* D1 */
                  SUNXI_FUNCTION_IRQ(0x6, 9),           /* EINT9 */
                  SUNXI_FUNCTION(0x7, "csi1")),         /* D9 */
-       SUNXI_PIN(SUNXI_PINCTRL_PIN_PH10,
+       SUNXI_PIN(SUNXI_PINCTRL_PIN(H, 10),
                  SUNXI_FUNCTION(0x0, "gpio_in"),
                  SUNXI_FUNCTION(0x1, "gpio_out"),
                  SUNXI_FUNCTION(0x2, "lcd1"),          /* D10 */
@@ -3642,7 +3642,7 @@ static const struct sunxi_desc_pin sun7i_a20_pins[] = {
                  SUNXI_FUNCTION(0x5, "ms"),            /* D2 */
                  SUNXI_FUNCTION_IRQ(0x6, 10),          /* EINT10 */
                  SUNXI_FUNCTION(0x7, "csi1")),         /* D10 */
-       SUNXI_PIN(SUNXI_PINCTRL_PIN_PH11,
+       SUNXI_PIN(SUNXI_PINCTRL_PIN(H, 11),
                  SUNXI_FUNCTION(0x0, "gpio_in"),
                  SUNXI_FUNCTION(0x1, "gpio_out"),
                  SUNXI_FUNCTION(0x2, "lcd1"),          /* D11 */
@@ -3651,14 +3651,14 @@ static const struct sunxi_desc_pin sun7i_a20_pins[] = {
                  SUNXI_FUNCTION(0x5, "ms"),            /* D3 */
                  SUNXI_FUNCTION_IRQ(0x6, 11),          /* EINT11 */
                  SUNXI_FUNCTION(0x7, "csi1")),         /* D11 */
-       SUNXI_PIN(SUNXI_PINCTRL_PIN_PH12,
+       SUNXI_PIN(SUNXI_PINCTRL_PIN(H, 12),
                  SUNXI_FUNCTION(0x0, "gpio_in"),
                  SUNXI_FUNCTION(0x1, "gpio_out"),
                  SUNXI_FUNCTION(0x2, "lcd1"),          /* D12 */
                  SUNXI_FUNCTION(0x4, "ps2"),           /* SCK1 */
                  SUNXI_FUNCTION_IRQ(0x6, 12),          /* EINT12 */
                  SUNXI_FUNCTION(0x7, "csi1")),         /* D12 */
-       SUNXI_PIN(SUNXI_PINCTRL_PIN_PH13,
+       SUNXI_PIN(SUNXI_PINCTRL_PIN(H, 13),
                  SUNXI_FUNCTION(0x0, "gpio_in"),
                  SUNXI_FUNCTION(0x1, "gpio_out"),
                  SUNXI_FUNCTION(0x2, "lcd1"),          /* D13 */
@@ -3666,7 +3666,7 @@ static const struct sunxi_desc_pin sun7i_a20_pins[] = {
                  SUNXI_FUNCTION(0x5, "sim"),           /* RST */
                  SUNXI_FUNCTION_IRQ(0x6, 13),          /* EINT13 */
                  SUNXI_FUNCTION(0x7, "csi1")),         /* D13 */
-       SUNXI_PIN(SUNXI_PINCTRL_PIN_PH14,
+       SUNXI_PIN(SUNXI_PINCTRL_PIN(H, 14),
                  SUNXI_FUNCTION(0x0, "gpio_in"),
                  SUNXI_FUNCTION(0x1, "gpio_out"),
                  SUNXI_FUNCTION(0x2, "lcd1"),          /* D14 */
@@ -3675,7 +3675,7 @@ static const struct sunxi_desc_pin sun7i_a20_pins[] = {
                  SUNXI_FUNCTION(0x5, "sim"),           /* VPPEN */
                  SUNXI_FUNCTION_IRQ(0x6, 14),          /* EINT14 */
                  SUNXI_FUNCTION(0x7, "csi1")),         /* D14 */
-       SUNXI_PIN(SUNXI_PINCTRL_PIN_PH15,
+       SUNXI_PIN(SUNXI_PINCTRL_PIN(H, 15),
                  SUNXI_FUNCTION(0x0, "gpio_in"),
                  SUNXI_FUNCTION(0x1, "gpio_out"),
                  SUNXI_FUNCTION(0x2, "lcd1"),          /* D15 */
@@ -3684,7 +3684,7 @@ static const struct sunxi_desc_pin sun7i_a20_pins[] = {
                  SUNXI_FUNCTION(0x5, "sim"),           /* VPPPP */
                  SUNXI_FUNCTION_IRQ(0x6, 15),          /* EINT15 */
                  SUNXI_FUNCTION(0x7, "csi1")),         /* D15 */
-       SUNXI_PIN(SUNXI_PINCTRL_PIN_PH16,
+       SUNXI_PIN(SUNXI_PINCTRL_PIN(H, 16),
                  SUNXI_FUNCTION(0x0, "gpio_in"),
                  SUNXI_FUNCTION(0x1, "gpio_out"),
                  SUNXI_FUNCTION(0x2, "lcd1"),          /* D16 */
@@ -3692,7 +3692,7 @@ static const struct sunxi_desc_pin sun7i_a20_pins[] = {
                  SUNXI_FUNCTION(0x4, "keypad"),        /* IN6 */
                  SUNXI_FUNCTION_IRQ(0x6, 16),          /* EINT16 */
                  SUNXI_FUNCTION(0x7, "csi1")),         /* D16 */
-       SUNXI_PIN(SUNXI_PINCTRL_PIN_PH17,
+       SUNXI_PIN(SUNXI_PINCTRL_PIN(H, 17),
                  SUNXI_FUNCTION(0x0, "gpio_in"),
                  SUNXI_FUNCTION(0x1, "gpio_out"),
                  SUNXI_FUNCTION(0x2, "lcd1"),          /* D17 */
@@ -3701,7 +3701,7 @@ static const struct sunxi_desc_pin sun7i_a20_pins[] = {
                  SUNXI_FUNCTION(0x5, "sim"),           /* VCCEN */
                  SUNXI_FUNCTION_IRQ(0x6, 17),          /* EINT17 */
                  SUNXI_FUNCTION(0x7, "csi1")),         /* D17 */
-       SUNXI_PIN(SUNXI_PINCTRL_PIN_PH18,
+       SUNXI_PIN(SUNXI_PINCTRL_PIN(H, 18),
                  SUNXI_FUNCTION(0x0, "gpio_in"),
                  SUNXI_FUNCTION(0x1, "gpio_out"),
                  SUNXI_FUNCTION(0x2, "lcd1"),          /* D18 */
@@ -3710,7 +3710,7 @@ static const struct sunxi_desc_pin sun7i_a20_pins[] = {
                  SUNXI_FUNCTION(0x5, "sim"),           /* SCK */
                  SUNXI_FUNCTION_IRQ(0x6, 18),          /* EINT18 */
                  SUNXI_FUNCTION(0x7, "csi1")),         /* D18 */
-       SUNXI_PIN(SUNXI_PINCTRL_PIN_PH19,
+       SUNXI_PIN(SUNXI_PINCTRL_PIN(H, 19),
                  SUNXI_FUNCTION(0x0, "gpio_in"),
                  SUNXI_FUNCTION(0x1, "gpio_out"),
                  SUNXI_FUNCTION(0x2, "lcd1"),          /* D19 */
@@ -3719,7 +3719,7 @@ static const struct sunxi_desc_pin sun7i_a20_pins[] = {
                  SUNXI_FUNCTION(0x5, "sim"),           /* SDA */
                  SUNXI_FUNCTION_IRQ(0x6, 19),          /* EINT19 */
                  SUNXI_FUNCTION(0x7, "csi1")),         /* D19 */
-       SUNXI_PIN(SUNXI_PINCTRL_PIN_PH20,
+       SUNXI_PIN(SUNXI_PINCTRL_PIN(H, 20),
                  SUNXI_FUNCTION(0x0, "gpio_in"),
                  SUNXI_FUNCTION(0x1, "gpio_out"),
                  SUNXI_FUNCTION(0x2, "lcd1"),          /* D20 */
@@ -3727,7 +3727,7 @@ static const struct sunxi_desc_pin sun7i_a20_pins[] = {
                  SUNXI_FUNCTION(0x4, "can"),           /* TX */
                  SUNXI_FUNCTION_IRQ(0x6, 20),          /* EINT20 */
                  SUNXI_FUNCTION(0x7, "csi1")),         /* D20 */
-       SUNXI_PIN(SUNXI_PINCTRL_PIN_PH21,
+       SUNXI_PIN(SUNXI_PINCTRL_PIN(H, 21),
                  SUNXI_FUNCTION(0x0, "gpio_in"),
                  SUNXI_FUNCTION(0x1, "gpio_out"),
                  SUNXI_FUNCTION(0x2, "lcd1"),          /* D21 */
@@ -3735,7 +3735,7 @@ static const struct sunxi_desc_pin sun7i_a20_pins[] = {
                  SUNXI_FUNCTION(0x4, "can"),           /* RX */
                  SUNXI_FUNCTION_IRQ(0x6, 21),          /* EINT21 */
                  SUNXI_FUNCTION(0x7, "csi1")),         /* D21 */
-       SUNXI_PIN(SUNXI_PINCTRL_PIN_PH22,
+       SUNXI_PIN(SUNXI_PINCTRL_PIN(H, 22),
                  SUNXI_FUNCTION(0x0, "gpio_in"),
                  SUNXI_FUNCTION(0x1, "gpio_out"),
                  SUNXI_FUNCTION(0x2, "lcd1"),          /* D22 */
@@ -3743,7 +3743,7 @@ static const struct sunxi_desc_pin sun7i_a20_pins[] = {
                  SUNXI_FUNCTION(0x4, "keypad"),        /* OUT2 */
                  SUNXI_FUNCTION(0x5, "mmc1"),          /* CMD */
                  SUNXI_FUNCTION(0x7, "csi1")),         /* D22 */
-       SUNXI_PIN(SUNXI_PINCTRL_PIN_PH23,
+       SUNXI_PIN(SUNXI_PINCTRL_PIN(H, 23),
                  SUNXI_FUNCTION(0x0, "gpio_in"),
                  SUNXI_FUNCTION(0x1, "gpio_out"),
                  SUNXI_FUNCTION(0x2, "lcd1"),          /* D23 */
@@ -3751,7 +3751,7 @@ static const struct sunxi_desc_pin sun7i_a20_pins[] = {
                  SUNXI_FUNCTION(0x4, "keypad"),        /* OUT3 */
                  SUNXI_FUNCTION(0x5, "mmc1"),          /* CLK */
                  SUNXI_FUNCTION(0x7, "csi1")),         /* D23 */
-       SUNXI_PIN(SUNXI_PINCTRL_PIN_PH24,
+       SUNXI_PIN(SUNXI_PINCTRL_PIN(H, 24),
                  SUNXI_FUNCTION(0x0, "gpio_in"),
                  SUNXI_FUNCTION(0x1, "gpio_out"),
                  SUNXI_FUNCTION(0x2, "lcd1"),          /* CLK */
@@ -3759,7 +3759,7 @@ static const struct sunxi_desc_pin sun7i_a20_pins[] = {
                  SUNXI_FUNCTION(0x4, "keypad"),        /* OUT4 */
                  SUNXI_FUNCTION(0x5, "mmc1"),          /* D0 */
                  SUNXI_FUNCTION(0x7, "csi1")),         /* PCLK */
-       SUNXI_PIN(SUNXI_PINCTRL_PIN_PH25,
+       SUNXI_PIN(SUNXI_PINCTRL_PIN(H, 25),
                  SUNXI_FUNCTION(0x0, "gpio_in"),
                  SUNXI_FUNCTION(0x1, "gpio_out"),
                  SUNXI_FUNCTION(0x2, "lcd1"),          /* DE */
@@ -3767,7 +3767,7 @@ static const struct sunxi_desc_pin sun7i_a20_pins[] = {
                  SUNXI_FUNCTION(0x4, "keypad"),        /* OUT5 */
                  SUNXI_FUNCTION(0x5, "mmc1"),          /* D1 */
                  SUNXI_FUNCTION(0x7, "csi1")),         /* FIELD */
-       SUNXI_PIN(SUNXI_PINCTRL_PIN_PH26,
+       SUNXI_PIN(SUNXI_PINCTRL_PIN(H, 26),
                  SUNXI_FUNCTION(0x0, "gpio_in"),
                  SUNXI_FUNCTION(0x1, "gpio_out"),
                  SUNXI_FUNCTION(0x2, "lcd1"),          /* HSYNC */
@@ -3775,7 +3775,7 @@ static const struct sunxi_desc_pin sun7i_a20_pins[] = {
                  SUNXI_FUNCTION(0x4, "keypad"),        /* OUT6 */
                  SUNXI_FUNCTION(0x5, "mmc1"),          /* D2 */
                  SUNXI_FUNCTION(0x7, "csi1")),         /* HSYNC */
-       SUNXI_PIN(SUNXI_PINCTRL_PIN_PH27,
+       SUNXI_PIN(SUNXI_PINCTRL_PIN(H, 27),
                  SUNXI_FUNCTION(0x0, "gpio_in"),
                  SUNXI_FUNCTION(0x1, "gpio_out"),
                  SUNXI_FUNCTION(0x2, "lcd1"),          /* VSYNC */
@@ -3784,118 +3784,118 @@ static const struct sunxi_desc_pin sun7i_a20_pins[] = {
                  SUNXI_FUNCTION(0x5, "mmc1"),          /* D3 */
                  SUNXI_FUNCTION(0x7, "csi1")),         /* VSYNC */
        /* Hole */
-       SUNXI_PIN(SUNXI_PINCTRL_PIN_PI0,
+       SUNXI_PIN(SUNXI_PINCTRL_PIN(I, 0),
                  SUNXI_FUNCTION(0x0, "gpio_in"),
                  SUNXI_FUNCTION(0x1, "gpio_out"),
                  SUNXI_FUNCTION(0x3, "i2c3")),         /* SCK */
-       SUNXI_PIN(SUNXI_PINCTRL_PIN_PI1,
+       SUNXI_PIN(SUNXI_PINCTRL_PIN(I, 1),
                  SUNXI_FUNCTION(0x0, "gpio_in"),
                  SUNXI_FUNCTION(0x1, "gpio_out"),
                  SUNXI_FUNCTION(0x3, "i2c3")),         /* SDA */
-       SUNXI_PIN(SUNXI_PINCTRL_PIN_PI2,
+       SUNXI_PIN(SUNXI_PINCTRL_PIN(I, 2),
                  SUNXI_FUNCTION(0x0, "gpio_in"),
                  SUNXI_FUNCTION(0x1, "gpio_out"),
                  SUNXI_FUNCTION(0x3, "i2c4")),         /* SCK */
-       SUNXI_PIN(SUNXI_PINCTRL_PIN_PI3,
+       SUNXI_PIN(SUNXI_PINCTRL_PIN(I, 3),
                  SUNXI_FUNCTION(0x0, "gpio_in"),
                  SUNXI_FUNCTION(0x1, "gpio_out"),
                  SUNXI_FUNCTION(0x2, "pwm"),           /* PWM1 */
                  SUNXI_FUNCTION(0x3, "i2c4")),         /* SDA */
-       SUNXI_PIN(SUNXI_PINCTRL_PIN_PI4,
+       SUNXI_PIN(SUNXI_PINCTRL_PIN(I, 4),
                  SUNXI_FUNCTION(0x0, "gpio_in"),
                  SUNXI_FUNCTION(0x1, "gpio_out"),
                  SUNXI_FUNCTION(0x2, "mmc3")),         /* CMD */
-       SUNXI_PIN(SUNXI_PINCTRL_PIN_PI5,
+       SUNXI_PIN(SUNXI_PINCTRL_PIN(I, 5),
                  SUNXI_FUNCTION(0x0, "gpio_in"),
                  SUNXI_FUNCTION(0x1, "gpio_out"),
                  SUNXI_FUNCTION(0x2, "mmc3")),         /* CLK */
-       SUNXI_PIN(SUNXI_PINCTRL_PIN_PI6,
+       SUNXI_PIN(SUNXI_PINCTRL_PIN(I, 6),
                  SUNXI_FUNCTION(0x0, "gpio_in"),
                  SUNXI_FUNCTION(0x1, "gpio_out"),
                  SUNXI_FUNCTION(0x2, "mmc3")),         /* D0 */
-       SUNXI_PIN(SUNXI_PINCTRL_PIN_PI7,
+       SUNXI_PIN(SUNXI_PINCTRL_PIN(I, 7),
                  SUNXI_FUNCTION(0x0, "gpio_in"),
                  SUNXI_FUNCTION(0x1, "gpio_out"),
                  SUNXI_FUNCTION(0x2, "mmc3")),         /* D1 */
-       SUNXI_PIN(SUNXI_PINCTRL_PIN_PI8,
+       SUNXI_PIN(SUNXI_PINCTRL_PIN(I, 8),
                  SUNXI_FUNCTION(0x0, "gpio_in"),
                  SUNXI_FUNCTION(0x1, "gpio_out"),
                  SUNXI_FUNCTION(0x2, "mmc3")),         /* D2 */
-       SUNXI_PIN(SUNXI_PINCTRL_PIN_PI9,
+       SUNXI_PIN(SUNXI_PINCTRL_PIN(I, 9),
                  SUNXI_FUNCTION(0x0, "gpio_in"),
                  SUNXI_FUNCTION(0x1, "gpio_out"),
                  SUNXI_FUNCTION(0x2, "mmc3")),         /* D3 */
-       SUNXI_PIN(SUNXI_PINCTRL_PIN_PI10,
+       SUNXI_PIN(SUNXI_PINCTRL_PIN(I, 10),
                  SUNXI_FUNCTION(0x0, "gpio_in"),
                  SUNXI_FUNCTION(0x1, "gpio_out"),
                  SUNXI_FUNCTION(0x2, "spi0"),          /* CS0 */
                  SUNXI_FUNCTION(0x3, "uart5"),         /* TX */
                  SUNXI_FUNCTION_IRQ(0x5, 22)),         /* EINT22 */
-       SUNXI_PIN(SUNXI_PINCTRL_PIN_PI11,
+       SUNXI_PIN(SUNXI_PINCTRL_PIN(I, 11),
                  SUNXI_FUNCTION(0x0, "gpio_in"),
                  SUNXI_FUNCTION(0x1, "gpio_out"),
                  SUNXI_FUNCTION(0x2, "spi0"),          /* CLK */
                  SUNXI_FUNCTION(0x3, "uart5"),         /* RX */
                  SUNXI_FUNCTION_IRQ(0x5, 23)),         /* EINT23 */
-       SUNXI_PIN(SUNXI_PINCTRL_PIN_PI12,
+       SUNXI_PIN(SUNXI_PINCTRL_PIN(I, 12),
                  SUNXI_FUNCTION(0x0, "gpio_in"),
                  SUNXI_FUNCTION(0x1, "gpio_out"),
                  SUNXI_FUNCTION(0x2, "spi0"),          /* MOSI */
                  SUNXI_FUNCTION(0x3, "uart6"),         /* TX */
                  SUNXI_FUNCTION(0x4, "clk_out_a"),     /* CLK_OUT_A */
                  SUNXI_FUNCTION_IRQ(0x5, 24)),         /* EINT24 */
-       SUNXI_PIN(SUNXI_PINCTRL_PIN_PI13,
+       SUNXI_PIN(SUNXI_PINCTRL_PIN(I, 13),
                  SUNXI_FUNCTION(0x0, "gpio_in"),
                  SUNXI_FUNCTION(0x1, "gpio_out"),
                  SUNXI_FUNCTION(0x2, "spi0"),          /* MISO */
                  SUNXI_FUNCTION(0x3, "uart6"),         /* RX */
                  SUNXI_FUNCTION(0x4, "clk_out_b"),     /* CLK_OUT_B */
                  SUNXI_FUNCTION_IRQ(0x5, 25)),         /* EINT25 */
-       SUNXI_PIN(SUNXI_PINCTRL_PIN_PI14,
+       SUNXI_PIN(SUNXI_PINCTRL_PIN(I, 14),
                  SUNXI_FUNCTION(0x0, "gpio_in"),
                  SUNXI_FUNCTION(0x1, "gpio_out"),
                  SUNXI_FUNCTION(0x2, "spi0"),          /* CS1 */
                  SUNXI_FUNCTION(0x3, "ps2"),           /* SCK1 */
                  SUNXI_FUNCTION(0x4, "timer4"),        /* TCLKIN0 */
                  SUNXI_FUNCTION_IRQ(0x5, 26)),         /* EINT26 */
-       SUNXI_PIN(SUNXI_PINCTRL_PIN_PI15,
+       SUNXI_PIN(SUNXI_PINCTRL_PIN(I, 15),
                  SUNXI_FUNCTION(0x0, "gpio_in"),
                  SUNXI_FUNCTION(0x1, "gpio_out"),
                  SUNXI_FUNCTION(0x2, "spi1"),          /* CS1 */
                  SUNXI_FUNCTION(0x3, "ps2"),           /* SDA1 */
                  SUNXI_FUNCTION(0x4, "timer5"),        /* TCLKIN1 */
                  SUNXI_FUNCTION_IRQ(0x5, 27)),         /* EINT27 */
-       SUNXI_PIN(SUNXI_PINCTRL_PIN_PI16,
+       SUNXI_PIN(SUNXI_PINCTRL_PIN(I, 16),
                  SUNXI_FUNCTION(0x0, "gpio_in"),
                  SUNXI_FUNCTION(0x1, "gpio_out"),
                  SUNXI_FUNCTION(0x2, "spi1"),          /* CS0 */
                  SUNXI_FUNCTION(0x3, "uart2"),         /* RTS */
                  SUNXI_FUNCTION_IRQ(0x5, 28)),         /* EINT28 */
-       SUNXI_PIN(SUNXI_PINCTRL_PIN_PI17,
+       SUNXI_PIN(SUNXI_PINCTRL_PIN(I, 17),
                  SUNXI_FUNCTION(0x0, "gpio_in"),
                  SUNXI_FUNCTION(0x1, "gpio_out"),
                  SUNXI_FUNCTION(0x2, "spi1"),          /* CLK */
                  SUNXI_FUNCTION(0x3, "uart2"),         /* CTS */
                  SUNXI_FUNCTION_IRQ(0x5, 29)),         /* EINT29 */
-       SUNXI_PIN(SUNXI_PINCTRL_PIN_PI18,
+       SUNXI_PIN(SUNXI_PINCTRL_PIN(I, 18),
                  SUNXI_FUNCTION(0x0, "gpio_in"),
                  SUNXI_FUNCTION(0x1, "gpio_out"),
                  SUNXI_FUNCTION(0x2, "spi1"),          /* MOSI */
                  SUNXI_FUNCTION(0x3, "uart2"),         /* TX */
                  SUNXI_FUNCTION_IRQ(0x5, 30)),         /* EINT30 */
-       SUNXI_PIN(SUNXI_PINCTRL_PIN_PI19,
+       SUNXI_PIN(SUNXI_PINCTRL_PIN(I, 19),
                  SUNXI_FUNCTION(0x0, "gpio_in"),
                  SUNXI_FUNCTION(0x1, "gpio_out"),
                  SUNXI_FUNCTION(0x2, "spi1"),          /* MISO */
                  SUNXI_FUNCTION(0x3, "uart2"),         /* RX */
                  SUNXI_FUNCTION_IRQ(0x5, 31)),         /* EINT31 */
-       SUNXI_PIN(SUNXI_PINCTRL_PIN_PI20,
+       SUNXI_PIN(SUNXI_PINCTRL_PIN(I, 20),
                  SUNXI_FUNCTION(0x0, "gpio_in"),
                  SUNXI_FUNCTION(0x1, "gpio_out"),
                  SUNXI_FUNCTION(0x2, "ps2"),           /* SCK0 */
                  SUNXI_FUNCTION(0x3, "uart7"),         /* TX */
                  SUNXI_FUNCTION(0x4, "hdmi")),         /* HSCL */
-       SUNXI_PIN(SUNXI_PINCTRL_PIN_PI21,
+       SUNXI_PIN(SUNXI_PINCTRL_PIN(I, 21),
                  SUNXI_FUNCTION(0x0, "gpio_in"),
                  SUNXI_FUNCTION(0x1, "gpio_out"),
                  SUNXI_FUNCTION(0x2, "ps2"),           /* SDA0 */

diff --git a/drivers/pinctrl/sunxi/pinctrl-sunxi.h b/drivers/pinctrl/sunxi/pinctrl-sunxi.h
index 4e24b9b..9775a50 100644 (file)
--- a/drivers/pinctrl/sunxi/pinctrl-sunxi.h
+++ b/drivers/pinctrl/sunxi/pinctrl-sunxi.h
@@ -28,368 +28,8 @@
 #define PL_BASE        352
 #define PM_BASE        384
 
-#define SUNXI_PINCTRL_PIN_PA0  PINCTRL_PIN(PA_BASE + 0, "PA0")
-#define SUNXI_PINCTRL_PIN_PA1  PINCTRL_PIN(PA_BASE + 1, "PA1")
-#define SUNXI_PINCTRL_PIN_PA2  PINCTRL_PIN(PA_BASE + 2, "PA2")
-#define SUNXI_PINCTRL_PIN_PA3  PINCTRL_PIN(PA_BASE + 3, "PA3")
-#define SUNXI_PINCTRL_PIN_PA4  PINCTRL_PIN(PA_BASE + 4, "PA4")
-#define SUNXI_PINCTRL_PIN_PA5  PINCTRL_PIN(PA_BASE + 5, "PA5")
-#define SUNXI_PINCTRL_PIN_PA6  PINCTRL_PIN(PA_BASE + 6, "PA6")
-#define SUNXI_PINCTRL_PIN_PA7  PINCTRL_PIN(PA_BASE + 7, "PA7")
-#define SUNXI_PINCTRL_PIN_PA8  PINCTRL_PIN(PA_BASE + 8, "PA8")
-#define SUNXI_PINCTRL_PIN_PA9  PINCTRL_PIN(PA_BASE + 9, "PA9")
-#define SUNXI_PINCTRL_PIN_PA10 PINCTRL_PIN(PA_BASE + 10, "PA10")
-#define SUNXI_PINCTRL_PIN_PA11 PINCTRL_PIN(PA_BASE + 11, "PA11")
-#define SUNXI_PINCTRL_PIN_PA12 PINCTRL_PIN(PA_BASE + 12, "PA12")
-#define SUNXI_PINCTRL_PIN_PA13 PINCTRL_PIN(PA_BASE + 13, "PA13")
-#define SUNXI_PINCTRL_PIN_PA14 PINCTRL_PIN(PA_BASE + 14, "PA14")
-#define SUNXI_PINCTRL_PIN_PA15 PINCTRL_PIN(PA_BASE + 15, "PA15")
-#define SUNXI_PINCTRL_PIN_PA16 PINCTRL_PIN(PA_BASE + 16, "PA16")
-#define SUNXI_PINCTRL_PIN_PA17 PINCTRL_PIN(PA_BASE + 17, "PA17")
-#define SUNXI_PINCTRL_PIN_PA18 PINCTRL_PIN(PA_BASE + 18, "PA18")
-#define SUNXI_PINCTRL_PIN_PA19 PINCTRL_PIN(PA_BASE + 19, "PA19")
-#define SUNXI_PINCTRL_PIN_PA20 PINCTRL_PIN(PA_BASE + 20, "PA20")
-#define SUNXI_PINCTRL_PIN_PA21 PINCTRL_PIN(PA_BASE + 21, "PA21")
-#define SUNXI_PINCTRL_PIN_PA22 PINCTRL_PIN(PA_BASE + 22, "PA22")
-#define SUNXI_PINCTRL_PIN_PA23 PINCTRL_PIN(PA_BASE + 23, "PA23")
-#define SUNXI_PINCTRL_PIN_PA24 PINCTRL_PIN(PA_BASE + 24, "PA24")
-#define SUNXI_PINCTRL_PIN_PA25 PINCTRL_PIN(PA_BASE + 25, "PA25")
-#define SUNXI_PINCTRL_PIN_PA26 PINCTRL_PIN(PA_BASE + 26, "PA26")
-#define SUNXI_PINCTRL_PIN_PA27 PINCTRL_PIN(PA_BASE + 27, "PA27")
-#define SUNXI_PINCTRL_PIN_PA28 PINCTRL_PIN(PA_BASE + 28, "PA28")
-#define SUNXI_PINCTRL_PIN_PA29 PINCTRL_PIN(PA_BASE + 29, "PA29")
-#define SUNXI_PINCTRL_PIN_PA30 PINCTRL_PIN(PA_BASE + 30, "PA30")
-#define SUNXI_PINCTRL_PIN_PA31 PINCTRL_PIN(PA_BASE + 31, "PA31")
-
-#define SUNXI_PINCTRL_PIN_PB0  PINCTRL_PIN(PB_BASE + 0, "PB0")
-#define SUNXI_PINCTRL_PIN_PB1  PINCTRL_PIN(PB_BASE + 1, "PB1")
-#define SUNXI_PINCTRL_PIN_PB2  PINCTRL_PIN(PB_BASE + 2, "PB2")
-#define SUNXI_PINCTRL_PIN_PB3  PINCTRL_PIN(PB_BASE + 3, "PB3")
-#define SUNXI_PINCTRL_PIN_PB4  PINCTRL_PIN(PB_BASE + 4, "PB4")
-#define SUNXI_PINCTRL_PIN_PB5  PINCTRL_PIN(PB_BASE + 5, "PB5")
-#define SUNXI_PINCTRL_PIN_PB6  PINCTRL_PIN(PB_BASE + 6, "PB6")
-#define SUNXI_PINCTRL_PIN_PB7  PINCTRL_PIN(PB_BASE + 7, "PB7")
-#define SUNXI_PINCTRL_PIN_PB8  PINCTRL_PIN(PB_BASE + 8, "PB8")
-#define SUNXI_PINCTRL_PIN_PB9  PINCTRL_PIN(PB_BASE + 9, "PB9")
-#define SUNXI_PINCTRL_PIN_PB10 PINCTRL_PIN(PB_BASE + 10, "PB10")
-#define SUNXI_PINCTRL_PIN_PB11 PINCTRL_PIN(PB_BASE + 11, "PB11")
-#define SUNXI_PINCTRL_PIN_PB12 PINCTRL_PIN(PB_BASE + 12, "PB12")
-#define SUNXI_PINCTRL_PIN_PB13 PINCTRL_PIN(PB_BASE + 13, "PB13")
-#define SUNXI_PINCTRL_PIN_PB14 PINCTRL_PIN(PB_BASE + 14, "PB14")
-#define SUNXI_PINCTRL_PIN_PB15 PINCTRL_PIN(PB_BASE + 15, "PB15")
-#define SUNXI_PINCTRL_PIN_PB16 PINCTRL_PIN(PB_BASE + 16, "PB16")
-#define SUNXI_PINCTRL_PIN_PB17 PINCTRL_PIN(PB_BASE + 17, "PB17")
-#define SUNXI_PINCTRL_PIN_PB18 PINCTRL_PIN(PB_BASE + 18, "PB18")
-#define SUNXI_PINCTRL_PIN_PB19 PINCTRL_PIN(PB_BASE + 19, "PB19")
-#define SUNXI_PINCTRL_PIN_PB20 PINCTRL_PIN(PB_BASE + 20, "PB20")
-#define SUNXI_PINCTRL_PIN_PB21 PINCTRL_PIN(PB_BASE + 21, "PB21")
-#define SUNXI_PINCTRL_PIN_PB22 PINCTRL_PIN(PB_BASE + 22, "PB22")
-#define SUNXI_PINCTRL_PIN_PB23 PINCTRL_PIN(PB_BASE + 23, "PB23")
-#define SUNXI_PINCTRL_PIN_PB24 PINCTRL_PIN(PB_BASE + 24, "PB24")
-#define SUNXI_PINCTRL_PIN_PB25 PINCTRL_PIN(PB_BASE + 25, "PB25")
-#define SUNXI_PINCTRL_PIN_PB26 PINCTRL_PIN(PB_BASE + 26, "PB26")
-#define SUNXI_PINCTRL_PIN_PB27 PINCTRL_PIN(PB_BASE + 27, "PB27")
-#define SUNXI_PINCTRL_PIN_PB28 PINCTRL_PIN(PB_BASE + 28, "PB28")
-#define SUNXI_PINCTRL_PIN_PB29 PINCTRL_PIN(PB_BASE + 29, "PB29")
-#define SUNXI_PINCTRL_PIN_PB30 PINCTRL_PIN(PB_BASE + 30, "PB30")
-#define SUNXI_PINCTRL_PIN_PB31 PINCTRL_PIN(PB_BASE + 31, "PB31")
-
-#define SUNXI_PINCTRL_PIN_PC0  PINCTRL_PIN(PC_BASE + 0, "PC0")
-#define SUNXI_PINCTRL_PIN_PC1  PINCTRL_PIN(PC_BASE + 1, "PC1")
-#define SUNXI_PINCTRL_PIN_PC2  PINCTRL_PIN(PC_BASE + 2, "PC2")
-#define SUNXI_PINCTRL_PIN_PC3  PINCTRL_PIN(PC_BASE + 3, "PC3")
-#define SUNXI_PINCTRL_PIN_PC4  PINCTRL_PIN(PC_BASE + 4, "PC4")
-#define SUNXI_PINCTRL_PIN_PC5  PINCTRL_PIN(PC_BASE + 5, "PC5")
-#define SUNXI_PINCTRL_PIN_PC6  PINCTRL_PIN(PC_BASE + 6, "PC6")
-#define SUNXI_PINCTRL_PIN_PC7  PINCTRL_PIN(PC_BASE + 7, "PC7")
-#define SUNXI_PINCTRL_PIN_PC8  PINCTRL_PIN(PC_BASE + 8, "PC8")
-#define SUNXI_PINCTRL_PIN_PC9  PINCTRL_PIN(PC_BASE + 9, "PC9")
-#define SUNXI_PINCTRL_PIN_PC10 PINCTRL_PIN(PC_BASE + 10, "PC10")
-#define SUNXI_PINCTRL_PIN_PC11 PINCTRL_PIN(PC_BASE + 11, "PC11")
-#define SUNXI_PINCTRL_PIN_PC12 PINCTRL_PIN(PC_BASE + 12, "PC12")
-#define SUNXI_PINCTRL_PIN_PC13 PINCTRL_PIN(PC_BASE + 13, "PC13")
-#define SUNXI_PINCTRL_PIN_PC14 PINCTRL_PIN(PC_BASE + 14, "PC14")
-#define SUNXI_PINCTRL_PIN_PC15 PINCTRL_PIN(PC_BASE + 15, "PC15")
-#define SUNXI_PINCTRL_PIN_PC16 PINCTRL_PIN(PC_BASE + 16, "PC16")
-#define SUNXI_PINCTRL_PIN_PC17 PINCTRL_PIN(PC_BASE + 17, "PC17")
-#define SUNXI_PINCTRL_PIN_PC18 PINCTRL_PIN(PC_BASE + 18, "PC18")
-#define SUNXI_PINCTRL_PIN_PC19 PINCTRL_PIN(PC_BASE + 19, "PC19")
-#define SUNXI_PINCTRL_PIN_PC20 PINCTRL_PIN(PC_BASE + 20, "PC20")
-#define SUNXI_PINCTRL_PIN_PC21 PINCTRL_PIN(PC_BASE + 21, "PC21")
-#define SUNXI_PINCTRL_PIN_PC22 PINCTRL_PIN(PC_BASE + 22, "PC22")
-#define SUNXI_PINCTRL_PIN_PC23 PINCTRL_PIN(PC_BASE + 23, "PC23")
-#define SUNXI_PINCTRL_PIN_PC24 PINCTRL_PIN(PC_BASE + 24, "PC24")
-#define SUNXI_PINCTRL_PIN_PC25 PINCTRL_PIN(PC_BASE + 25, "PC25")
-#define SUNXI_PINCTRL_PIN_PC26 PINCTRL_PIN(PC_BASE + 26, "PC26")
-#define SUNXI_PINCTRL_PIN_PC27 PINCTRL_PIN(PC_BASE + 27, "PC27")
-#define SUNXI_PINCTRL_PIN_PC28 PINCTRL_PIN(PC_BASE + 28, "PC28")
-#define SUNXI_PINCTRL_PIN_PC29 PINCTRL_PIN(PC_BASE + 29, "PC29")
-#define SUNXI_PINCTRL_PIN_PC30 PINCTRL_PIN(PC_BASE + 30, "PC30")
-#define SUNXI_PINCTRL_PIN_PC31 PINCTRL_PIN(PC_BASE + 31, "PC31")
-
-#define SUNXI_PINCTRL_PIN_PD0  PINCTRL_PIN(PD_BASE + 0, "PD0")
-#define SUNXI_PINCTRL_PIN_PD1  PINCTRL_PIN(PD_BASE + 1, "PD1")
-#define SUNXI_PINCTRL_PIN_PD2  PINCTRL_PIN(PD_BASE + 2, "PD2")
-#define SUNXI_PINCTRL_PIN_PD3  PINCTRL_PIN(PD_BASE + 3, "PD3")
-#define SUNXI_PINCTRL_PIN_PD4  PINCTRL_PIN(PD_BASE + 4, "PD4")
-#define SUNXI_PINCTRL_PIN_PD5  PINCTRL_PIN(PD_BASE + 5, "PD5")
-#define SUNXI_PINCTRL_PIN_PD6  PINCTRL_PIN(PD_BASE + 6, "PD6")
-#define SUNXI_PINCTRL_PIN_PD7  PINCTRL_PIN(PD_BASE + 7, "PD7")
-#define SUNXI_PINCTRL_PIN_PD8  PINCTRL_PIN(PD_BASE + 8, "PD8")
-#define SUNXI_PINCTRL_PIN_PD9  PINCTRL_PIN(PD_BASE + 9, "PD9")
-#define SUNXI_PINCTRL_PIN_PD10 PINCTRL_PIN(PD_BASE + 10, "PD10")
-#define SUNXI_PINCTRL_PIN_PD11 PINCTRL_PIN(PD_BASE + 11, "PD11")
-#define SUNXI_PINCTRL_PIN_PD12 PINCTRL_PIN(PD_BASE + 12, "PD12")
-#define SUNXI_PINCTRL_PIN_PD13 PINCTRL_PIN(PD_BASE + 13, "PD13")
-#define SUNXI_PINCTRL_PIN_PD14 PINCTRL_PIN(PD_BASE + 14, "PD14")
-#define SUNXI_PINCTRL_PIN_PD15 PINCTRL_PIN(PD_BASE + 15, "PD15")
-#define SUNXI_PINCTRL_PIN_PD16 PINCTRL_PIN(PD_BASE + 16, "PD16")
-#define SUNXI_PINCTRL_PIN_PD17 PINCTRL_PIN(PD_BASE + 17, "PD17")
-#define SUNXI_PINCTRL_PIN_PD18 PINCTRL_PIN(PD_BASE + 18, "PD18")
-#define SUNXI_PINCTRL_PIN_PD19 PINCTRL_PIN(PD_BASE + 19, "PD19")
-#define SUNXI_PINCTRL_PIN_PD20 PINCTRL_PIN(PD_BASE + 20, "PD20")
-#define SUNXI_PINCTRL_PIN_PD21 PINCTRL_PIN(PD_BASE + 21, "PD21")
-#define SUNXI_PINCTRL_PIN_PD22 PINCTRL_PIN(PD_BASE + 22, "PD22")
-#define SUNXI_PINCTRL_PIN_PD23 PINCTRL_PIN(PD_BASE + 23, "PD23")
-#define SUNXI_PINCTRL_PIN_PD24 PINCTRL_PIN(PD_BASE + 24, "PD24")
-#define SUNXI_PINCTRL_PIN_PD25 PINCTRL_PIN(PD_BASE + 25, "PD25")
-#define SUNXI_PINCTRL_PIN_PD26 PINCTRL_PIN(PD_BASE + 26, "PD26")
-#define SUNXI_PINCTRL_PIN_PD27 PINCTRL_PIN(PD_BASE + 27, "PD27")
-#define SUNXI_PINCTRL_PIN_PD28 PINCTRL_PIN(PD_BASE + 28, "PD28")
-#define SUNXI_PINCTRL_PIN_PD29 PINCTRL_PIN(PD_BASE + 29, "PD29")
-#define SUNXI_PINCTRL_PIN_PD30 PINCTRL_PIN(PD_BASE + 30, "PD30")
-#define SUNXI_PINCTRL_PIN_PD31 PINCTRL_PIN(PD_BASE + 31, "PD31")
-
-#define SUNXI_PINCTRL_PIN_PE0  PINCTRL_PIN(PE_BASE + 0, "PE0")
-#define SUNXI_PINCTRL_PIN_PE1  PINCTRL_PIN(PE_BASE + 1, "PE1")
-#define SUNXI_PINCTRL_PIN_PE2  PINCTRL_PIN(PE_BASE + 2, "PE2")
-#define SUNXI_PINCTRL_PIN_PE3  PINCTRL_PIN(PE_BASE + 3, "PE3")
-#define SUNXI_PINCTRL_PIN_PE4  PINCTRL_PIN(PE_BASE + 4, "PE4")
-#define SUNXI_PINCTRL_PIN_PE5  PINCTRL_PIN(PE_BASE + 5, "PE5")
-#define SUNXI_PINCTRL_PIN_PE6  PINCTRL_PIN(PE_BASE + 6, "PE6")
-#define SUNXI_PINCTRL_PIN_PE7  PINCTRL_PIN(PE_BASE + 7, "PE7")
-#define SUNXI_PINCTRL_PIN_PE8  PINCTRL_PIN(PE_BASE + 8, "PE8")
-#define SUNXI_PINCTRL_PIN_PE9  PINCTRL_PIN(PE_BASE + 9, "PE9")
-#define SUNXI_PINCTRL_PIN_PE10 PINCTRL_PIN(PE_BASE + 10, "PE10")
-#define SUNXI_PINCTRL_PIN_PE11 PINCTRL_PIN(PE_BASE + 11, "PE11")
-#define SUNXI_PINCTRL_PIN_PE12 PINCTRL_PIN(PE_BASE + 12, "PE12")
-#define SUNXI_PINCTRL_PIN_PE13 PINCTRL_PIN(PE_BASE + 13, "PE13")
-#define SUNXI_PINCTRL_PIN_PE14 PINCTRL_PIN(PE_BASE + 14, "PE14")
-#define SUNXI_PINCTRL_PIN_PE15 PINCTRL_PIN(PE_BASE + 15, "PE15")
-#define SUNXI_PINCTRL_PIN_PE16 PINCTRL_PIN(PE_BASE + 16, "PE16")
-#define SUNXI_PINCTRL_PIN_PE17 PINCTRL_PIN(PE_BASE + 17, "PE17")
-#define SUNXI_PINCTRL_PIN_PE18 PINCTRL_PIN(PE_BASE + 18, "PE18")
-#define SUNXI_PINCTRL_PIN_PE19 PINCTRL_PIN(PE_BASE + 19, "PE19")
-#define SUNXI_PINCTRL_PIN_PE20 PINCTRL_PIN(PE_BASE + 20, "PE20")
-#define SUNXI_PINCTRL_PIN_PE21 PINCTRL_PIN(PE_BASE + 21, "PE21")
-#define SUNXI_PINCTRL_PIN_PE22 PINCTRL_PIN(PE_BASE + 22, "PE22")
-#define SUNXI_PINCTRL_PIN_PE23 PINCTRL_PIN(PE_BASE + 23, "PE23")
-#define SUNXI_PINCTRL_PIN_PE24 PINCTRL_PIN(PE_BASE + 24, "PE24")
-#define SUNXI_PINCTRL_PIN_PE25 PINCTRL_PIN(PE_BASE + 25, "PE25")
-#define SUNXI_PINCTRL_PIN_PE26 PINCTRL_PIN(PE_BASE + 26, "PE26")
-#define SUNXI_PINCTRL_PIN_PE27 PINCTRL_PIN(PE_BASE + 27, "PE27")
-#define SUNXI_PINCTRL_PIN_PE28 PINCTRL_PIN(PE_BASE + 28, "PE28")
-#define SUNXI_PINCTRL_PIN_PE29 PINCTRL_PIN(PE_BASE + 29, "PE29")
-#define SUNXI_PINCTRL_PIN_PE30 PINCTRL_PIN(PE_BASE + 30, "PE30")
-#define SUNXI_PINCTRL_PIN_PE31 PINCTRL_PIN(PE_BASE + 31, "PE31")
-
-#define SUNXI_PINCTRL_PIN_PF0  PINCTRL_PIN(PF_BASE + 0, "PF0")
-#define SUNXI_PINCTRL_PIN_PF1  PINCTRL_PIN(PF_BASE + 1, "PF1")
-#define SUNXI_PINCTRL_PIN_PF2  PINCTRL_PIN(PF_BASE + 2, "PF2")
-#define SUNXI_PINCTRL_PIN_PF3  PINCTRL_PIN(PF_BASE + 3, "PF3")
-#define SUNXI_PINCTRL_PIN_PF4  PINCTRL_PIN(PF_BASE + 4, "PF4")
-#define SUNXI_PINCTRL_PIN_PF5  PINCTRL_PIN(PF_BASE + 5, "PF5")
-#define SUNXI_PINCTRL_PIN_PF6  PINCTRL_PIN(PF_BASE + 6, "PF6")
-#define SUNXI_PINCTRL_PIN_PF7  PINCTRL_PIN(PF_BASE + 7, "PF7")
-#define SUNXI_PINCTRL_PIN_PF8  PINCTRL_PIN(PF_BASE + 8, "PF8")
-#define SUNXI_PINCTRL_PIN_PF9  PINCTRL_PIN(PF_BASE + 9, "PF9")
-#define SUNXI_PINCTRL_PIN_PF10 PINCTRL_PIN(PF_BASE + 10, "PF10")
-#define SUNXI_PINCTRL_PIN_PF11 PINCTRL_PIN(PF_BASE + 11, "PF11")
-#define SUNXI_PINCTRL_PIN_PF12 PINCTRL_PIN(PF_BASE + 12, "PF12")
-#define SUNXI_PINCTRL_PIN_PF13 PINCTRL_PIN(PF_BASE + 13, "PF13")
-#define SUNXI_PINCTRL_PIN_PF14 PINCTRL_PIN(PF_BASE + 14, "PF14")
-#define SUNXI_PINCTRL_PIN_PF15 PINCTRL_PIN(PF_BASE + 15, "PF15")
-#define SUNXI_PINCTRL_PIN_PF16 PINCTRL_PIN(PF_BASE + 16, "PF16")
-#define SUNXI_PINCTRL_PIN_PF17 PINCTRL_PIN(PF_BASE + 17, "PF17")
-#define SUNXI_PINCTRL_PIN_PF18 PINCTRL_PIN(PF_BASE + 18, "PF18")
-#define SUNXI_PINCTRL_PIN_PF19 PINCTRL_PIN(PF_BASE + 19, "PF19")
-#define SUNXI_PINCTRL_PIN_PF20 PINCTRL_PIN(PF_BASE + 20, "PF20")
-#define SUNXI_PINCTRL_PIN_PF21 PINCTRL_PIN(PF_BASE + 21, "PF21")
-#define SUNXI_PINCTRL_PIN_PF22 PINCTRL_PIN(PF_BASE + 22, "PF22")
-#define SUNXI_PINCTRL_PIN_PF23 PINCTRL_PIN(PF_BASE + 23, "PF23")
-#define SUNXI_PINCTRL_PIN_PF24 PINCTRL_PIN(PF_BASE + 24, "PF24")
-#define SUNXI_PINCTRL_PIN_PF25 PINCTRL_PIN(PF_BASE + 25, "PF25")
-#define SUNXI_PINCTRL_PIN_PF26 PINCTRL_PIN(PF_BASE + 26, "PF26")
-#define SUNXI_PINCTRL_PIN_PF27 PINCTRL_PIN(PF_BASE + 27, "PF27")
-#define SUNXI_PINCTRL_PIN_PF28 PINCTRL_PIN(PF_BASE + 28, "PF28")
-#define SUNXI_PINCTRL_PIN_PF29 PINCTRL_PIN(PF_BASE + 29, "PF29")
-#define SUNXI_PINCTRL_PIN_PF30 PINCTRL_PIN(PF_BASE + 30, "PF30")
-#define SUNXI_PINCTRL_PIN_PF31 PINCTRL_PIN(PF_BASE + 31, "PF31")
-
-#define SUNXI_PINCTRL_PIN_PG0  PINCTRL_PIN(PG_BASE + 0, "PG0")
-#define SUNXI_PINCTRL_PIN_PG1  PINCTRL_PIN(PG_BASE + 1, "PG1")
-#define SUNXI_PINCTRL_PIN_PG2  PINCTRL_PIN(PG_BASE + 2, "PG2")
-#define SUNXI_PINCTRL_PIN_PG3  PINCTRL_PIN(PG_BASE + 3, "PG3")
-#define SUNXI_PINCTRL_PIN_PG4  PINCTRL_PIN(PG_BASE + 4, "PG4")
-#define SUNXI_PINCTRL_PIN_PG5  PINCTRL_PIN(PG_BASE + 5, "PG5")
-#define SUNXI_PINCTRL_PIN_PG6  PINCTRL_PIN(PG_BASE + 6, "PG6")
-#define SUNXI_PINCTRL_PIN_PG7  PINCTRL_PIN(PG_BASE + 7, "PG7")
-#define SUNXI_PINCTRL_PIN_PG8  PINCTRL_PIN(PG_BASE + 8, "PG8")
-#define SUNXI_PINCTRL_PIN_PG9  PINCTRL_PIN(PG_BASE + 9, "PG9")
-#define SUNXI_PINCTRL_PIN_PG10 PINCTRL_PIN(PG_BASE + 10, "PG10")
-#define SUNXI_PINCTRL_PIN_PG11 PINCTRL_PIN(PG_BASE + 11, "PG11")
-#define SUNXI_PINCTRL_PIN_PG12 PINCTRL_PIN(PG_BASE + 12, "PG12")
-#define SUNXI_PINCTRL_PIN_PG13 PINCTRL_PIN(PG_BASE + 13, "PG13")
-#define SUNXI_PINCTRL_PIN_PG14 PINCTRL_PIN(PG_BASE + 14, "PG14")
-#define SUNXI_PINCTRL_PIN_PG15 PINCTRL_PIN(PG_BASE + 15, "PG15")
-#define SUNXI_PINCTRL_PIN_PG16 PINCTRL_PIN(PG_BASE + 16, "PG16")
-#define SUNXI_PINCTRL_PIN_PG17 PINCTRL_PIN(PG_BASE + 17, "PG17")
-#define SUNXI_PINCTRL_PIN_PG18 PINCTRL_PIN(PG_BASE + 18, "PG18")
-#define SUNXI_PINCTRL_PIN_PG19 PINCTRL_PIN(PG_BASE + 19, "PG19")
-#define SUNXI_PINCTRL_PIN_PG20 PINCTRL_PIN(PG_BASE + 20, "PG20")
-#define SUNXI_PINCTRL_PIN_PG21 PINCTRL_PIN(PG_BASE + 21, "PG21")
-#define SUNXI_PINCTRL_PIN_PG22 PINCTRL_PIN(PG_BASE + 22, "PG22")
-#define SUNXI_PINCTRL_PIN_PG23 PINCTRL_PIN(PG_BASE + 23, "PG23")
-#define SUNXI_PINCTRL_PIN_PG24 PINCTRL_PIN(PG_BASE + 24, "PG24")
-#define SUNXI_PINCTRL_PIN_PG25 PINCTRL_PIN(PG_BASE + 25, "PG25")
-#define SUNXI_PINCTRL_PIN_PG26 PINCTRL_PIN(PG_BASE + 26, "PG26")
-#define SUNXI_PINCTRL_PIN_PG27 PINCTRL_PIN(PG_BASE + 27, "PG27")
-#define SUNXI_PINCTRL_PIN_PG28 PINCTRL_PIN(PG_BASE + 28, "PG28")
-#define SUNXI_PINCTRL_PIN_PG29 PINCTRL_PIN(PG_BASE + 29, "PG29")
-#define SUNXI_PINCTRL_PIN_PG30 PINCTRL_PIN(PG_BASE + 30, "PG30")
-#define SUNXI_PINCTRL_PIN_PG31 PINCTRL_PIN(PG_BASE + 31, "PG31")
-
-#define SUNXI_PINCTRL_PIN_PH0  PINCTRL_PIN(PH_BASE + 0, "PH0")
-#define SUNXI_PINCTRL_PIN_PH1  PINCTRL_PIN(PH_BASE + 1, "PH1")
-#define SUNXI_PINCTRL_PIN_PH2  PINCTRL_PIN(PH_BASE + 2, "PH2")
-#define SUNXI_PINCTRL_PIN_PH3  PINCTRL_PIN(PH_BASE + 3, "PH3")
-#define SUNXI_PINCTRL_PIN_PH4  PINCTRL_PIN(PH_BASE + 4, "PH4")
-#define SUNXI_PINCTRL_PIN_PH5  PINCTRL_PIN(PH_BASE + 5, "PH5")
-#define SUNXI_PINCTRL_PIN_PH6  PINCTRL_PIN(PH_BASE + 6, "PH6")
-#define SUNXI_PINCTRL_PIN_PH7  PINCTRL_PIN(PH_BASE + 7, "PH7")
-#define SUNXI_PINCTRL_PIN_PH8  PINCTRL_PIN(PH_BASE + 8, "PH8")
-#define SUNXI_PINCTRL_PIN_PH9  PINCTRL_PIN(PH_BASE + 9, "PH9")
-#define SUNXI_PINCTRL_PIN_PH10 PINCTRL_PIN(PH_BASE + 10, "PH10")
-#define SUNXI_PINCTRL_PIN_PH11 PINCTRL_PIN(PH_BASE + 11, "PH11")
-#define SUNXI_PINCTRL_PIN_PH12 PINCTRL_PIN(PH_BASE + 12, "PH12")
-#define SUNXI_PINCTRL_PIN_PH13 PINCTRL_PIN(PH_BASE + 13, "PH13")
-#define SUNXI_PINCTRL_PIN_PH14 PINCTRL_PIN(PH_BASE + 14, "PH14")
-#define SUNXI_PINCTRL_PIN_PH15 PINCTRL_PIN(PH_BASE + 15, "PH15")
-#define SUNXI_PINCTRL_PIN_PH16 PINCTRL_PIN(PH_BASE + 16, "PH16")
-#define SUNXI_PINCTRL_PIN_PH17 PINCTRL_PIN(PH_BASE + 17, "PH17")
-#define SUNXI_PINCTRL_PIN_PH18 PINCTRL_PIN(PH_BASE + 18, "PH18")
-#define SUNXI_PINCTRL_PIN_PH19 PINCTRL_PIN(PH_BASE + 19, "PH19")
-#define SUNXI_PINCTRL_PIN_PH20 PINCTRL_PIN(PH_BASE + 20, "PH20")
-#define SUNXI_PINCTRL_PIN_PH21 PINCTRL_PIN(PH_BASE + 21, "PH21")
-#define SUNXI_PINCTRL_PIN_PH22 PINCTRL_PIN(PH_BASE + 22, "PH22")
-#define SUNXI_PINCTRL_PIN_PH23 PINCTRL_PIN(PH_BASE + 23, "PH23")
-#define SUNXI_PINCTRL_PIN_PH24 PINCTRL_PIN(PH_BASE + 24, "PH24")
-#define SUNXI_PINCTRL_PIN_PH25 PINCTRL_PIN(PH_BASE + 25, "PH25")
-#define SUNXI_PINCTRL_PIN_PH26 PINCTRL_PIN(PH_BASE + 26, "PH26")
-#define SUNXI_PINCTRL_PIN_PH27 PINCTRL_PIN(PH_BASE + 27, "PH27")
-#define SUNXI_PINCTRL_PIN_PH28 PINCTRL_PIN(PH_BASE + 28, "PH28")
-#define SUNXI_PINCTRL_PIN_PH29 PINCTRL_PIN(PH_BASE + 29, "PH29")
-#define SUNXI_PINCTRL_PIN_PH30 PINCTRL_PIN(PH_BASE + 30, "PH30")
-#define SUNXI_PINCTRL_PIN_PH31 PINCTRL_PIN(PH_BASE + 31, "PH31")
-
-#define SUNXI_PINCTRL_PIN_PI0  PINCTRL_PIN(PI_BASE + 0, "PI0")
-#define SUNXI_PINCTRL_PIN_PI1  PINCTRL_PIN(PI_BASE + 1, "PI1")
-#define SUNXI_PINCTRL_PIN_PI2  PINCTRL_PIN(PI_BASE + 2, "PI2")
-#define SUNXI_PINCTRL_PIN_PI3  PINCTRL_PIN(PI_BASE + 3, "PI3")
-#define SUNXI_PINCTRL_PIN_PI4  PINCTRL_PIN(PI_BASE + 4, "PI4")
-#define SUNXI_PINCTRL_PIN_PI5  PINCTRL_PIN(PI_BASE + 5, "PI5")
-#define SUNXI_PINCTRL_PIN_PI6  PINCTRL_PIN(PI_BASE + 6, "PI6")
-#define SUNXI_PINCTRL_PIN_PI7  PINCTRL_PIN(PI_BASE + 7, "PI7")
-#define SUNXI_PINCTRL_PIN_PI8  PINCTRL_PIN(PI_BASE + 8, "PI8")
-#define SUNXI_PINCTRL_PIN_PI9  PINCTRL_PIN(PI_BASE + 9, "PI9")
-#define SUNXI_PINCTRL_PIN_PI10 PINCTRL_PIN(PI_BASE + 10, "PI10")
-#define SUNXI_PINCTRL_PIN_PI11 PINCTRL_PIN(PI_BASE + 11, "PI11")
-#define SUNXI_PINCTRL_PIN_PI12 PINCTRL_PIN(PI_BASE + 12, "PI12")
-#define SUNXI_PINCTRL_PIN_PI13 PINCTRL_PIN(PI_BASE + 13, "PI13")
-#define SUNXI_PINCTRL_PIN_PI14 PINCTRL_PIN(PI_BASE + 14, "PI14")
-#define SUNXI_PINCTRL_PIN_PI15 PINCTRL_PIN(PI_BASE + 15, "PI15")
-#define SUNXI_PINCTRL_PIN_PI16 PINCTRL_PIN(PI_BASE + 16, "PI16")
-#define SUNXI_PINCTRL_PIN_PI17 PINCTRL_PIN(PI_BASE + 17, "PI17")
-#define SUNXI_PINCTRL_PIN_PI18 PINCTRL_PIN(PI_BASE + 18, "PI18")
-#define SUNXI_PINCTRL_PIN_PI19 PINCTRL_PIN(PI_BASE + 19, "PI19")
-#define SUNXI_PINCTRL_PIN_PI20 PINCTRL_PIN(PI_BASE + 20, "PI20")
-#define SUNXI_PINCTRL_PIN_PI21 PINCTRL_PIN(PI_BASE + 21, "PI21")
-#define SUNXI_PINCTRL_PIN_PI22 PINCTRL_PIN(PI_BASE + 22, "PI22")
-#define SUNXI_PINCTRL_PIN_PI23 PINCTRL_PIN(PI_BASE + 23, "PI23")
-#define SUNXI_PINCTRL_PIN_PI24 PINCTRL_PIN(PI_BASE + 24, "PI24")
-#define SUNXI_PINCTRL_PIN_PI25 PINCTRL_PIN(PI_BASE + 25, "PI25")
-#define SUNXI_PINCTRL_PIN_PI26 PINCTRL_PIN(PI_BASE + 26, "PI26")
-#define SUNXI_PINCTRL_PIN_PI27 PINCTRL_PIN(PI_BASE + 27, "PI27")
-#define SUNXI_PINCTRL_PIN_PI28 PINCTRL_PIN(PI_BASE + 28, "PI28")
-#define SUNXI_PINCTRL_PIN_PI29 PINCTRL_PIN(PI_BASE + 29, "PI29")
-#define SUNXI_PINCTRL_PIN_PI30 PINCTRL_PIN(PI_BASE + 30, "PI30")
-#define SUNXI_PINCTRL_PIN_PI31 PINCTRL_PIN(PI_BASE + 31, "PI31")
-
-#define SUNXI_PINCTRL_PIN_PL0  PINCTRL_PIN(PL_BASE + 0, "PL0")
-#define SUNXI_PINCTRL_PIN_PL1  PINCTRL_PIN(PL_BASE + 1, "PL1")
-#define SUNXI_PINCTRL_PIN_PL2  PINCTRL_PIN(PL_BASE + 2, "PL2")
-#define SUNXI_PINCTRL_PIN_PL3  PINCTRL_PIN(PL_BASE + 3, "PL3")
-#define SUNXI_PINCTRL_PIN_PL4  PINCTRL_PIN(PL_BASE + 4, "PL4")
-#define SUNXI_PINCTRL_PIN_PL5  PINCTRL_PIN(PL_BASE + 5, "PL5")
-#define SUNXI_PINCTRL_PIN_PL6  PINCTRL_PIN(PL_BASE + 6, "PL6")
-#define SUNXI_PINCTRL_PIN_PL7  PINCTRL_PIN(PL_BASE + 7, "PL7")
-#define SUNXI_PINCTRL_PIN_PL8  PINCTRL_PIN(PL_BASE + 8, "PL8")
-#define SUNXI_PINCTRL_PIN_PL9  PINCTRL_PIN(PL_BASE + 9, "PL9")
-#define SUNXI_PINCTRL_PIN_PL10 PINCTRL_PIN(PL_BASE + 10, "PL10")
-#define SUNXI_PINCTRL_PIN_PL11 PINCTRL_PIN(PL_BASE + 11, "PL11")
-#define SUNXI_PINCTRL_PIN_PL12 PINCTRL_PIN(PL_BASE + 12, "PL12")
-#define SUNXI_PINCTRL_PIN_PL13 PINCTRL_PIN(PL_BASE + 13, "PL13")
-#define SUNXI_PINCTRL_PIN_PL14 PINCTRL_PIN(PL_BASE + 14, "PL14")
-#define SUNXI_PINCTRL_PIN_PL15 PINCTRL_PIN(PL_BASE + 15, "PL15")
-#define SUNXI_PINCTRL_PIN_PL16 PINCTRL_PIN(PL_BASE + 16, "PL16")
-#define SUNXI_PINCTRL_PIN_PL17 PINCTRL_PIN(PL_BASE + 17, "PL17")
-#define SUNXI_PINCTRL_PIN_PL18 PINCTRL_PIN(PL_BASE + 18, "PL18")
-#define SUNXI_PINCTRL_PIN_PL19 PINCTRL_PIN(PL_BASE + 19, "PL19")
-#define SUNXI_PINCTRL_PIN_PL20 PINCTRL_PIN(PL_BASE + 20, "PL20")
-#define SUNXI_PINCTRL_PIN_PL21 PINCTRL_PIN(PL_BASE + 21, "PL21")
-#define SUNXI_PINCTRL_PIN_PL22 PINCTRL_PIN(PL_BASE + 22, "PL22")
-#define SUNXI_PINCTRL_PIN_PL23 PINCTRL_PIN(PL_BASE + 23, "PL23")
-#define SUNXI_PINCTRL_PIN_PL24 PINCTRL_PIN(PL_BASE + 24, "PL24")
-#define SUNXI_PINCTRL_PIN_PL25 PINCTRL_PIN(PL_BASE + 25, "PL25")
-#define SUNXI_PINCTRL_PIN_PL26 PINCTRL_PIN(PL_BASE + 26, "PL26")
-#define SUNXI_PINCTRL_PIN_PL27 PINCTRL_PIN(PL_BASE + 27, "PL27")
-#define SUNXI_PINCTRL_PIN_PL28 PINCTRL_PIN(PL_BASE + 28, "PL28")
-#define SUNXI_PINCTRL_PIN_PL29 PINCTRL_PIN(PL_BASE + 29, "PL29")
-#define SUNXI_PINCTRL_PIN_PL30 PINCTRL_PIN(PL_BASE + 30, "PL30")
-#define SUNXI_PINCTRL_PIN_PL31 PINCTRL_PIN(PL_BASE + 31, "PL31")
-
-#define SUNXI_PINCTRL_PIN_PM0  PINCTRL_PIN(PM_BASE + 0, "PM0")
-#define SUNXI_PINCTRL_PIN_PM1  PINCTRL_PIN(PM_BASE + 1, "PM1")
-#define SUNXI_PINCTRL_PIN_PM2  PINCTRL_PIN(PM_BASE + 2, "PM2")
-#define SUNXI_PINCTRL_PIN_PM3  PINCTRL_PIN(PM_BASE + 3, "PM3")
-#define SUNXI_PINCTRL_PIN_PM4  PINCTRL_PIN(PM_BASE + 4, "PM4")
-#define SUNXI_PINCTRL_PIN_PM5  PINCTRL_PIN(PM_BASE + 5, "PM5")
-#define SUNXI_PINCTRL_PIN_PM6  PINCTRL_PIN(PM_BASE + 6, "PM6")
-#define SUNXI_PINCTRL_PIN_PM7  PINCTRL_PIN(PM_BASE + 7, "PM7")
-#define SUNXI_PINCTRL_PIN_PM8  PINCTRL_PIN(PM_BASE + 8, "PM8")
-#define SUNXI_PINCTRL_PIN_PM9  PINCTRL_PIN(PM_BASE + 9, "PM9")
-#define SUNXI_PINCTRL_PIN_PM10 PINCTRL_PIN(PM_BASE + 10, "PM10")
-#define SUNXI_PINCTRL_PIN_PM11 PINCTRL_PIN(PM_BASE + 11, "PM11")
-#define SUNXI_PINCTRL_PIN_PM12 PINCTRL_PIN(PM_BASE + 12, "PM12")
-#define SUNXI_PINCTRL_PIN_PM13 PINCTRL_PIN(PM_BASE + 13, "PM13")
-#define SUNXI_PINCTRL_PIN_PM14 PINCTRL_PIN(PM_BASE + 14, "PM14")
-#define SUNXI_PINCTRL_PIN_PM15 PINCTRL_PIN(PM_BASE + 15, "PM15")
-#define SUNXI_PINCTRL_PIN_PM16 PINCTRL_PIN(PM_BASE + 16, "PM16")
-#define SUNXI_PINCTRL_PIN_PM17 PINCTRL_PIN(PM_BASE + 17, "PM17")
-#define SUNXI_PINCTRL_PIN_PM18 PINCTRL_PIN(PM_BASE + 18, "PM18")
-#define SUNXI_PINCTRL_PIN_PM19 PINCTRL_PIN(PM_BASE + 19, "PM19")
-#define SUNXI_PINCTRL_PIN_PM20 PINCTRL_PIN(PM_BASE + 20, "PM20")
-#define SUNXI_PINCTRL_PIN_PM21 PINCTRL_PIN(PM_BASE + 21, "PM21")
-#define SUNXI_PINCTRL_PIN_PM22 PINCTRL_PIN(PM_BASE + 22, "PM22")
-#define SUNXI_PINCTRL_PIN_PM23 PINCTRL_PIN(PM_BASE + 23, "PM23")
-#define SUNXI_PINCTRL_PIN_PM24 PINCTRL_PIN(PM_BASE + 24, "PM24")
-#define SUNXI_PINCTRL_PIN_PM25 PINCTRL_PIN(PM_BASE + 25, "PM25")
-#define SUNXI_PINCTRL_PIN_PM26 PINCTRL_PIN(PM_BASE + 26, "PM26")
-#define SUNXI_PINCTRL_PIN_PM27 PINCTRL_PIN(PM_BASE + 27, "PM27")
-#define SUNXI_PINCTRL_PIN_PM28 PINCTRL_PIN(PM_BASE + 28, "PM28")
-#define SUNXI_PINCTRL_PIN_PM29 PINCTRL_PIN(PM_BASE + 29, "PM29")
-#define SUNXI_PINCTRL_PIN_PM30 PINCTRL_PIN(PM_BASE + 30, "PM30")
-#define SUNXI_PINCTRL_PIN_PM31 PINCTRL_PIN(PM_BASE + 31, "PM31")
+#define SUNXI_PINCTRL_PIN(bank, pin)           \
+       PINCTRL_PIN(P ## bank ## _BASE + (pin), "P" #bank #pin)
 
 #define SUNXI_PIN_NAME_MAX_LEN 5