Merge branches 'at91', 'ep93xx', 'iop', 'kprobes', 'ks8695', 'misc', 'msm', 's3c2410...

* at91: (24 commits)
  [ARM] 4615/4: sam926[13]ek buttons updated
  [ARM] 4765/1: [AT91] AT91CAP9A-DK board support
  [ARM] 4764/1: [AT91] AT91CAP9 core support
  [ARM] 4738/1: at91sam9261: Remove udc pullup enabling in board initialisation
  [ARM] 4761/1: [AT91] Board-support for NEW_LEDs
  [ARM] 4760/1: [AT91] SPI CS0 errata on AT91RM9200
  [ARM] 4759/1: [AT91] Buttons on CSB300
  [ARM] 4758/1: [AT91] LEDs
  [ARM] 4757/1: [AT91] UART initialization
  [ARM] 4756/1: [AT91] Makefile cleanup
  [ARM] 4755/1: [AT91] NAND update
  [ARM] 4754/1: [AT91] SSC library support
  [ARM] 4753/1: [AT91] Use DMA_BIT_MASK
  [ARM] 4752/1: [AT91] RTT, RTC and WDT peripherals on SAM9
  [ARM] 4751/1: [AT91] ISI peripheral on SAM9263
  [ARM] 4750/1: [AT91] STN LCD displays on SAM9261
  [ARM] 4734/1: at91sam9263ek: include IRQ for Ethernet PHY
  [ARM] 4646/1: AT91: configurable HZ, default to 128
  [ARM] 4688/1: at91: speed-up irq processing
  [ARM] 4657/1: AT91: Header definition update
  ...

* ep93xx:
  [ARM] 4671/1: ep93xx: remove obsolete gpio_line_* operations
  [ARM] 4670/1: ep93xx: implement IRQT_BOTHEDGE gpio irq sense type
  [ARM] 4669/1: ep93xx: simplify GPIO code and cleanups
  [ARM] 4668/1: ep93xx: implement new GPIO API

* iop:
  [ARM] 4770/1: GLAN Tank: correct physmap_flash_data width field
  [ARM] 4732/1: GLAN Tank: register rtc-rs5c372 i2c device
  [ARM] 4708/1: iop: update defconfigs for 2.6.24

* kprobes:
  ARM kprobes: let's enable it
  ARM kprobes: special hook for the kprobes breakpoint handler
  ARM kprobes: prevent some functions involved with kprobes from being probed
  ARM kprobes: don't let a single-stepped stmdb corrupt the exception stack
  ARM kprobes: add the kprobes hook to the page fault handler
  ARM kprobes: core code
  ARM kprobes: instruction single-stepping support

* ks8695:
  [ARM] 4603/1: KS8695: debugfs interface to view pin state
  [ARM] 4601/1: KS8695: PCI support

* misc:
  [ARM] remove duplicate includes
  [ARM] CONFIG_DEBUG_STACK_USAGE
  [ARM] 4689/1: small comment wrap fix
  [ARM] 4687/1: Trivial arch/arm/kernel/entry-common.S comment fix
  [ARM] 4666/1: ixp4xx: fix sparse warnings in include/asm-arm/arch-ixp4xx/io.h
  [ARM] remove reference to non-existent MTD_OBSOLETE_CHIPS
  [SERIAL] 21285: Report baud rate back via termios
  [ARM] Remove pointless casts from void pointers,
  [ARM] Misc minor interrupt handler cleanups
  [ARM] Remove at91_lcdc.h
  [ARM] ARRAY_SIZE() cleanup
  [ARM] Update mach-types

* msm:
  [ARM] msm: dma support for MSM7X00A
  [ARM] msm: board file for MACH_HALIBUT (QCT MSM7200A)
  [ARM] msm: irq and timer support for ARCH_MSM7X00A
  [ARM] msm: core platform support for ARCH_MSM7X00A

* s3c2410: (33 commits)
  [ARM] 4795/1: S3C244X: Add armclk and setparent call
  [ARM] 4794/1: S3C24XX: Comonise S3C2440 and S3C2442 clock code
  [ARM] 4793/1: S3C24XX: Add IRQ->GPIO pin mapping function
  [ARM] 4792/1: S3C24XX: Remove warnings from debug-macro.S
  [ARM] 4791/1: S3C2412: Make fclk a parent of msysclk
  [ARM] 4790/1: S3C2412: Fix parent selection for msysclk.
  [ARM] 4789/1: S3C2412: Add missing CLKDIVN register values
  [ARM] 4788/1: S3C24XX: Fix paramet to s3c2410_dma_ctrl if S3C2410_DMAF_AUTOSTART used.
  [ARM] 4787/1: S3C24XX: s3c2410_dma_request() should return the allocated channel number
  [ARM] 4786/1: S3C2412: Add SPI FIFO controll constants
  [ARM] 4785/1: S3C24XX: Add _SHIFT definitions for S3C2410_BANKCON registers
  [ARM] 4784/1: S3C24XX: Fix GPIO restore glitches
  [ARM] 4783/1: S3C24XX: Add s3c2410_gpio_getpull()
  [ARM] 4782/1: S3C24XX: Define FIQ_START for any FIQ users
  [ARM] 4781/1: S3C24XX: DMA suspend and resume support
  [ARM] 4780/1: S3C2412: Allow for seperate DMA channels for TX and RX
  [ARM] 4779/1: S3C2412: Add s3c2412_gpio_set_sleepcfg() call
  [ARM] 4778/1: S3C2412: Add armclk and init from DVS state
  [ARM] 4777/1: S3C24XX: Ensure clk_set_rate() checks the set_rate method for the clk
  [ARM] 4775/1: s3c2410: fix compilation error if only s3c2442 cpu is selected
  ...

* sa1100:
  [ARM] sa1100: add clock source support

* vfp:
  [ARM] 4584/2: ARMv7: Add Advanced SIMD (NEON) extension support
  [ARM] 4583/1: ARMv7: Add VFPv3 support
  [ARM] 4582/2: Add support for the common VFP subarchitecture

diff --cc arch/arm/Kconfig
Simple merge

diff --cc arch/arm/kernel/entry-armv.S
Simple merge

diff --cc arch/arm/mach-ep93xx/core.c
index f1074ff,70b2c78,4cb3f74,70b2c78,70b2c78,70b2c78,f8f001d,70b2c78,70b2c78,70b2c78,70b2c78..91f6a07
--- 1/arch/arm/mach-ep93xx/core.c
--- 2/arch/arm/mach-ep93xx/core.c
--- 3/arch/arm/mach-ep93xx/core.c
--- 4/arch/arm/mach-ep93xx/core.c
--- 5/arch/arm/mach-ep93xx/core.c
--- 6/arch/arm/mach-ep93xx/core.c
--- 7/arch/arm/mach-ep93xx/core.c
--- 8/arch/arm/mach-ep93xx/core.c
--- 9/arch/arm/mach-ep93xx/core.c
--- 10/arch/arm/mach-ep93xx/core.c
--- 11/arch/arm/mach-ep93xx/core.c
+++ b/arch/arm/mach-ep93xx/core.c
@@@@@@@@@@@@ -153,38 -157,38 -158,41 -157,38 -157,38 -157,38 -156,38 -157,38 -157,38 -157,38 -157,38 +153,41 @@@@@@@@@@@@ static unsigned char gpio_int_enabled[3
           static unsigned char gpio_int_type1[3];
           static unsigned char gpio_int_type2[3];
           
-- --------static void update_gpio_int_params(int abf)
++ ++++++++/* Port ordering is: A B F */
++ ++++++++static const u8 int_type1_register_offset[3] = { 0x90, 0xac, 0x4c };
++ ++++++++static const u8 int_type2_register_offset[3] = { 0x94, 0xb0, 0x50 };
++ ++++++++static const u8 eoi_register_offset[3]               = { 0x98, 0xb4, 0x54 };
++ ++++++++static const u8 int_en_register_offset[3]    = { 0x9c, 0xb8, 0x5c };
++ ++++++++
++ ++++++++static void update_gpio_int_params(unsigned port)
           {
-- --------     if (abf == 0) {
-- --------             __raw_writeb(0, EP93XX_GPIO_A_INT_ENABLE);
-- --------             __raw_writeb(gpio_int_type2[0], EP93XX_GPIO_A_INT_TYPE2);
-- --------             __raw_writeb(gpio_int_type1[0], EP93XX_GPIO_A_INT_TYPE1);
-- --------             __raw_writeb(gpio_int_unmasked[0] & gpio_int_enabled[0], EP93XX_GPIO_A_INT_ENABLE);
-- --------     } else if (abf == 1) {
-- --------             __raw_writeb(0, EP93XX_GPIO_B_INT_ENABLE);
-- --------             __raw_writeb(gpio_int_type2[1], EP93XX_GPIO_B_INT_TYPE2);
-- --------             __raw_writeb(gpio_int_type1[1], EP93XX_GPIO_B_INT_TYPE1);
-- --------             __raw_writeb(gpio_int_unmasked[1] & gpio_int_enabled[1], EP93XX_GPIO_B_INT_ENABLE);
-- --------     } else if (abf == 2) {
-- --------             __raw_writeb(0, EP93XX_GPIO_F_INT_ENABLE);
-- --------             __raw_writeb(gpio_int_type2[2], EP93XX_GPIO_F_INT_TYPE2);
-- --------             __raw_writeb(gpio_int_type1[2], EP93XX_GPIO_F_INT_TYPE1);
-- --------             __raw_writeb(gpio_int_unmasked[2] & gpio_int_enabled[2], EP93XX_GPIO_F_INT_ENABLE);
-- --------     } else {
-- --------             BUG();
-- --------     }
-- --------}
++ ++++++++     BUG_ON(port > 2);
++ +++ ++++
++ ++++++++     __raw_writeb(0, EP93XX_GPIO_REG(int_en_register_offset[port]));
 + +++ ++++
      -    static unsigned char data_register_offset[8] = {
      -         0x00, 0x04, 0x08, 0x0c, 0x20, 0x30, 0x38, 0x40,
++ ++++++++     __raw_writeb(gpio_int_type2[port],
++ ++++++++             EP93XX_GPIO_REG(int_type2_register_offset[port]));
      +    
-          static unsigned char data_register_offset[8] = {
-               0x00, 0x04, 0x08, 0x0c, 0x20, 0x30, 0x38, 0x40,
++ ++++++++     __raw_writeb(gpio_int_type1[port],
++ ++++++++             EP93XX_GPIO_REG(int_type1_register_offset[port]));
++ ++++++++
++ ++++++++     __raw_writeb(gpio_int_unmasked[port] & gpio_int_enabled[port],
++ ++++++++             EP93XX_GPIO_REG(int_en_register_offset[port]));
++ ++++++++}
+     +    
 - --- ----static unsigned char data_register_offset[8] = {
 - --- ----     0x00, 0x04, 0x08, 0x0c, 0x20, 0x30, 0x38, 0x40,
++ ++++++++/* Port ordering is: A B F D E C G H */
++ ++++++++static const u8 data_register_offset[8] = {
++ ++++++++     0x00, 0x04, 0x30, 0x0c, 0x20, 0x08, 0x38, 0x40,
           };
           
-- --------static unsigned char data_direction_register_offset[8] = {
-- --------     0x10, 0x14, 0x18, 0x1c, 0x24, 0x34, 0x3c, 0x44,
++ ++++++++static const u8 data_direction_register_offset[8] = {
++ ++++++++     0x10, 0x14, 0x34, 0x1c, 0x24, 0x18, 0x3c, 0x44,
           };
           
-- --------void gpio_line_config(int line, int direction)
++ ++++++++#define GPIO_IN              0
++ ++++++++#define GPIO_OUT     1
++ ++++++++
++ ++++++++static void ep93xx_gpio_set_direction(unsigned line, int direction)
           {
                unsigned int data_direction_register;
                unsigned long flags;

diff --cc arch/arm/mach-omap1/board-osk.c
Simple merge

diff --cc arch/arm/mach-sa1100/time.c
Simple merge

diff --cc arch/arm/mm/Kconfig
Simple merge