+Thu Apr 23 20:21:06 1997 J"orn Rennecke <amylaar@cygnus.co.uk>
+
+ * sh.c (gen_ashift_hi): Implement right shifts via gen_ashift.
+ * sh.md (ashrhi3_k, lshrhi3_k, lshrhi3_m, lshrhi3, lshrhi3+1): Delete.
+
Wed Apr 22 17:07:35 1998 Michael Meissner <meissner@cygnus.com>
* loop.c (note_addr_stored): Correct function to take 2 arguments,
switch (type)
{
case ASHIFTRT:
- emit_insn (gen_ashrhi3_k (reg, reg, GEN_INT (n)));
- break;
case LSHIFTRT:
- if (n == 1)
- emit_insn (gen_lshrhi3_m (reg, reg, GEN_INT (n)));
- else
- emit_insn (gen_lshrhi3_k (reg, reg, GEN_INT (n)));
+ /* We don't have HImode right shift operations because using the
+ ordinary 32 bit shift instructions for that doesn't generate proper
+ zero/sign extension.
+ gen_ashift_hi is only called in contexts where we know that the
+ sign extension works out correctly. */
+ gen_ashift (type, n, gen_rtx_SUBREG (SImode, reg, 0));
break;
case ASHIFT:
emit_insn (gen_ashlhi3_k (reg, reg, GEN_INT (n)));
"shar %0"
[(set_attr "type" "arith")])
-(define_insn "ashrhi3_k"
- [(set (match_operand:HI 0 "arith_reg_operand" "=r")
- (ashiftrt:HI (match_operand:HI 1 "arith_reg_operand" "0")
- (match_operand:HI 2 "const_int_operand" "M")))
- (clobber (reg:SI 18))]
- "INTVAL (operands[2]) == 1"
- "shar %0"
- [(set_attr "type" "arith")])
+;; We can't do HImode right shifts correctly unless we start out with an
+;; explicit zero / sign extension; doing that would result in worse overall
+;; code, so just let the machine independent code widen the mode.
+;; That's why we don't have ashrhi3_k / lshrhi3_k / lshrhi3_m / lshrhi3 .
+
;; ??? This should be a define expand.
"shlr%O2 %0"
[(set_attr "type" "arith")])
-(define_insn "lshrhi3_m"
- [(set (match_operand:HI 0 "arith_reg_operand" "=r")
- (lshiftrt:HI (match_operand:HI 1 "arith_reg_operand" "0")
- (match_operand:HI 2 "const_int_operand" "M")))
- (clobber (reg:SI 18))]
- "CONST_OK_FOR_M (INTVAL (operands[2]))"
- "shlr %0"
- [(set_attr "type" "arith")])
-
-(define_insn "lshrhi3_k"
- [(set (match_operand:HI 0 "arith_reg_operand" "=r")
- (lshiftrt:HI (match_operand:HI 1 "arith_reg_operand" "0")
- (match_operand:HI 2 "const_int_operand" "K")))]
- "CONST_OK_FOR_K (INTVAL (operands[2]))
- && ! CONST_OK_FOR_M (INTVAL (operands[2]))"
- "shlr%O2 %0"
- [(set_attr "type" "arith")])
-
(define_insn "lshrsi3_n"
[(set (match_operand:SI 0 "arith_reg_operand" "=r")
(lshiftrt:SI (match_operand:SI 1 "arith_reg_operand" "0")
FAIL;
}")
-(define_insn "lshrhi3"
- [(set (match_operand:HI 0 "arith_reg_operand" "=r")
- (lshiftrt:HI (match_operand:HI 1 "arith_reg_operand" "0")
- (match_operand:HI 2 "const_int_operand" "n")))
- (clobber (reg:SI 18))]
- ""
- "#"
-;; ??? length attribute is sometimes six instead of four.
- [(set (attr "length")
- (cond [(eq (symbol_ref "shift_insns_rtx (insn)") (const_int 1))
- (const_string "2")
- (eq (symbol_ref "shift_insns_rtx (insn)") (const_int 2))
- (const_string "4")]
- (const_string "6")))
- (set_attr "type" "arith")])
-
-(define_split
- [(set (match_operand:HI 0 "arith_reg_operand" "")
- (lshiftrt:HI (match_operand:HI 1 "arith_reg_operand" "")
- (match_operand:HI 2 "const_int_operand" "n")))
- (clobber (reg:SI 18))]
- ""
- [(use (reg:SI 0))]
- "
-{
- gen_shifty_hi_op (LSHIFTRT, operands);
- DONE;
-}")
-
;; ??? This should be a define expand.
(define_insn "ashldi3_k"