dmaengine: idxd: Correct IAX operation code names
authorFenghua Yu <fenghua.yu@intel.com>
Thu, 7 Jul 2022 00:20:52 +0000 (17:20 -0700)
committerVinod Koul <vkoul@kernel.org>
Thu, 21 Jul 2022 12:40:43 +0000 (18:10 +0530)
Some IAX operation code nomenclatures are misleading or don't match with
others:

1. Operation code 0x4c is Zero Compress 32. IAX_OPCODE_DECOMP_32 is a
   misleading name. Change it to IAX_OPCODE_ZERO_COMP_32.
2. Operation code 0x4d is Zero Compress 16. IAX_OPCODE_DECOMP_16 is a
   misleading name. Change it to IAX_OPCODE_ZERO_COMP_16.
3. IAX_OPCDE_FIND_UNIQUE is corrected to match with other nomenclatures.

Co-developed-by: Li Zhang <li4.zhang@intel.com>
Signed-off-by: Li Zhang <li4.zhang@intel.com>
Signed-off-by: Fenghua Yu <fenghua.yu@intel.com>
Reviewed-by: Dave Jiang <dave.jiang@intel.com>
Link: https://lore.kernel.org/r/20220707002052.1546361-1-fenghua.yu@intel.com
Signed-off-by: Vinod Koul <vkoul@kernel.org>
include/uapi/linux/idxd.h

index bce7c43..095299c 100644 (file)
@@ -89,14 +89,14 @@ enum iax_opcode {
        IAX_OPCODE_CRC64,
        IAX_OPCODE_ZERO_DECOMP_32 = 0x48,
        IAX_OPCODE_ZERO_DECOMP_16,
-       IAX_OPCODE_DECOMP_32 = 0x4c,
-       IAX_OPCODE_DECOMP_16,
+       IAX_OPCODE_ZERO_COMP_32 = 0x4c,
+       IAX_OPCODE_ZERO_COMP_16,
        IAX_OPCODE_SCAN = 0x50,
        IAX_OPCODE_SET_MEMBER,
        IAX_OPCODE_EXTRACT,
        IAX_OPCODE_SELECT,
        IAX_OPCODE_RLE_BURST,
-       IAX_OPCDE_FIND_UNIQUE,
+       IAX_OPCODE_FIND_UNIQUE,
        IAX_OPCODE_EXPAND,
 };