+; NOTE: Assertions have been autogenerated by utils/update_test_checks.py
; RUN: opt < %s -instsimplify -S | FileCheck %s
+define i32 @zero_dividend(i32 %A) {
+; CHECK-LABEL: @zero_dividend(
+; CHECK-NEXT: ret i32 0
+;
+ %B = sdiv i32 0, %A
+ ret i32 %B
+}
+
+define <2 x i32> @zero_dividend_vector(<2 x i32> %A) {
+; CHECK-LABEL: @zero_dividend_vector(
+; CHECK-NEXT: ret <2 x i32> zeroinitializer
+;
+ %B = udiv <2 x i32> zeroinitializer, %A
+ ret <2 x i32> %B
+}
+
+define <2 x i32> @zero_dividend_vector_undef_elt(<2 x i32> %A) {
+; CHECK-LABEL: @zero_dividend_vector_undef_elt(
+; CHECK-NEXT: [[B:%.*]] = sdiv <2 x i32> <i32 0, i32 undef>, [[A:%.*]]
+; CHECK-NEXT: ret <2 x i32> [[B]]
+;
+ %B = sdiv <2 x i32> <i32 0, i32 undef>, %A
+ ret <2 x i32> %B
+}
+
; Division-by-zero is undef. UB in any vector lane means the whole op is undef.
define <2 x i8> @sdiv_zero_elt_vec_constfold(<2 x i8> %x) {
define <2 x i1> @sdiv_bool_vec(<2 x i1> %x, <2 x i1> %y) {
; CHECK-LABEL: @sdiv_bool_vec(
-; CHECK-NEXT: ret <2 x i1> %x
+; CHECK-NEXT: ret <2 x i1> [[X:%.*]]
;
%div = sdiv <2 x i1> %x, %y
ret <2 x i1> %div
define <2 x i1> @udiv_bool_vec(<2 x i1> %x, <2 x i1> %y) {
; CHECK-LABEL: @udiv_bool_vec(
-; CHECK-NEXT: ret <2 x i1> %x
+; CHECK-NEXT: ret <2 x i1> [[X:%.*]]
;
%div = udiv <2 x i1> %x, %y
ret <2 x i1> %div
define i32 @not_udiv_dividend_known_smaller_than_constant_divisor(i32 %x) {
; CHECK-LABEL: @not_udiv_dividend_known_smaller_than_constant_divisor(
-; CHECK-NEXT: [[AND:%.*]] = and i32 %x, 251
+; CHECK-NEXT: [[AND:%.*]] = and i32 [[X:%.*]], 251
; CHECK-NEXT: [[DIV:%.*]] = udiv i32 [[AND]], 251
; CHECK-NEXT: ret i32 [[DIV]]
;
define i32 @not_udiv_constant_dividend_known_smaller_than_divisor(i32 %x) {
; CHECK-LABEL: @not_udiv_constant_dividend_known_smaller_than_divisor(
-; CHECK-NEXT: [[OR:%.*]] = or i32 %x, 251
+; CHECK-NEXT: [[OR:%.*]] = or i32 [[X:%.*]], 251
; CHECK-NEXT: [[DIV:%.*]] = udiv i32 251, [[OR]]
; CHECK-NEXT: ret i32 [[DIV]]
;
define i32 @udiv_dividend_known_smaller_than_divisor(i32 %x, i32 %y) {
; CHECK-LABEL: @udiv_dividend_known_smaller_than_divisor(
-; CHECK-NEXT: [[AND:%.*]] = and i32 %x, 250
-; CHECK-NEXT: [[OR:%.*]] = or i32 %y, 251
+; CHECK-NEXT: [[AND:%.*]] = and i32 [[X:%.*]], 250
+; CHECK-NEXT: [[OR:%.*]] = or i32 [[Y:%.*]], 251
; CHECK-NEXT: [[DIV:%.*]] = udiv i32 [[AND]], [[OR]]
; CHECK-NEXT: ret i32 [[DIV]]
;
define i32 @not_udiv_dividend_known_smaller_than_divisor(i32 %x, i32 %y) {
; CHECK-LABEL: @not_udiv_dividend_known_smaller_than_divisor(
-; CHECK-NEXT: [[AND:%.*]] = and i32 %x, 251
-; CHECK-NEXT: [[OR:%.*]] = or i32 %y, 251
+; CHECK-NEXT: [[AND:%.*]] = and i32 [[X:%.*]], 251
+; CHECK-NEXT: [[OR:%.*]] = or i32 [[Y:%.*]], 251
; CHECK-NEXT: [[DIV:%.*]] = udiv i32 [[AND]], [[OR]]
; CHECK-NEXT: ret i32 [[DIV]]
;
ret <2 x i32> %neg
}
+define <2 x i32> @negate_nuw_vec_undef_elt(<2 x i32> %x) {
+; CHECK-LABEL: @negate_nuw_vec_undef_elt(
+; CHECK-NEXT: [[NEG:%.*]] = sub nuw <2 x i32> <i32 0, i32 undef>, [[X:%.*]]
+; CHECK-NEXT: ret <2 x i32> [[NEG]]
+;
+ %neg = sub nuw <2 x i32> <i32 0, i32 undef>, %x
+ ret <2 x i32> %neg
+}
+
define i8 @negate_zero_or_minsigned_nsw(i8 %x) {
; CHECK-LABEL: @negate_zero_or_minsigned_nsw(
; CHECK-NEXT: ret i8 0
ret <2 x i8> %neg
}
+define <2 x i8> @negate_zero_or_minsigned_nsw_vec_undef_elt(<2 x i8> %x) {
+; CHECK-LABEL: @negate_zero_or_minsigned_nsw_vec_undef_elt(
+; CHECK-NEXT: [[SIGNBIT:%.*]] = shl <2 x i8> [[X:%.*]], <i8 7, i8 7>
+; CHECK-NEXT: [[NEG:%.*]] = sub nsw <2 x i8> <i8 undef, i8 0>, [[SIGNBIT]]
+; CHECK-NEXT: ret <2 x i8> [[NEG]]
+;
+ %signbit = shl <2 x i8> %x, <i8 7, i8 7>
+ %neg = sub nsw <2 x i8> <i8 undef, i8 0>, %signbit
+ ret <2 x i8> %neg
+}
+
define i8 @negate_zero_or_minsigned(i8 %x) {
; CHECK-LABEL: @negate_zero_or_minsigned(
-; CHECK-NEXT: [[SIGNBIT:%.*]] = shl i8 %x, 7
+; CHECK-NEXT: [[SIGNBIT:%.*]] = shl i8 [[X:%.*]], 7
; CHECK-NEXT: ret i8 [[SIGNBIT]]
;
%signbit = shl i8 %x, 7
define <2 x i8> @negate_zero_or_minsigned_vec(<2 x i8> %x) {
; CHECK-LABEL: @negate_zero_or_minsigned_vec(
-; CHECK-NEXT: [[SIGNBIT:%.*]] = and <2 x i8> %x, <i8 -128, i8 -128>
+; CHECK-NEXT: [[SIGNBIT:%.*]] = and <2 x i8> [[X:%.*]], <i8 -128, i8 -128>
; CHECK-NEXT: ret <2 x i8> [[SIGNBIT]]
;
%signbit = and <2 x i8> %x, <i8 128, i8 128>
; NOTE: Assertions have been autogenerated by utils/update_test_checks.py
; RUN: opt < %s -instsimplify -S | FileCheck %s
+define i32 @zero_dividend(i32 %A) {
+; CHECK-LABEL: @zero_dividend(
+; CHECK-NEXT: ret i32 0
+;
+ %B = urem i32 0, %A
+ ret i32 %B
+}
+
+define <2 x i32> @zero_dividend_vector(<2 x i32> %A) {
+; CHECK-LABEL: @zero_dividend_vector(
+; CHECK-NEXT: ret <2 x i32> zeroinitializer
+;
+ %B = srem <2 x i32> zeroinitializer, %A
+ ret <2 x i32> %B
+}
+
+define <2 x i32> @zero_dividend_vector_undef_elt(<2 x i32> %A) {
+; CHECK-LABEL: @zero_dividend_vector_undef_elt(
+; CHECK-NEXT: [[B:%.*]] = urem <2 x i32> <i32 undef, i32 0>, [[A:%.*]]
+; CHECK-NEXT: ret <2 x i32> [[B]]
+;
+ %B = urem <2 x i32> <i32 undef, i32 0>, %A
+ ret <2 x i32> %B
+}
+
; Division-by-zero is undef. UB in any vector lane means the whole op is undef.
define <2 x i8> @srem_zero_elt_vec_constfold(<2 x i8> %x) {