drm/msm/dpu: remove display H_TILE from encoder

Encoder H_TILE values are not used for allocating the hw blocks.
no. of hw_intf blocks provides the info.

changes in v4:
	- remove irrelevant changes (Sean)
	- retain log macros (Sean)
changes in v5:
	- none

Signed-off-by: Jeykumar Sankaran <jsanka@codeaurora.org>
Reviewed-by: Sean Paul <seanpaul@chromium.org>
Signed-off-by: Sean Paul <seanpaul@chromium.org>
Signed-off-by: Rob Clark <robdclark@gmail.com>

diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c
index 0454e94..0d43525 100644 (file)
--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c
+++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c
@@ -175,8 +175,6 @@ struct dpu_encoder_virt {
        spinlock_t enc_spinlock;
        uint32_t bus_scaling_client;
 
-       uint32_t display_num_of_h_tiles;
-
        unsigned int num_phys_encs;
        struct dpu_encoder_phys *phys_encs[MAX_PHYS_ENCODERS_PER_VIRTUAL];
        struct dpu_encoder_phys *cur_master;
@@ -455,7 +453,6 @@ void dpu_encoder_get_hw_resources(struct drm_encoder *drm_enc,
 
        /* Query resources used by phys encs, expected to be without overlap */
        memset(hw_res, 0, sizeof(*hw_res));
-       hw_res->display_num_of_h_tiles = dpu_enc->display_num_of_h_tiles;
 
        for (i = 0; i < dpu_enc->num_phys_encs; i++) {
                struct dpu_encoder_phys *phys = dpu_enc->phys_encs[i];
@@ -2104,8 +2101,6 @@ static int dpu_encoder_setup_display(struct dpu_encoder_virt *dpu_enc,
 
        WARN_ON(disp_info->num_of_h_tiles < 1);
 
-       dpu_enc->display_num_of_h_tiles = disp_info->num_of_h_tiles;
-
        DPU_DEBUG("dsi_info->num_of_h_tiles %d\n", disp_info->num_of_h_tiles);
 
        if ((disp_info->capabilities & MSM_DISPLAY_CAP_CMD_MODE) ||

diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.h b/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.h
index ff064e3..f109b4d 100644 (file)
--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.h
+++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.h
@@ -32,13 +32,10 @@
 /**
  * Encoder functions and data types
  * @intfs:     Interfaces this encoder is using, INTF_MODE_NONE if unused
- * @display_num_of_h_tiles: Number of horizontal tiles in case of split
- *                          interface
  * @topology:   Topology of the display
  */
 struct dpu_encoder_hw_resources {
        enum dpu_intf_mode intfs[INTF_MAX];
-       u32 display_num_of_h_tiles;
 };
 
 /**

diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_rm.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_rm.c
index 42751ba..86466f0 100644 (file)
--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_rm.c
+++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_rm.c
@@ -751,7 +751,6 @@ static int _dpu_rm_populate_requirements(
                return -EINVAL;
        }
 
-       DRM_DEBUG_KMS("num_h_tiles: %d\n", reqs->hw_res.display_num_of_h_tiles);
        DRM_DEBUG_KMS("num_lm: %d num_ctl: %d topology: %d split_display: %d\n",
                      reqs->topology->num_lm, reqs->topology->num_ctl,
                      reqs->topology->top_name,