drm/amd/amdgpu: expose fragment size as module parameter (v2)
authorRoger He <Hongbo.He@amd.com>
Tue, 15 Aug 2017 08:05:59 +0000 (16:05 +0800)
committerAlex Deucher <alexander.deucher@amd.com>
Thu, 17 Aug 2017 20:47:43 +0000 (16:47 -0400)
Allow overrides on the command line.

v2: agd: sqaush in spelling fix and bogus default value warning

Reviewed-by: Christian König <christian.koenig@amd.com>
Signed-off-by: Roger He <Hongbo.He@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
drivers/gpu/drm/amd/amdgpu/amdgpu.h
drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c
drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c
drivers/gpu/drm/amd/amdgpu/amdgpu_vm.h
drivers/gpu/drm/amd/amdgpu/gmc_v6_0.c
drivers/gpu/drm/amd/amdgpu/gmc_v7_0.c
drivers/gpu/drm/amd/amdgpu/gmc_v8_0.c
drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c

index 1f915a5..12e71bb 100644 (file)
@@ -96,6 +96,7 @@ extern int amdgpu_bapm;
 extern int amdgpu_deep_color;
 extern int amdgpu_vm_size;
 extern int amdgpu_vm_block_size;
+extern int amdgpu_vm_fragment_size;
 extern int amdgpu_vm_fault_stop;
 extern int amdgpu_vm_debug;
 extern int amdgpu_vm_update_mode;
index a6f6cb0..1a459ac 100644 (file)
@@ -1076,6 +1076,13 @@ static void amdgpu_check_arguments(struct amdgpu_device *adev)
                amdgpu_gtt_size = -1;
        }
 
+       /* valid range is between 4 and 9 inclusive */
+       if (amdgpu_vm_fragment_size != -1 &&
+           (amdgpu_vm_fragment_size > 9 || amdgpu_vm_fragment_size < 4)) {
+               dev_warn(adev->dev, "valid range is between 4 and 9\n");
+               amdgpu_vm_fragment_size = -1;
+       }
+
        amdgpu_check_vm_size(adev);
 
        amdgpu_check_block_size(adev);
index 5e9ce8a..353e346 100644 (file)
@@ -94,6 +94,7 @@ unsigned amdgpu_ip_block_mask = 0xffffffff;
 int amdgpu_bapm = -1;
 int amdgpu_deep_color = 0;
 int amdgpu_vm_size = -1;
+int amdgpu_vm_fragment_size = -1;
 int amdgpu_vm_block_size = -1;
 int amdgpu_vm_fault_stop = 0;
 int amdgpu_vm_debug = 0;
@@ -183,6 +184,9 @@ module_param_named(deep_color, amdgpu_deep_color, int, 0444);
 MODULE_PARM_DESC(vm_size, "VM address space size in gigabytes (default 64GB)");
 module_param_named(vm_size, amdgpu_vm_size, int, 0444);
 
+MODULE_PARM_DESC(vm_fragment_size, "VM fragment size in bits (4, 5, etc. 4 = 64K (default), Max 9 = 2M)");
+module_param_named(vm_fragment_size, amdgpu_vm_fragment_size, int, 0444);
+
 MODULE_PARM_DESC(vm_block_size, "VM page table size in bits (default depending on vm_size)");
 module_param_named(vm_block_size, amdgpu_vm_block_size, int, 0444);
 
index efac05d..6b1343e 100644 (file)
@@ -2413,12 +2413,26 @@ static uint32_t amdgpu_vm_get_block_size(uint64_t vm_size)
 }
 
 /**
- * amdgpu_vm_adjust_size - adjust vm size and block size
+ * amdgpu_vm_set_fragment_size - adjust fragment size in PTE
+ *
+ * @adev: amdgpu_device pointer
+ * @fragment_size_default: the default fragment size if it's set auto
+ */
+void amdgpu_vm_set_fragment_size(struct amdgpu_device *adev, uint32_t fragment_size_default)
+{
+       if (amdgpu_vm_fragment_size == -1)
+               adev->vm_manager.fragment_size = fragment_size_default;
+       else
+               adev->vm_manager.fragment_size = amdgpu_vm_fragment_size;
+}
+
+/**
+ * amdgpu_vm_adjust_size - adjust vm size, block size and fragment size
  *
  * @adev: amdgpu_device pointer
  * @vm_size: the default vm size if it's set auto
  */
-void amdgpu_vm_adjust_size(struct amdgpu_device *adev, uint64_t vm_size)
+void amdgpu_vm_adjust_size(struct amdgpu_device *adev, uint64_t vm_size, uint32_t fragment_size_default)
 {
        /* adjust vm size firstly */
        if (amdgpu_vm_size == -1)
@@ -2433,8 +2447,11 @@ void amdgpu_vm_adjust_size(struct amdgpu_device *adev, uint64_t vm_size)
        else
                adev->vm_manager.block_size = amdgpu_vm_block_size;
 
-       DRM_INFO("vm size is %llu GB, block size is %u-bit\n",
-               adev->vm_manager.vm_size, adev->vm_manager.block_size);
+       amdgpu_vm_set_fragment_size(adev, fragment_size_default);
+
+       DRM_INFO("vm size is %llu GB, block size is %u-bit, fragment size is %u-bit\n",
+               adev->vm_manager.vm_size, adev->vm_manager.block_size,
+               adev->vm_manager.fragment_size);
 }
 
 /**
index 45a2769..ba6691b 100644 (file)
@@ -271,7 +271,10 @@ int amdgpu_vm_bo_clear_mappings(struct amdgpu_device *adev,
                                uint64_t saddr, uint64_t size);
 void amdgpu_vm_bo_rmv(struct amdgpu_device *adev,
                      struct amdgpu_bo_va *bo_va);
-void amdgpu_vm_adjust_size(struct amdgpu_device *adev, uint64_t vm_size);
+void amdgpu_vm_set_fragment_size(struct amdgpu_device *adev,
+                               uint32_t fragment_size_default);
+void amdgpu_vm_adjust_size(struct amdgpu_device *adev, uint64_t vm_size,
+                               uint32_t fragment_size_default);
 int amdgpu_vm_ioctl(struct drm_device *dev, void *data, struct drm_file *filp);
 bool amdgpu_vm_need_pipeline_sync(struct amdgpu_ring *ring,
                                  struct amdgpu_job *job);
index 2db5c71..12b0c4c 100644 (file)
@@ -814,8 +814,7 @@ static int gmc_v6_0_sw_init(void *handle)
        if (r)
                return r;
 
-       amdgpu_vm_adjust_size(adev, 64);
-       adev->vm_manager.fragment_size = 4;
+       amdgpu_vm_adjust_size(adev, 64, 4);
        adev->vm_manager.max_pfn = adev->vm_manager.vm_size << 18;
 
        adev->mc.mc_mask = 0xffffffffffULL;
index 8ffdad9..e42c1ad 100644 (file)
@@ -950,8 +950,7 @@ static int gmc_v7_0_sw_init(void *handle)
         * Currently set to 4GB ((1 << 20) 4k pages).
         * Max GPUVM size for cayman and SI is 40 bits.
         */
-       amdgpu_vm_adjust_size(adev, 64);
-       adev->vm_manager.fragment_size = 4;
+       amdgpu_vm_adjust_size(adev, 64, 4);
        adev->vm_manager.max_pfn = adev->vm_manager.vm_size << 18;
 
        /* Set the internal MC address mask
index a13f661..7ca2dae 100644 (file)
@@ -1048,8 +1048,7 @@ static int gmc_v8_0_sw_init(void *handle)
         * Currently set to 4GB ((1 << 20) 4k pages).
         * Max GPUVM size for cayman and SI is 40 bits.
         */
-       amdgpu_vm_adjust_size(adev, 64);
-       adev->vm_manager.fragment_size = 4;
+       amdgpu_vm_adjust_size(adev, 64, 4);
        adev->vm_manager.max_pfn = adev->vm_manager.vm_size << 18;
 
        /* Set the internal MC address mask
index f721b4f..2769c2b 100644 (file)
@@ -541,12 +541,11 @@ static int gmc_v9_0_sw_init(void *handle)
                        adev->vm_manager.vm_size = 1U << 18;
                        adev->vm_manager.block_size = 9;
                        adev->vm_manager.num_level = 3;
-                       adev->vm_manager.fragment_size = 9;
+                       amdgpu_vm_set_fragment_size(adev, 9);
                } else {
-                       /* vm_size is 64GB for legacy 2-level page support*/
-                       amdgpu_vm_adjust_size(adev, 64);
+                       /* vm_size is 64GB for legacy 2-level page support */
+                       amdgpu_vm_adjust_size(adev, 64, 9);
                        adev->vm_manager.num_level = 1;
-                       adev->vm_manager.fragment_size = 9;
                }
                break;
        case CHIP_VEGA10:
@@ -560,7 +559,7 @@ static int gmc_v9_0_sw_init(void *handle)
                adev->vm_manager.vm_size = 1U << 18;
                adev->vm_manager.block_size = 9;
                adev->vm_manager.num_level = 3;
-               adev->vm_manager.fragment_size = 9;
+               amdgpu_vm_set_fragment_size(adev, 9);
                break;
        default:
                break;