radv_dispatch(struct radv_cmd_buffer *cmd_buffer, const struct radv_dispatch_info *info,
struct radv_compute_pipeline *pipeline, VkPipelineBindPoint bind_point)
{
+ struct radv_shader *compute_shader = pipeline->base.shaders[MESA_SHADER_COMPUTE];
bool has_prefetch = cmd_buffer->device->physical_device->rad_info.gfx_level >= GFX7;
bool pipeline_is_dirty = pipeline != cmd_buffer->state.emitted_compute_pipeline;
- if (pipeline->cs_regalloc_hang_bug)
+ if (compute_shader->info.cs.regalloc_hang_bug)
cmd_buffer->state.flush_bits |= RADV_CMD_FLAG_PS_PARTIAL_FLUSH |
RADV_CMD_FLAG_CS_PARTIAL_FLUSH;
: VK_PIPELINE_BIND_POINT_COMPUTE);
}
- if (pipeline->cs_regalloc_hang_bug)
+ if (compute_shader->info.cs.regalloc_hang_bug)
cmd_buffer->state.flush_bits |= RADV_CMD_FLAG_CS_PARTIAL_FLUSH;
radv_cmd_buffer_after_draw(cmd_buffer, RADV_CMD_FLAG_CS_PARTIAL_FLUSH);
pipeline->base.shader_upload_seq = pipeline->base.shaders[MESA_SHADER_COMPUTE]->upload_seq;
- if (device->physical_device->rad_info.has_cs_regalloc_hang_bug) {
- struct radv_shader *compute_shader = pipeline->base.shaders[MESA_SHADER_COMPUTE];
- unsigned *cs_block_size = compute_shader->info.cs.block_size;
-
- pipeline->cs_regalloc_hang_bug = cs_block_size[0] * cs_block_size[1] * cs_block_size[2] > 256;
- }
-
radv_compute_generate_pm4(pipeline);
}
bool uses_dynamic_rt_callable_stack;
bool uses_rt;
bool uses_full_subgroups;
+
+ bool regalloc_hang_bug;
} cs;
struct {
uint64_t tes_inputs_read;
}
info->cs.subgroup_size = subgroup_size;
+
+ if (device->physical_device->rad_info.has_cs_regalloc_hang_bug) {
+ info->cs.regalloc_hang_bug =
+ info->cs.block_size[0] * info->cs.block_size[1] * info->cs.block_size[2] > 256;
+ }
}
static void