radv: move cs_regalloc_hang_bug to radv_shader_info
authorSamuel Pitoiset <samuel.pitoiset@gmail.com>
Tue, 21 Mar 2023 10:13:41 +0000 (11:13 +0100)
committerMarge Bot <emma+marge@anholt.net>
Fri, 24 Mar 2023 12:43:51 +0000 (12:43 +0000)
This is more like a shader property.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22102>

src/amd/vulkan/radv_cmd_buffer.c
src/amd/vulkan/radv_pipeline.c
src/amd/vulkan/radv_private.h
src/amd/vulkan/radv_shader.h
src/amd/vulkan/radv_shader_info.c

index 9f68afa..5c624e8 100644 (file)
@@ -9763,10 +9763,11 @@ static void
 radv_dispatch(struct radv_cmd_buffer *cmd_buffer, const struct radv_dispatch_info *info,
               struct radv_compute_pipeline *pipeline, VkPipelineBindPoint bind_point)
 {
+   struct radv_shader *compute_shader = pipeline->base.shaders[MESA_SHADER_COMPUTE];
    bool has_prefetch = cmd_buffer->device->physical_device->rad_info.gfx_level >= GFX7;
    bool pipeline_is_dirty = pipeline != cmd_buffer->state.emitted_compute_pipeline;
 
-   if (pipeline->cs_regalloc_hang_bug)
+   if (compute_shader->info.cs.regalloc_hang_bug)
       cmd_buffer->state.flush_bits |= RADV_CMD_FLAG_PS_PARTIAL_FLUSH |
                                       RADV_CMD_FLAG_CS_PARTIAL_FLUSH;
 
@@ -9825,7 +9826,7 @@ radv_dispatch(struct radv_cmd_buffer *cmd_buffer, const struct radv_dispatch_inf
                                                      : VK_PIPELINE_BIND_POINT_COMPUTE);
    }
 
-   if (pipeline->cs_regalloc_hang_bug)
+   if (compute_shader->info.cs.regalloc_hang_bug)
       cmd_buffer->state.flush_bits |= RADV_CMD_FLAG_CS_PARTIAL_FLUSH;
 
    radv_cmd_buffer_after_draw(cmd_buffer, RADV_CMD_FLAG_CS_PARTIAL_FLUSH);
index c2306e5..63ca692 100644 (file)
@@ -5303,13 +5303,6 @@ radv_compute_pipeline_init(struct radv_compute_pipeline *pipeline,
 
    pipeline->base.shader_upload_seq = pipeline->base.shaders[MESA_SHADER_COMPUTE]->upload_seq;
 
-   if (device->physical_device->rad_info.has_cs_regalloc_hang_bug) {
-      struct radv_shader *compute_shader = pipeline->base.shaders[MESA_SHADER_COMPUTE];
-      unsigned *cs_block_size = compute_shader->info.cs.block_size;
-
-      pipeline->cs_regalloc_hang_bug = cs_block_size[0] * cs_block_size[1] * cs_block_size[2] > 256;
-   }
-
    radv_compute_generate_pm4(pipeline);
 }
 
index 9298240..6c484db 100644 (file)
@@ -2275,8 +2275,6 @@ struct radv_graphics_pipeline {
 
 struct radv_compute_pipeline {
    struct radv_pipeline base;
-
-   bool cs_regalloc_hang_bug;
 };
 
 struct radv_ray_tracing_module {
index 46ac486..1168f10 100644 (file)
@@ -367,6 +367,8 @@ struct radv_shader_info {
       bool uses_dynamic_rt_callable_stack;
       bool uses_rt;
       bool uses_full_subgroups;
+
+      bool regalloc_hang_bug;
    } cs;
    struct {
       uint64_t tes_inputs_read;
index bcc6701..a7c28e2 100644 (file)
@@ -697,6 +697,11 @@ gather_shader_info_cs(struct radv_device *device, const nir_shader *nir,
    }
 
    info->cs.subgroup_size = subgroup_size;
+
+   if (device->physical_device->rad_info.has_cs_regalloc_hang_bug) {
+      info->cs.regalloc_hang_bug =
+         info->cs.block_size[0] * info->cs.block_size[1] * info->cs.block_size[2] > 256;
+   }
 }
 
 static void