AArch64 support for NEG in vector registers for DI and SI mode

git-svn-id: svn+ssh://gcc.gnu.org/svn/gcc/trunk@201261 138bc75d-0d04-0410-961f-82ee72b054a4

diff --git a/gcc/ChangeLog b/gcc/ChangeLog
index f3fabaa..773e35c 100644 (file)
--- a/gcc/ChangeLog
+++ b/gcc/ChangeLog
@@ -1,3 +1,8 @@
+2013-07-26  Ian Bolton  <ian.bolton@arm.com>
+
+       * config/aarch64/aarch64.md (neg<mode>2): Offer alternative that
+       uses vector registers.
+
 2013-07-26  Kyrylo Tkachov  <kyrylo.tkachov@arm.com>
             Richard Earnshaw  <richard.earnshaw@arm.com>
 

diff --git a/gcc/config/aarch64/aarch64.md b/gcc/config/aarch64/aarch64.md
index 233014e..5d64228 100644 (file)
--- a/gcc/config/aarch64/aarch64.md
+++ b/gcc/config/aarch64/aarch64.md
@@ -2041,12 +2041,17 @@
 )
 
 (define_insn "neg<mode>2"
-  [(set (match_operand:GPI 0 "register_operand" "=r")
-       (neg:GPI (match_operand:GPI 1 "register_operand" "r")))]
+  [(set (match_operand:GPI 0 "register_operand" "=r,w")
+       (neg:GPI (match_operand:GPI 1 "register_operand" "r,w")))]
   ""
-  "neg\\t%<w>0, %<w>1"
+  "@
+   neg\\t%<w>0, %<w>1
+   neg\\t%<rtn>0<vas>, %<rtn>1<vas>"
   [(set_attr "v8type" "alu")
-   (set_attr "mode" "<MODE>")]
+   (set_attr "simd_type" "*,simd_negabs")
+   (set_attr "simd" "*,yes")
+   (set_attr "mode" "<MODE>")
+   (set_attr "simd_mode" "<MODE>")]
 )
 
 ;; zero_extend version of above

diff --git a/gcc/testsuite/ChangeLog b/gcc/testsuite/ChangeLog
index 202cdaa..ca1a227 100644 (file)
--- a/gcc/testsuite/ChangeLog
+++ b/gcc/testsuite/ChangeLog
@@ -1,3 +1,7 @@
+2013-07-26  Ian Bolton  <ian.bolton@arm.com>
+
+       * gcc.target/aarch64/neg_1.c: New test.
+
 2013-07-25  Janus Weil  <janus@gcc.gnu.org>
 
        PR fortran/57966

diff --git a/gcc/testsuite/gcc.target/aarch64/neg_1.c b/gcc/testsuite/gcc.target/aarch64/neg_1.c
new file mode 100644 (file)
index 0000000..04b0fdd
--- /dev/null
+++ b/gcc/testsuite/gcc.target/aarch64/neg_1.c
@@ -0,0 +1,67 @@
+/* { dg-do run } */
+/* { dg-options "-O2 -fno-inline --save-temps" } */
+
+extern void abort (void);
+
+long long
+neg64 (long long a)
+{
+  /* { dg-final { scan-assembler "neg\tx\[0-9\]+" } } */
+  return 0 - a;
+}
+
+long long
+neg64_in_dreg (long long a)
+{
+  /* { dg-final { scan-assembler "neg\td\[0-9\]+, d\[0-9\]+" } } */
+  register long long x asm ("d8") = a;
+  register long long y asm ("d9");
+  asm volatile ("" : : "w" (x));
+  y = 0 - x;
+  asm volatile ("" : : "w" (y));
+  return y;
+}
+
+int
+neg32 (int a)
+{
+  /* { dg-final { scan-assembler "neg\tw\[0-9\]+" } } */
+  return 0 - a;
+}
+
+int
+neg32_in_sreg (int a)
+{
+  /* { dg-final { scan-assembler "neg\tv\[0-9\]+\.2s, v\[0-9\]+\.2s" } } */
+  register int x asm ("s8") = a;
+  register int y asm ("s9");
+  asm volatile ("" : : "w" (x));
+  y = 0 - x;
+  asm volatile ("" : : "w" (y));
+  return y;
+}
+
+int
+main (void)
+{
+  long long a;
+  int b;
+  a = 61;
+  b = 313;
+
+  if (neg64 (a) != -61)
+    abort ();
+
+  if (neg64_in_dreg (a) != -61)
+    abort ();
+
+  if (neg32 (b) != -313)
+    abort ();
+
+  if (neg32_in_sreg (b) != -313)
+    abort ();
+
+  return 0;
+}
+
+/* { dg-final { cleanup-saved-temps } } */