intel/dev: switch defect identifiers to use lineage numbers

Update existing workarounds when necessary to match changed
identifiers.

Reviewed-by: Tapani Pälli <tapani.palli@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/23226>

diff --git a/src/gallium/drivers/iris/iris_state.c b/src/gallium/drivers/iris/iris_state.c
index 96736c9..1b08973 100644 (file)
--- a/src/gallium/drivers/iris/iris_state.c
+++ b/src/gallium/drivers/iris/iris_state.c
@@ -4862,9 +4862,9 @@ iris_store_tes_state(const struct intel_device_info *devinfo,
       te.MaximumTessellationFactorNotOdd = 64.0;
 #if GFX_VERx10 >= 125
       STATIC_ASSERT(TEDMODE_OFF == 0);
-      if (intel_needs_workaround(devinfo, 14015297576)) {
+      if (intel_needs_workaround(devinfo, 14015055625)) {
          te.TessellationDistributionMode = TEDMODE_OFF;
-      } else if (intel_needs_workaround(devinfo, 22012785325)) {
+      } else if (intel_needs_workaround(devinfo, 22012699309)) {
          te.TessellationDistributionMode = TEDMODE_RR_STRICT;
       } else {
          te.TessellationDistributionMode = TEDMODE_RR_FREE;
@@ -6133,24 +6133,24 @@ iris_preemption_streamout_wa(struct iris_context *ice,
 }
 
 static void
-shader_program_needs_wa_14015297576(struct iris_context *ice,
+shader_program_needs_wa_14015055625(struct iris_context *ice,
                                     struct iris_batch *batch,
                                     const struct brw_stage_prog_data *prog_data,
                                     gl_shader_stage stage,
-                                    bool *program_needs_wa_14015297576)
+                                    bool *program_needs_wa_14015055625)
 {
-   if (!intel_needs_workaround(batch->screen->devinfo, 14015297576))
+   if (!intel_needs_workaround(batch->screen->devinfo, 14015055625))
       return;
 
    switch (stage) {
    case MESA_SHADER_TESS_CTRL: {
       struct brw_tcs_prog_data *tcs_prog_data = (void *) prog_data;
-      *program_needs_wa_14015297576 |= tcs_prog_data->include_primitive_id;
+      *program_needs_wa_14015055625 |= tcs_prog_data->include_primitive_id;
       break;
    }
    case MESA_SHADER_TESS_EVAL: {
       struct brw_tes_prog_data *tes_prog_data = (void *) prog_data;
-      *program_needs_wa_14015297576 |= tes_prog_data->include_primitive_id;
+      *program_needs_wa_14015055625 |= tes_prog_data->include_primitive_id;
       break;
    }
    default:
@@ -6162,7 +6162,7 @@ shader_program_needs_wa_14015297576(struct iris_context *ice,
    const struct brw_gs_prog_data *gs_prog_data =
       gs_shader ? (void *) gs_shader->prog_data : NULL;
 
-   *program_needs_wa_14015297576 |=
+   *program_needs_wa_14015055625 |=
       gs_prog_data && gs_prog_data->include_primitive_id;
 }
 
@@ -6508,14 +6508,14 @@ iris_upload_dirty_render_state(struct iris_context *ice,
       }
    }
 
-   bool program_needs_wa_14015297576 = false;
+   bool program_needs_wa_14015055625 = false;
 
-   /* Check if FS stage will use primitive ID overrides for Wa_14015297576. */
+   /* Check if FS stage will use primitive ID overrides for Wa_14015055625. */
    const struct brw_vue_map *last_vue_map =
       &brw_vue_prog_data(ice->shaders.last_vue_shader->prog_data)->vue_map;
    if ((wm_prog_data->inputs & VARYING_BIT_PRIMITIVE_ID) &&
        last_vue_map->varying_to_slot[VARYING_SLOT_PRIMITIVE_ID] == -1) {
-      program_needs_wa_14015297576 = true;
+      program_needs_wa_14015055625 = true;
    }
 
    for (int stage = 0; stage <= MESA_SHADER_FRAGMENT; stage++) {
@@ -6532,8 +6532,8 @@ iris_upload_dirty_render_state(struct iris_context *ice,
          uint32_t scratch_addr =
             pin_scratch_space(ice, batch, prog_data, stage);
 
-         shader_program_needs_wa_14015297576(ice, batch, prog_data, stage,
-                                             &program_needs_wa_14015297576);
+         shader_program_needs_wa_14015055625(ice, batch, prog_data, stage,
+                                             &program_needs_wa_14015055625);
 
          if (stage == MESA_SHADER_FRAGMENT) {
             UNUSED struct iris_rasterizer_state *cso = ice->state.cso_rast;
@@ -6592,15 +6592,15 @@ iris_upload_dirty_render_state(struct iris_context *ice,
             iris_emit_merge(batch, shader_psx, psx_state,
                             GENX(3DSTATE_PS_EXTRA_length));
          } else if (stage == MESA_SHADER_TESS_EVAL &&
-                    intel_needs_workaround(batch->screen->devinfo, 14015297576) &&
-                    !program_needs_wa_14015297576) {
-            /* This program doesn't require Wa_14015297576, so we can enable
+                    intel_needs_workaround(batch->screen->devinfo, 14015055625) &&
+                    !program_needs_wa_14015055625) {
+            /* This program doesn't require Wa_14015055625, so we can enable
              * a Tessellation Distribution Mode.
              */
 #if GFX_VERx10 >= 125
             uint32_t te_state[GENX(3DSTATE_TE_length)] = { 0 };
             iris_pack_command(GENX(3DSTATE_TE), te_state, te) {
-               if (intel_needs_workaround(batch->screen->devinfo, 22012785325))
+               if (intel_needs_workaround(batch->screen->devinfo, 22012699309))
                   te.TessellationDistributionMode = TEDMODE_RR_STRICT;
                else
                   te.TessellationDistributionMode = TEDMODE_RR_FREE;
@@ -7415,11 +7415,11 @@ iris_upload_render_state(struct iris_context *ice,
       batch->contains_draw_with_next_seqno = true;
    }
 
-   /* Wa_1409433168 - Send HS state for every primitive on gfx11.
+   /* Wa_1306463417 - Send HS state for every primitive on gfx11.
     * Wa_16011107343 (same for gfx12)
     * We implement this by setting TCS dirty on each draw.
     */
-   if ((INTEL_NEEDS_WA_1409433168 || INTEL_NEEDS_WA_16011107343) &&
+   if ((INTEL_NEEDS_WA_1306463417 || INTEL_NEEDS_WA_16011107343) &&
        ice->shaders.prog[MESA_SHADER_TESS_CTRL]) {
       ice->state.stage_dirty |= IRIS_STAGE_DIRTY_TCS;
    }

diff --git a/src/intel/common/intel_genX_state.h b/src/intel/common/intel_genX_state.h
index a2dbbdd..3a3ef86 100644 (file)
--- a/src/intel/common/intel_genX_state.h
+++ b/src/intel/common/intel_genX_state.h
@@ -131,7 +131,7 @@ intel_set_ps_dispatch_state(struct GENX(3DSTATE_PS) *ps,
 UNUSED static int
 preferred_slm_allocation_size(const struct intel_device_info *devinfo)
 {
-   if (intel_needs_workaround(devinfo, 14017341140))
+   if (intel_needs_workaround(devinfo, 14017245111))
       return SLM_ENCODES_96K;
 
    return 0;

diff --git a/src/intel/compiler/brw_nir.c b/src/intel/compiler/brw_nir.c
index c266ca0..f4284df 100644 (file)
--- a/src/intel/compiler/brw_nir.c
+++ b/src/intel/compiler/brw_nir.c
@@ -1101,7 +1101,7 @@ brw_nir_zero_inputs(nir_shader *shader, uint64_t *zero_inputs)
          nir_metadata_block_index | nir_metadata_dominance, zero_inputs);
 }
 
-/* Code for Wa_14015590813 may have created input/output variables beyond
+/* Code for Wa_18019110168 may have created input/output variables beyond
  * VARYING_SLOT_MAX and removed uses of variables below VARYING_SLOT_MAX.
  * Clean it up, so they all stay below VARYING_SLOT_MAX.
  */
@@ -1138,7 +1138,7 @@ brw_mesh_compact_io(nir_shader *mesh, nir_shader *frag)
    if (!compact)
       return;
 
-   /* The rest of this function should be hit only for Wa_14015590813. */
+   /* The rest of this function should be hit only for Wa_18019110168. */
 
    nir_foreach_shader_out_variable(var, mesh) {
       gl_varying_slot location = var->data.location;

diff --git a/src/intel/dev/intel_device_info.c b/src/intel/dev/intel_device_info.c
index ec0d173..4daf3b0 100644 (file)
--- a/src/intel/dev/intel_device_info.c
+++ b/src/intel/dev/intel_device_info.c
@@ -1373,7 +1373,7 @@ intel_device_info_init_common(int pci_id,
 static void
 intel_device_info_apply_workarounds(struct intel_device_info *devinfo)
 {
-   if (intel_needs_workaround(devinfo, 22012575642))
+   if (intel_needs_workaround(devinfo, 18012660806))
       devinfo->urb.max_entries[MESA_SHADER_GEOMETRY] = 1536;
 
    /* Fixes issues with:

diff --git a/src/intel/dev/mesa_defs.json b/src/intel/dev/mesa_defs.json
index cbce6bb..041f703 100644 (file)
--- a/src/intel/dev/mesa_defs.json
+++ b/src/intel/dev/mesa_defs.json
@@ -16,125 +16,98 @@
       }
     }
   },
-  "1405543622": {
+  "1305770284": {
     "mesa_platforms": {
       "INTEL_PLATFORM_EHL": {
         "ids": [
-          14010909196
+          1407403919
         ],
         "steppings": "all"
-      }
-    }
-  },
-  "1405586840": {
-    "mesa_platforms": {
+      },
       "INTEL_PLATFORM_ICL": {
         "ids": [
-          1405862851
+          1305770284,
+          1407391552,
+          1407399546
         ],
         "steppings": "all"
       }
     }
   },
-  "1406306137": {
+  "1306055483": {
     "mesa_platforms": {
       "INTEL_PLATFORM_EHL": {
         "ids": [
-          1406990620
+          1408631644
         ],
         "steppings": "all"
       },
       "INTEL_PLATFORM_ICL": {
         "ids": [
-          1406306137,
-          1406340945
+          1306055483,
+          1408615042,
+          1408626922
         ],
         "steppings": "all"
       }
     }
   },
-  "1406606421": {
+  "1306463417": {
     "mesa_platforms": {
-      "INTEL_PLATFORM_ADL": {
-        "ids": [
-          14010801457,
-          14013824293
-        ],
-        "steppings": "all"
-      },
-      "INTEL_PLATFORM_DG1": {
-        "ids": [
-          1406606421,
-          14010679611
-        ],
-        "steppings": "all"
-      },
-      "INTEL_PLATFORM_RKL": {
-        "ids": [
-          14010680668
-        ],
-        "steppings": "all"
-      },
-      "INTEL_PLATFORM_RPL": {
+      "INTEL_PLATFORM_EHL": {
         "ids": [
-          14010801457,
-          14013824293
+          1409442356
         ],
         "steppings": "all"
       },
-      "INTEL_PLATFORM_TGL": {
+      "INTEL_PLATFORM_ICL": {
         "ids": [
-          1406606421,
-          14010679611
+          1306463417,
+          1409433168,
+          1409440821
         ],
         "steppings": "all"
       }
     }
   },
-  "1406609750": {
+  "1405543622": {
     "mesa_platforms": {
-      "INTEL_PLATFORM_RKL": {
+      "INTEL_PLATFORM_EHL": {
         "ids": [
-          14010680673
+          14010909196
         ],
         "steppings": "all"
       }
     }
   },
-  "1406614636": {
+  "1405586840": {
     "mesa_platforms": {
-      "INTEL_PLATFORM_EHL": {
-        "ids": [
-          14010882456
-        ],
-        "steppings": "all"
-      },
       "INTEL_PLATFORM_ICL": {
         "ids": [
-          1406614636,
-          14010882322
+          1405862851
         ],
         "steppings": "all"
       }
     }
   },
-  "1406631448": {
+  "1406306137": {
     "mesa_platforms": {
-      "INTEL_PLATFORM_DG1": {
+      "INTEL_PLATFORM_EHL": {
         "ids": [
-          1406631448
+          1406990620
         ],
         "steppings": "all"
       },
-      "INTEL_PLATFORM_TGL": {
+      "INTEL_PLATFORM_ICL": {
         "ids": [
-          1406631448
+          1406306137,
+          1406340945
         ],
         "steppings": "all"
       }
     }
   },
-  "1406680960": {
+  "1406337848": {
     "mesa_platforms": {
       "INTEL_PLATFORM_ADL": {
         "ids": [
@@ -146,6 +119,7 @@
       },
       "INTEL_PLATFORM_DG1": {
         "ids": [
+          1406337848,
           1406680960,
           14010679640
         ],
@@ -167,6 +141,7 @@
       },
       "INTEL_PLATFORM_TGL": {
         "ids": [
+          1406337848,
           1406680960,
           14010679640
         ],
@@ -174,107 +149,130 @@
       }
     }
   },
-  "1406697149": {
+  "1406606421": {
     "mesa_platforms": {
-      "INTEL_PLATFORM_EHL": {
+      "INTEL_PLATFORM_ADL": {
         "ids": [
-          1406990764
+          14010698203,
+          14010801457,
+          14013824293
         ],
         "steppings": "all"
       },
-      "INTEL_PLATFORM_ICL": {
+      "INTEL_PLATFORM_DG1": {
         "ids": [
-          1406697149,
-          1406697800
+          1406606421,
+          14010679611
+        ],
+        "steppings": "all"
+      },
+      "INTEL_PLATFORM_RKL": {
+        "ids": [
+          14010680668
+        ],
+        "steppings": "all"
+      },
+      "INTEL_PLATFORM_RPL": {
+        "ids": [
+          14010698203,
+          14010801457,
+          14013824293
+        ],
+        "steppings": "all"
+      },
+      "INTEL_PLATFORM_TGL": {
+        "ids": [
+          1406606421,
+          14010679611
         ],
         "steppings": "all"
       }
     }
   },
-  "1406756463": {
+  "1406609750": {
     "mesa_platforms": {
-      "INTEL_PLATFORM_ICL": {
+      "INTEL_PLATFORM_RKL": {
         "ids": [
-          1406756463,
-          1406966074
+          14010680673
         ],
         "steppings": "all"
       }
     }
   },
-  "1406950495": {
+  "1406614636": {
     "mesa_platforms": {
       "INTEL_PLATFORM_EHL": {
         "ids": [
-          1407016567
+          14010882456
         ],
         "steppings": "all"
       },
       "INTEL_PLATFORM_ICL": {
         "ids": [
-          1406950495,
-          1407001392
+          1406614636,
+          14010882322
         ],
         "steppings": "all"
       }
     }
   },
-  "1407240128": {
+  "1406697149": {
     "mesa_platforms": {
       "INTEL_PLATFORM_EHL": {
         "ids": [
-          1407251288
+          1406990764
         ],
         "steppings": "all"
       },
       "INTEL_PLATFORM_ICL": {
         "ids": [
-          1407240128,
-          1407243700
+          1406697149,
+          1406697800
         ],
         "steppings": "all"
       }
     }
   },
-  "1407385565": {
+  "1406756463": {
     "mesa_platforms": {
       "INTEL_PLATFORM_ICL": {
         "ids": [
-          1407385565,
-          1407391147
+          1406756463,
+          1406966074
         ],
         "steppings": "all"
       }
     }
   },
-  "1407391552": {
+  "1406950495": {
     "mesa_platforms": {
       "INTEL_PLATFORM_EHL": {
         "ids": [
-          1407403919
+          1407016567
         ],
         "steppings": "all"
       },
       "INTEL_PLATFORM_ICL": {
         "ids": [
-          1407391552,
-          1407399546
+          1406950495,
+          1407001392
         ],
         "steppings": "all"
       }
     }
   },
-  "1407520876": {
+  "1407240128": {
     "mesa_platforms": {
       "INTEL_PLATFORM_EHL": {
         "ids": [
-          1407533743
+          1407251288
         ],
-        "steppings": "a0..b0"
+        "steppings": "all"
       },
       "INTEL_PLATFORM_ICL": {
         "ids": [
-          1407520876
+          1407240128,
+          1407243700
         ],
         "steppings": "all"
       }
@@ -284,6 +282,7 @@
     "mesa_platforms": {
       "INTEL_PLATFORM_ADL": {
         "ids": [
+          1409386879,
           14010801730,
           14013823841
         ],
@@ -304,6 +303,7 @@
       },
       "INTEL_PLATFORM_RPL": {
         "ids": [
+          1409386879,
           14010801730,
           14013823841
         ],
@@ -339,6 +339,7 @@
     "mesa_platforms": {
       "INTEL_PLATFORM_ADL": {
         "ids": [
+          1409386784,
           14010801777,
           14013823797
         ],
@@ -353,6 +354,7 @@
       },
       "INTEL_PLATFORM_RPL": {
         "ids": [
+          1409386784,
           14010801777,
           14013823797
         ],
@@ -371,6 +373,7 @@
     "mesa_platforms": {
       "INTEL_PLATFORM_ADL": {
         "ids": [
+          1409386594,
           14010801791,
           14013823780
         ],
@@ -391,6 +394,7 @@
       },
       "INTEL_PLATFORM_RPL": {
         "ids": [
+          1409386594,
           14010801791,
           14013823780
         ],
@@ -415,24 +419,7 @@
       }
     }
   },
-  "1408615042": {
-    "mesa_platforms": {
-      "INTEL_PLATFORM_EHL": {
-        "ids": [
-          1408631644
-        ],
-        "steppings": "all"
-      },
-      "INTEL_PLATFORM_ICL": {
-        "ids": [
-          1408615042,
-          1408626922
-        ],
-        "steppings": "all"
-      }
-    }
-  },
-  "1408937953": {
+  "1408908852": {
     "mesa_platforms": {
       "INTEL_PLATFORM_EHL": {
         "ids": [
@@ -443,6 +430,7 @@
       },
       "INTEL_PLATFORM_ICL": {
         "ids": [
+          1408908852,
           1408937953,
           1408941138
         ],
@@ -462,6 +450,7 @@
       "INTEL_PLATFORM_DG1": {
         "ids": [
           1409392000,
+          1409392018,
           1409392019
         ],
         "steppings": "all"
@@ -482,23 +471,6 @@
       }
     }
   },
-  "1409433168": {
-    "mesa_platforms": {
-      "INTEL_PLATFORM_EHL": {
-        "ids": [
-          1409442356
-        ],
-        "steppings": "all"
-      },
-      "INTEL_PLATFORM_ICL": {
-        "ids": [
-          1409433168,
-          1409440821
-        ],
-        "steppings": "all"
-      }
-    }
-  },
   "1409600907": {
     "mesa_platforms": {
       "INTEL_PLATFORM_ADL": {
@@ -535,68 +507,12 @@
       }
     }
   },
-  "1505013527": {
-    "mesa_platforms": {
-      "INTEL_PLATFORM_EHL": {
-        "ids": [
-          1407064519
-        ],
-        "steppings": "all"
-      },
-      "INTEL_PLATFORM_ICL": {
-        "ids": [
-          1407058870,
-          1505013527
-        ],
-        "steppings": "all"
-      }
-    }
-  },
-  "1508701464": {
-    "mesa_platforms": {
-      "INTEL_PLATFORM_ADL": {
-        "ids": [
-          1508701464,
-          14013824004,
-          16012203808
-        ],
-        "steppings": "all"
-      },
-      "INTEL_PLATFORM_DG1": {
-        "ids": [
-          16012409068,
-          16012414995
-        ],
-        "steppings": "all"
-      },
-      "INTEL_PLATFORM_RKL": {
-        "ids": [
-          16012415143
-        ],
-        "steppings": "all"
-      },
-      "INTEL_PLATFORM_RPL": {
-        "ids": [
-          1508701464,
-          14013824004,
-          16012203808
-        ],
-        "steppings": "all"
-      },
-      "INTEL_PLATFORM_TGL": {
-        "ids": [
-          16012409068,
-          16012414995
-        ],
-        "steppings": "all"
-      }
-    }
-  },
   "1508744258": {
     "mesa_platforms": {
       "INTEL_PLATFORM_ADL": {
         "ids": [
           14013824817,
+          16012812099,
           22012530219
         ],
         "steppings": "all"
@@ -618,6 +534,7 @@
       "INTEL_PLATFORM_RPL": {
         "ids": [
           14013824817,
+          16012812099,
           22012530219
         ],
         "steppings": "all"
@@ -657,6 +574,7 @@
     "mesa_platforms": {
       "INTEL_PLATFORM_ADL": {
         "ids": [
+          14010698051,
           14010801151,
           14013824179
         ],
@@ -691,6 +609,7 @@
       },
       "INTEL_PLATFORM_RPL": {
         "ids": [
+          14010698051,
           14010801151,
           14013824179
         ],
@@ -747,6 +666,7 @@
     "mesa_platforms": {
       "INTEL_PLATFORM_ADL": {
         "ids": [
+          1409386777,
           14010802348,
           14013823795
         ],
@@ -767,6 +687,7 @@
       },
       "INTEL_PLATFORM_RPL": {
         "ids": [
+          1409386777,
           14010802348,
           14013823795
         ],
@@ -821,6 +742,18 @@
       }
     }
   },
+  "1607794140": {
+    "mesa_platforms": {
+      "INTEL_PLATFORM_TGL": {
+        "ids": [
+          1607794140,
+          14010672564,
+          16011655240
+        ],
+        "steppings": "a0..c0"
+      }
+    }
+  },
   "1607854226": {
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+        "steppings": "all"
+      },
+      "INTEL_PLATFORM_DG2_G12": {
+        "ids": [
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         ],
         "steppings": "all"
       }
     }
   },
-  "18012201914": {
+  "18012660806": {
     "mesa_platforms": {
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+        "ids": [
+          14013840690,
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+          14013841850
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+        "steppings": "all"
+      },
+      "INTEL_PLATFORM_DG1": {
+        "ids": [
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+          18012660806,
+          22012575642
+        ],
+        "steppings": "all"
+      },
       "INTEL_PLATFORM_DG2_G10": {
         "ids": [
-          18012201914
+          14013840143
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         "steppings": "all"
       },
       "INTEL_PLATFORM_DG2_G11": {
         "ids": [
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         ],
         "steppings": "all"
       },
       "INTEL_PLATFORM_DG2_G12": {
         "ids": [
-          14015548862
+          14015547433
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+      "INTEL_PLATFORM_MTL_M": {
+        "ids": [
+          14013840342
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+        "steppings": "a0..b0"
+      },
+      "INTEL_PLATFORM_RKL": {
+        "ids": [
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+        "steppings": "all"
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         "steppings": "all"
       }
@@ -3095,369 +2968,581 @@
       }
     }
   },
-  "22010628972": {
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+          18013889147
         ],
         "steppings": "all"
-      }
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-  },
-  "22011186057": {
-    "mesa_platforms": {
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+        "steppings": "all"
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-  "22011440098": {
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       "INTEL_PLATFORM_DG2_G12": {
         "ids": [
-          14015549061
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         "ids": [
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-          14013841850
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-      "INTEL_PLATFORM_DG1": {
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-          22012575642
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         "steppings": "all"
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         "ids": [
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       "INTEL_PLATFORM_DG2_G12": {
         "ids": [
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+          14017425777
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+      "INTEL_PLATFORM_EHL": {
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       "INTEL_PLATFORM_MTL_P": {
         "ids": [
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+      "INTEL_PLATFORM_RKL": {
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         "steppings": "all"
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   },
-  "22013689345": {
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         "ids": [
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+          14017879046,
+          18023881693
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+        "steppings": "all"
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       "INTEL_PLATFORM_MTL_P": {
         "ids": [
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-        "steppings": "a0..b0"
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-  "22013866836": {
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     "mesa_platforms": {
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         "steppings": "all"
       },
-      "INTEL_PLATFORM_MTL_P": {
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+        "ids": [
+          16012351604,
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+          22010893396
+        ],
+        "steppings": "all"
+      }
+    }
+  },
+  "22011186057": {
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         "ids": [
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+          22011186057
         ],
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       }
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   },
-  "22014344549": {
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         "ids": [
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         "ids": [
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         "steppings": "all"
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     }
   },
-  "22015224714": {
+  "22012699309": {
     "mesa_platforms": {
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+      "INTEL_PLATFORM_DG2_G10": {
         "ids": [
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-          14016946037,
-          14016950670
+          22012699309,
+          22012785325
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         "steppings": "all"
       },
-      "INTEL_PLATFORM_DG1": {
+      "INTEL_PLATFORM_DG2_G12": {
         "ids": [
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-          14016937494
+          14015549270
+        ],
+        "steppings": "all"
+      }
+    }
+  },
+  "22012725308": {
+    "mesa_platforms": {
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+        "ids": [
+          14013898759,
+          22012725308
+        ],
+        "steppings": "all"
+      }
+    }
+  },
+  "22013045878": {
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+      "INTEL_PLATFORM_DG2_G10": {
+        "ids": [
+          14014427904,
+          22013045878
         ],
         "steppings": "all"
       },
+      "INTEL_PLATFORM_DG2_G12": {
+        "ids": [
+          14015547818
+        ],
+        "steppings": "all"
+      }
+    }
+  },
+  "22013073587": {
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       "INTEL_PLATFORM_DG2_G10": {
         "ids": [
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+          22013073587
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       "INTEL_PLATFORM_DG2_G11": {
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       "INTEL_PLATFORM_DG2_G12": {
         "ids": [
-          14017100203
+          14015549420
         ],
         "steppings": "all"
-      },
-      "INTEL_PLATFORM_MTL_M": {
+      }
+    }
+  },
+  "22013689345": {
+    "mesa_platforms": {
+      "INTEL_PLATFORM_DG2_G10": {
         "ids": [
-          14016872205
+          22013689345
         ],
-        "steppings": "a0..b0"
+        "steppings": "all"
       },
-      "INTEL_PLATFORM_MTL_P": {
+      "INTEL_PLATFORM_DG2_G11": {
         "ids": [
-          14016880026
+          22013689510
         ],
-        "steppings": "a0..b0"
+        "steppings": "all"
       },
-      "INTEL_PLATFORM_RKL": {
+      "INTEL_PLATFORM_DG2_G12": {
         "ids": [
-          14016946064
+          14015549447
         ],
         "steppings": "all"
       },
-      "INTEL_PLATFORM_RPL": {
+      "INTEL_PLATFORM_MTL_M": {
         "ids": [
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-          14016946037,
-          14016950670
+          14014906135
         ],
-        "steppings": "all"
+        "steppings": "a0..b0"
       },
-      "INTEL_PLATFORM_TGL": {
+      "INTEL_PLATFORM_MTL_P": {
         "ids": [
-          14016929415,
-          14016937494
+          14014909922
         ],
-        "steppings": "all"
+        "steppings": "a0..b0"
       }
     }
   },
-  "22015614752": {
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     "mesa_platforms": {
       "INTEL_PLATFORM_DG2_G10": {
         "ids": [
-          22015614752
+          22014344549
+        ],
+        "steppings": "all"
+      },
+      "INTEL_PLATFORM_DG2_G11": {
+        "ids": [
+          22014345565
+        ],
+        "steppings": "all"
+      },
+      "INTEL_PLATFORM_DG2_G12": {
+        "ids": [
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         ],
         "steppings": "all"
       }
     }
   },
-  "22015761040": {
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         "ids": [
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+          14016118574,
+          22014412737
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         "steppings": "all"
       },
       "INTEL_PLATFORM_DG2_G11": {
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       "INTEL_PLATFORM_DG2_G12": {
         "ids": [
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+          14016381311
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       },
       "INTEL_PLATFORM_MTL_M": {
         "ids": [
-          14017483381
+          14016119375
         ],
-        "steppings": "all"
+        "steppings": "a0..b0"
       },
       "INTEL_PLATFORM_MTL_P": {
         "ids": [
-          22015761040
+          14016120505
+        ],
+        "steppings": "a0..b0"
+      }
+    }
+  },
+  "22015614752": {
+    "mesa_platforms": {
+      "INTEL_PLATFORM_DG2_G10": {
+        "ids": [
+          22015614752
+        ],
+        "steppings": "all"
+      },
+      "INTEL_PLATFORM_DG2_G12": {
+        "ids": [
+          14019383215
         ],
         "steppings": "all"
       }

diff --git a/src/intel/vulkan/anv_image.c b/src/intel/vulkan/anv_image.c
index 993f021..314c317 100644 (file)
--- a/src/intel/vulkan/anv_image.c
+++ b/src/intel/vulkan/anv_image.c
@@ -345,7 +345,7 @@ can_fast_clear_with_non_zero_color(const struct intel_device_info *devinfo,
       return false;
 
    /* On TGL (< C0), if a block of fragment shader outputs match the surface's
-    * clear color, the HW may convert them to fast-clears (see HSD 14010672564).
+    * clear color, the HW may convert them to fast-clears (see HSD 1607794140).
     * This can lead to rendering corruptions if not handled properly. We
     * restrict the clear color to zero to avoid issues that can occur with:
     *     - Texture view rendering (including blorp_copy calls)
@@ -757,7 +757,7 @@ add_aux_surface_if_supported(struct anv_device *device,
                                        image->vk.format, image->vk.tiling,
                                        image->vk.usage, fmt_list)) {
          image->planes[plane].aux_usage =
-            intel_needs_workaround(device->info, 14010672564) ?
+            intel_needs_workaround(device->info, 1607794140) ?
                ISL_AUX_USAGE_GFX12_CCS_E :
                ISL_AUX_USAGE_CCS_E;
       } else if (device->info->ver >= 12) {

diff --git a/src/intel/vulkan/anv_mesh_perprim_wa.c b/src/intel/vulkan/anv_mesh_perprim_wa.c
index f7346b6..d1313cb 100644 (file)
--- a/src/intel/vulkan/anv_mesh_perprim_wa.c
+++ b/src/intel/vulkan/anv_mesh_perprim_wa.c
@@ -25,7 +25,7 @@
 #include "nir_builder.h"
 
 /*
- * Wa_14015590813 for gfx 12.5.
+ * Wa_18019110168 for gfx 12.5.
  *
  * This file implements workaround for HW bug, which leads to fragment shader
  * reading incorrect per-primitive data if mesh shader, in addition to writing
@@ -532,7 +532,7 @@ anv_apply_per_prim_attr_wa(struct nir_shader *ms_nir,
    int mesh_conv_prim_attrs_to_vert_attrs =
          device->physical->instance->mesh_conv_prim_attrs_to_vert_attrs;
    if (mesh_conv_prim_attrs_to_vert_attrs < 0 &&
-         !intel_needs_workaround(devinfo, 14015590813))
+         !intel_needs_workaround(devinfo, 18019110168))
       mesh_conv_prim_attrs_to_vert_attrs = 0;
 
    if (mesh_conv_prim_attrs_to_vert_attrs != 0) {

diff --git a/src/intel/vulkan/genX_cmd_buffer.c b/src/intel/vulkan/genX_cmd_buffer.c
index 10b359c..f6eecdb 100644 (file)
--- a/src/intel/vulkan/genX_cmd_buffer.c
+++ b/src/intel/vulkan/genX_cmd_buffer.c
@@ -3420,9 +3420,9 @@ genX(cmd_buffer_flush_gfx_state)(struct anv_cmd_buffer *cmd_buffer)
       cmd_buffer->state.push_descriptors_dirty &= ~push_descriptor_dirty;
    }
 
-   /* Wa_1409433168, Wa_16011107343 - Send HS state for every primitive. */
+   /* Wa_1306463417, Wa_16011107343 - Send HS state for every primitive. */
    if (cmd_buffer->state.gfx.dirty & ANV_CMD_DIRTY_PIPELINE ||
-       (INTEL_NEEDS_WA_1409433168 || INTEL_NEEDS_WA_16011107343)) {
+       (INTEL_NEEDS_WA_1306463417 || INTEL_NEEDS_WA_16011107343)) {
       genX(emit_hs)(cmd_buffer);
    }
 
@@ -3586,9 +3586,9 @@ anv_use_generated_draws(const struct anv_cmd_buffer *cmd_buffer, uint32_t count)
    const struct anv_device *device = cmd_buffer->device;
 
    /* Limit generated draws to pipelines without HS stage. This makes things
-    * simpler for implementing Wa_1409433168, Wa_16011107343.
+    * simpler for implementing Wa_1306463417, Wa_16011107343.
     */
-   if ((INTEL_NEEDS_WA_1409433168 || INTEL_NEEDS_WA_16011107343) &&
+   if ((INTEL_NEEDS_WA_1306463417 || INTEL_NEEDS_WA_16011107343) &&
        anv_pipeline_has_stage(cmd_buffer->state.gfx.pipeline,
                               MESA_SHADER_TESS_CTRL)) {
       return false;
@@ -4269,10 +4269,10 @@ void genX(CmdDrawMultiEXT)(
 #else
    vk_foreach_multi_draw(draw, i, pVertexInfo, drawCount, stride) {
 
-      /* Wa_1409433168, Wa_16011107343 - Send HS state for every primitive,
+      /* Wa_1306463417, Wa_16011107343 - Send HS state for every primitive,
        * first one was handled by cmd_buffer_flush_gfx_state.
        */
-      if (i && (INTEL_NEEDS_WA_1409433168 || INTEL_NEEDS_WA_16011107343))
+      if (i && (INTEL_NEEDS_WA_1306463417 || INTEL_NEEDS_WA_16011107343))
          genX(emit_hs)(cmd_buffer);
 
       const uint32_t count = draw->vertexCount * instanceCount;
@@ -4502,10 +4502,10 @@ void genX(CmdDrawMultiIndexedEXT)(
 #else
    vk_foreach_multi_draw_indexed(draw, i, pIndexInfo, drawCount, stride) {
 
-      /* Wa_1409433168, Wa_16011107343 - Send HS state for every primitive,
+      /* Wa_1306463417, Wa_16011107343 - Send HS state for every primitive,
        * first one was handled by cmd_buffer_flush_gfx_state.
        */
-      if (i && (INTEL_NEEDS_WA_1409433168 || INTEL_NEEDS_WA_16011107343))
+      if (i && (INTEL_NEEDS_WA_1306463417 || INTEL_NEEDS_WA_16011107343))
          genX(emit_hs)(cmd_buffer);
 
       const uint32_t count =
@@ -4761,10 +4761,10 @@ emit_indirect_draws(struct anv_cmd_buffer *cmd_buffer,
 
       load_indirect_parameters(cmd_buffer, draw, indexed, i);
 
-      /* Wa_1409433168, Wa_16011107343 - Send HS state for every primitive,
+      /* Wa_1306463417, Wa_16011107343 - Send HS state for every primitive,
        * first one was handled by cmd_buffer_flush_gfx_state.
        */
-      if (i && (INTEL_NEEDS_WA_1409433168 || INTEL_NEEDS_WA_16011107343))
+      if (i && (INTEL_NEEDS_WA_1306463417 || INTEL_NEEDS_WA_16011107343))
          genX(emit_hs)(cmd_buffer);
 
       anv_batch_emit(&cmd_buffer->batch,
@@ -4986,10 +4986,10 @@ emit_indirect_count_draws(struct anv_cmd_buffer *cmd_buffer,
 
       load_indirect_parameters(cmd_buffer, draw, indexed, i);
 
-      /* Wa_1409433168, Wa_16011107343 - Send HS state for every primitive,
+      /* Wa_1306463417, Wa_16011107343 - Send HS state for every primitive,
        * first one was handled by cmd_buffer_flush_gfx_state.
        */
-      if (i && (INTEL_NEEDS_WA_1409433168 || INTEL_NEEDS_WA_16011107343))
+      if (i && (INTEL_NEEDS_WA_1306463417 || INTEL_NEEDS_WA_16011107343))
          genX(emit_hs)(cmd_buffer);
 
       anv_batch_emit(&cmd_buffer->batch,

diff --git a/src/intel/vulkan/gfx8_cmd_buffer.c b/src/intel/vulkan/gfx8_cmd_buffer.c
index bc4a762..68c8a1d 100644 (file)
--- a/src/intel/vulkan/gfx8_cmd_buffer.c
+++ b/src/intel/vulkan/gfx8_cmd_buffer.c
@@ -250,13 +250,13 @@ genX(cmd_emit_te)(struct anv_cmd_buffer *cmd_buffer)
       te.MaximumTessellationFactorOdd = 63.0;
       te.MaximumTessellationFactorNotOdd = 64.0;
 #if GFX_VERx10 >= 125
-      if (intel_needs_workaround(cmd_buffer->device->info, 22012785325))
+      if (intel_needs_workaround(cmd_buffer->device->info, 22012699309))
          te.TessellationDistributionMode = TEDMODE_RR_STRICT;
       else
          te.TessellationDistributionMode = TEDMODE_RR_FREE;
 
-      if (intel_needs_workaround(cmd_buffer->device->info, 14015297576)) {
-         /* Wa_14015297576:
+      if (intel_needs_workaround(cmd_buffer->device->info, 14015055625)) {
+         /* Wa_14015055625:
           *
           * Disable Tessellation Distribution when primitive Id is enabled.
           */