fi
endif
-shell_cmd = { $(echo-cmd) $(cmd_$(1)); }
+shell_cmd = { $(call echo-cmd,$(1)) $(cmd_$(1)); }
quiet_cmd_objcopy_uboot = OBJCOPY $@
cmd_objcopy_uboot = $(cmd_objcopy) && $(call shell_cmd,static_rela,$<,$@,$(CONFIG_SYS_TEXT_BASE)) || rm -f $@
dtb-$(CONFIG_ARCH_IMX8M) += \
imx8mm-evk.dtb \
imx8mm-verdin.dtb \
+ phycore-imx8mm.dtb \
imx8mn-ddr4-evk.dtb \
imx8mq-evk.dtb \
imx8mm-beacon-kit.dtb \
imx6q-b650v3.dtb \
imx6q-b450v3.dtb
+dtb-$(CONFIG_TARGET_GE_B1X5V2) += imx6dl-b1x5v2.dtb
dtb-$(CONFIG_TARGET_MX53PPD) += imx53-ppd.dtb
dtb-$(CONFIG_TARGET_VEXPRESS_CA5X2) += vexpress-v2p-ca5s.dtb
MX53_PAD_GPIO_1__GPIO1_1 0x1e4
/* KEY1 GPIO */
MX53_PAD_EIM_RW__GPIO2_26 0x1e4
+ /* LED GREEN GPIO */
+ MX53_PAD_EIM_WAIT__GPIO5_0 0x1e4
+ /* LED RED GPIO */
+ MX53_PAD_EIM_D28__GPIO3_28 0x1e4
>;
};
--- /dev/null
+/*
+ * GE B1x5v2 Patient Monitor
+ *
+ * Copyright 2018-2020 GE Inc.
+ * Copyright 2018-2020 Collabora Ltd.
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+/dts-v1/;
+
+#include "imx6dl.dtsi"
+#include <dt-bindings/gpio/gpio.h>
+
+/ {
+ compatible = "ge,imx6dl-b1x5v2", "congatec,qmx6", "fsl,imx6dl";
+
+ chosen {
+ bootargs = "console=ttymxc2,115200";
+ stdout-path = &uart3;
+ };
+
+ reg_3p3v: 3p3v {
+ compatible = "regulator-fixed";
+ regulator-name = "3P3V";
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ regulator-always-on;
+ };
+
+ reg_5v: regulator-5v {
+ compatible = "regulator-fixed";
+ regulator-name = "5V";
+ regulator-min-microvolt = <5000000>;
+ regulator-max-microvolt = <5000000>;
+ regulator-always-on;
+ };
+
+ reg_5v0_audio: regulator-5v0-audio {
+ compatible = "regulator-fixed";
+ regulator-name = "5V0_AUDIO";
+ regulator-min-microvolt = <5000000>;
+ regulator-max-microvolt = <5000000>;
+ vin-supply = <®_5v>;
+
+ gpio = <&tca6424a 16 GPIO_ACTIVE_HIGH>;
+ enable-active-high;
+
+ /*
+ * This must be always-on for da7212, which has some not properly
+ * documented dependencies for it's speaker supply pin. The issue
+ * manifests as speaker volume being very low.
+ */
+ regulator-always-on;
+ regulator-boot-on;
+ };
+
+ reg_lcd: regulator-lcd {
+ compatible = "regulator-fixed";
+ regulator-name = "LED_VCC";
+ regulator-min-microvolt = <12000000>;
+ regulator-max-microvolt = <12000000>;
+
+ pinctrl-0 = <&pinctrl_q7_lcd_power>;
+ pinctrl-names = "default";
+ gpio = <&gpio1 7 GPIO_ACTIVE_HIGH>; // LCDPWR
+ enable-active-high;
+ };
+
+ usb_power: regulator-usb-power {
+ compatible = "regulator-fixed";
+ regulator-name = "USB POWER";
+ regulator-min-microvolt = <5000000>;
+ regulator-max-microvolt = <5000000>;
+ vin-supply = <®_5v>;
+ };
+
+ backlight: backlight {
+ compatible = "pwm-backlight";
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_q7_backlight_enable>;
+ power-supply = <®_lcd>;
+ pwms = <&pwm4 0 5000000>;
+ brightness-levels = <0 4 8 16 32 64 128 255>;
+ default-brightness-level = <7>;
+ enable-gpios = <&gpio1 9 GPIO_ACTIVE_HIGH>;
+ };
+
+ panel {
+ compatible = "simple-panel";
+ backlight = <&backlight>;
+
+ port {
+ panel_in: endpoint {
+ remote-endpoint = <&lvds0_out>;
+ };
+ };
+ };
+
+ bootcount {
+ compatible = "u-boot,bootcount-spi-flash";
+ spi-flash = <&flash>;
+ offset = <0x01003fe>;
+ };
+
+ leds {
+ compatible = "gpio-leds";
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_q7_gpio1 &pinctrl_q7_gpio3 &pinctrl_q7_gpio5>;
+
+ alarm1 {
+ label = "alarm:red";
+ gpios = <&gpio1 8 GPIO_ACTIVE_HIGH>;
+ };
+
+ alarm2 {
+ label = "alarm:yellow";
+ gpios = <&gpio4 27 GPIO_ACTIVE_HIGH>;
+ };
+
+ alarm3 {
+ label = "alarm:blue";
+ gpios = <&gpio4 15 GPIO_ACTIVE_HIGH>;
+ };
+ };
+
+ poweroff {
+ compatible = "gpio-poweroff";
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_q7_spi_cs1>;
+ gpios = <&gpio4 25 GPIO_ACTIVE_LOW>;
+ active-delay-ms = <1000>;
+ inactive-delay-ms = <0>;
+ timeout-ms = <5000>;
+ };
+
+ i2cmux {
+ compatible = "i2c-mux-gpio";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_i2cmux>;
+ mux-gpios = <&gpio6 9 GPIO_ACTIVE_HIGH>;
+ i2c-parent = <&i2c2>;
+ idle-state = <1>;
+
+ i2c5: i2c@0 {
+ reg = <0>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ tmp112: temperature-sensor@48 {
+ compatible = "ti,tmp112";
+ reg = <0x48>;
+ interrupt-parent = <&tca6424a>;
+ interrupts = <2 IRQ_TYPE_LEVEL_LOW>;
+ };
+
+ tca6424a: gpio-controller@22 {
+ compatible = "ti,tca6424";
+ reg = <0x22>;
+ gpio-controller;
+ #gpio-cells = <2>;
+
+ interrupt-parent = <&gpio7>;
+ interrupts = <11 IRQ_TYPE_EDGE_RISING>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_q7_gpio6>;
+ interrupt-controller;
+ #interrupt-cells = <2>;
+
+ gpio-line-names = "GPIO_ROTOR#", "", "TMP_SENSOR_IRQ", "ACM_GPIO1", "ACM_GPIO2", "BATT_T", "", "",
+ "ACM_GPIO3", "ACM_GPIO4", "USB1_POWER_EN", "EGPIO_CC_CTL0", "EGPIO_CC_CTL1", "12V_OEMNBP_EN", "CP2105_RST", "",
+ "SPEAKER_PA_EN", "ARM7_UPI_RESET", "ARM7_PWR_RST", "NURSE_CALL", "MARKER_EN", "EGPIO_TOUCH_RST", "", "";
+ };
+ };
+
+ i2c6: i2c@1 {
+ reg = <1>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ pmic: pmic@08 {
+ compatible = "fsl,pfuze100";
+ reg = <0x08>;
+ };
+ };
+ };
+};
+
+&usbh1 {
+ /* Connected to USB-Hub SMSC USB2514, provides P0, P2, P3, P4 on Qseven connector */
+ vbus-supply = <®_5v>;
+ status = "okay";
+};
+
+&usbotg {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_usbotg>;
+ vbus-supply = <&usb_power>;
+ disable-over-current;
+ dr_mode = "host";
+ status = "okay";
+};
+
+&pmic {
+ regulators {
+ sw1a_reg: sw1ab {
+ regulator-min-microvolt = <300000>;
+ regulator-max-microvolt = <1875000>;
+ regulator-boot-on;
+ regulator-always-on;
+ regulator-ramp-delay = <6250>;
+ };
+
+ sw1c_reg: sw1c {
+ regulator-min-microvolt = <300000>;
+ regulator-max-microvolt = <1875000>;
+ regulator-boot-on;
+ regulator-always-on;
+ regulator-ramp-delay = <6250>;
+ };
+
+ sw2_reg: sw2 {
+ regulator-min-microvolt = <800000>;
+ regulator-max-microvolt = <3300000>;
+ regulator-boot-on;
+ regulator-always-on;
+ };
+
+ sw3a_reg: sw3a {
+ regulator-min-microvolt = <400000>;
+ regulator-max-microvolt = <1975000>;
+ regulator-boot-on;
+ regulator-always-on;
+ };
+
+ sw3b_reg: sw3b {
+ regulator-min-microvolt = <400000>;
+ regulator-max-microvolt = <1975000>;
+ regulator-boot-on;
+ regulator-always-on;
+ };
+
+ sw4_reg: sw4 {
+ regulator-min-microvolt = <675000>;
+ regulator-max-microvolt = <3300000>;
+ regulator-boot-on;
+ regulator-always-on;
+ };
+
+ swbst_reg: swbst {
+ regulator-min-microvolt = <5000000>;
+ regulator-max-microvolt = <5150000>;
+ };
+
+ snvs_reg: vsnvs {
+ regulator-min-microvolt = <1000000>;
+ regulator-max-microvolt = <3000000>;
+ regulator-boot-on;
+ regulator-always-on;
+ };
+
+ vref_reg: vrefddr {
+ regulator-boot-on;
+ regulator-always-on;
+ };
+
+ /* keep VGEN3, VGEN4 and VGEN5 enabled in order to maintain backward compatibility with hw-rev. A.0 */
+ vgen3_reg: vgen3 {
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <3300000>;
+ regulator-always-on;
+ };
+
+ vgen4_reg: vgen4 {
+ regulator-min-microvolt = <2500000>;
+ regulator-max-microvolt = <2500000>;
+ regulator-always-on;
+ };
+
+ vgen5_reg: vgen5 {
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <3300000>;
+ regulator-always-on;
+ };
+
+ /* supply voltage for eMMC */
+ vgen6_reg: vgen6 {
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ regulator-boot-on;
+ regulator-always-on;
+ };
+ };
+};
+
+&uart2 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_uart2>;
+ status = "okay";
+};
+
+&uart3 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_uart3>;
+ status = "okay";
+};
+
+&usdhc2 {
+ /* MicroSD card slot */
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_usdhc2>;
+ cd-gpios = <&gpio1 4 GPIO_ACTIVE_LOW>;
+ no-1-8-v;
+ keep-power-in-suspend;
+ wakeup-source;
+ vmmc-supply = <®_3p3v>;
+ status = "okay";
+};
+
+&usdhc3 {
+ /* eMMC module */
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_usdhc3>;
+ non-removable;
+ bus-width = <8>;
+ no-1-8-v;
+ keep-power-in-suspend;
+ wakeup-source;
+ vmmc-supply = <®_3p3v>;
+ status = "okay";
+};
+
+&i2c1 {
+ status = "okay";
+ pinctrl-names = "default", "gpio";
+ pinctrl-0 = <&pinctrl_i2c1>;
+ pinctrl-1 = <&pinctrl_i2c1_gpio>;
+ scl-gpios = <&gpio3 21 GPIO_ACTIVE_HIGH>;
+ sda-gpios = <&gpio3 28 GPIO_ACTIVE_HIGH>;
+
+ clock-frequency = <100000>;
+};
+
+&i2c2 {
+ status = "okay";
+ pinctrl-names = "default", "gpio";
+ pinctrl-0 = <&pinctrl_i2c2>;
+ pinctrl-1 = <&pinctrl_i2c2_gpio>;
+ scl-gpios = <&gpio4 12 GPIO_ACTIVE_HIGH>;
+ sda-gpios = <&gpio4 13 GPIO_ACTIVE_HIGH>;
+
+ clock-frequency = <100000>;
+};
+
+&i2c3 {
+ status = "okay";
+ pinctrl-names = "default", "gpio";
+ pinctrl-0 = <&pinctrl_i2c3>;
+ pinctrl-1 = <&pinctrl_i2c3_gpio>;
+ scl-gpios = <&gpio1 3 GPIO_ACTIVE_HIGH>;
+ sda-gpios = <&gpio1 6 GPIO_ACTIVE_HIGH>;
+
+ clock-frequency = <100000>;
+
+ rtc: m41t62@68 {
+ compatible = "st,m41t62";
+ reg = <0x68>;
+ };
+};
+
+&ldb {
+ status = "okay";
+
+ lvds0: lvds-channel@0 {
+ status = "okay";
+ fsl,data-mapping = "spwg";
+ fsl,data-width = <24>;
+
+ port@4 {
+ reg = <4>;
+ lvds0_out: endpoint {
+ remote-endpoint = <&panel_in>;
+ };
+ };
+ };
+};
+
+&hdmi {
+ status = "okay";
+};
+
+&fec {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_enet &pinctrl_phy_reset>;
+ phy-mode = "rgmii-id";
+ phy-handle = <&phy>;
+ status = "okay";
+
+ fsl,magic-packet;
+
+ mdio {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ phy: ethernet-phy@6 {
+ compatible = "ethernet-phy-ieee802.3-c22";
+ reg = <6>;
+ qca,clk-out-frequency = <125000000>;
+ reset-gpios = <&gpio3 23 GPIO_ACTIVE_LOW>;
+ reset-assert-us = <2000>;
+ };
+ };
+};
+
+&ecspi1 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_ecspi1>;
+ status = "okay";
+
+ num-cs = <1>;
+ cs-gpios = <&gpio3 19 GPIO_ACTIVE_LOW>;
+
+ flash: m25p80@0 {
+ #address-cells = <1>;
+ #size-cells = <1>;
+ compatible = "st,sst25vf032b", "jedec,spi-nor";
+ spi-max-frequency = <20000000>;
+ reg = <0>;
+
+ partition@0 {
+ label = "bootloader";
+ reg = <0x0000000 0x100000>;
+ };
+
+ partition@100000 {
+ label = "user";
+ reg = <0x0100000 0x2fc000>;
+ };
+
+ partition@3fc000 {
+ label = "reserved";
+ reg = <0x03fc000 0x4000>;
+ read-only;
+ };
+ };
+};
+
+&pwm4 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_pwm4>;
+ status = "okay";
+};
+
+&wdog1 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_wdog>;
+ fsl,ext-reset-output;
+};
+
+&iomuxc {
+ imx6qdl-congatec-qmx6 {
+ pinctrl_uart2: uart2grp {
+ fsl,pins = <
+ MX6QDL_PAD_EIM_D26__UART2_TX_DATA 0x1b0b1
+ MX6QDL_PAD_EIM_D27__UART2_RX_DATA 0x1b0b1
+ >;
+ };
+
+ pinctrl_uart3: uart3grp {
+ fsl,pins = <
+ MX6QDL_PAD_EIM_D25__UART3_RX_DATA 0x1b0b1
+ MX6QDL_PAD_EIM_D24__UART3_TX_DATA 0x1b0b1
+ >;
+ };
+
+ pinctrl_wdog: wdoggrp {
+ fsl,pins = <
+ MX6QDL_PAD_DISP0_DAT8__WDOG1_B 0x1b0b0
+ >;
+ };
+
+ pinctrl_usdhc2: usdhc2grp {
+ fsl,pins = <
+ MX6QDL_PAD_SD2_CMD__SD2_CMD 0x17059
+ MX6QDL_PAD_SD2_CLK__SD2_CLK 0x10059
+ MX6QDL_PAD_SD2_DAT0__SD2_DATA0 0x17059
+ MX6QDL_PAD_SD2_DAT1__SD2_DATA1 0x17059
+ MX6QDL_PAD_SD2_DAT2__SD2_DATA2 0x17059
+ MX6QDL_PAD_SD2_DAT3__SD2_DATA3 0x17059
+ >;
+ };
+
+ pinctrl_usdhc2_cd: sd2cdgrp {
+ fsl,pins = <
+ MX6QDL_PAD_GPIO_4__GPIO1_IO04 0x1b0b0
+ >;
+ };
+
+ pinctrl_usdhc3: usdhc4grp {
+ fsl,pins = <
+ MX6QDL_PAD_SD3_CMD__SD3_CMD 0x17059
+ MX6QDL_PAD_SD3_CLK__SD3_CLK 0x10059
+ MX6QDL_PAD_SD3_DAT0__SD3_DATA0 0x17059
+ MX6QDL_PAD_SD3_DAT1__SD3_DATA1 0x17059
+ MX6QDL_PAD_SD3_DAT2__SD3_DATA2 0x17059
+ MX6QDL_PAD_SD3_DAT3__SD3_DATA3 0x17059
+ MX6QDL_PAD_SD3_DAT4__SD3_DATA4 0x17059
+ MX6QDL_PAD_SD3_DAT5__SD3_DATA5 0x17059
+ MX6QDL_PAD_SD3_DAT6__SD3_DATA6 0x17059
+ MX6QDL_PAD_SD3_DAT7__SD3_DATA7 0x17059
+ >;
+ };
+
+ pinctrl_i2c1: i2c1grp {
+ fsl,pins = <
+ MX6QDL_PAD_EIM_D21__I2C1_SCL 0x4001b8b1
+ MX6QDL_PAD_EIM_D28__I2C1_SDA 0x4001b8b1
+ >;
+ };
+
+ pinctrl_i2c1_gpio: i2c1gpiogrp {
+ fsl,pins = <
+ MX6QDL_PAD_EIM_D21__GPIO3_IO21 0x1b0b0
+ MX6QDL_PAD_EIM_D28__GPIO3_IO28 0x1b0b0
+ >;
+ };
+
+ pinctrl_i2c2: i2c2grp {
+ fsl,pins = <
+ MX6QDL_PAD_KEY_COL3__I2C2_SCL 0x4001b8b1
+ MX6QDL_PAD_KEY_ROW3__I2C2_SDA 0x4001b8b1
+ >;
+ };
+
+ pinctrl_i2c2_gpio: i2c2gpiogrp {
+ fsl,pins = <
+ MX6QDL_PAD_KEY_COL3__GPIO4_IO12 0x1b0b0
+ MX6QDL_PAD_KEY_ROW3__GPIO4_IO13 0x1b0b0
+ >;
+ };
+
+ pinctrl_i2c3: i2c3grp {
+ fsl,pins = <
+ MX6QDL_PAD_GPIO_3__I2C3_SCL 0x4001b8b1
+ MX6QDL_PAD_GPIO_6__I2C3_SDA 0x4001b8b1
+ >;
+ };
+
+ pinctrl_i2c3_gpio: i2c3gpiogrp {
+ fsl,pins = <
+ MX6QDL_PAD_GPIO_3__GPIO1_IO03 0x1b0b0
+ MX6QDL_PAD_GPIO_6__GPIO1_IO06 0x1b0b0
+ >;
+ };
+
+ pinctrl_ecspi1: ecspi1grp {
+ fsl,pins = <
+ MX6QDL_PAD_EIM_D16__ECSPI1_SCLK 0x100b1
+ MX6QDL_PAD_EIM_D17__ECSPI1_MISO 0x100b1
+ MX6QDL_PAD_EIM_D18__ECSPI1_MOSI 0x100b1
+ MX6QDL_PAD_EIM_D19__GPIO3_IO19 0x1b0b0
+ >;
+ };
+
+ pinctrl_enet: enetgrp {
+ fsl,pins = <
+ MX6QDL_PAD_ENET_MDIO__ENET_MDIO 0x1b0b0
+ MX6QDL_PAD_ENET_MDC__ENET_MDC 0x1b0b0
+ MX6QDL_PAD_RGMII_TXC__RGMII_TXC 0x1b030
+ MX6QDL_PAD_RGMII_TD0__RGMII_TD0 0x1b030
+ MX6QDL_PAD_RGMII_TD1__RGMII_TD1 0x1b030
+ MX6QDL_PAD_RGMII_TD2__RGMII_TD2 0x1b030
+ MX6QDL_PAD_RGMII_TD3__RGMII_TD3 0x1b030
+ MX6QDL_PAD_RGMII_TX_CTL__RGMII_TX_CTL 0x1b030
+ MX6QDL_PAD_ENET_REF_CLK__ENET_TX_CLK 0x1b0b0
+ MX6QDL_PAD_RGMII_RXC__RGMII_RXC 0x1b030
+ MX6QDL_PAD_RGMII_RD0__RGMII_RD0 0x1b030
+ MX6QDL_PAD_RGMII_RD1__RGMII_RD1 0x1b030
+ MX6QDL_PAD_RGMII_RD2__RGMII_RD2 0x1b030
+ MX6QDL_PAD_RGMII_RD3__RGMII_RD3 0x1b030
+ MX6QDL_PAD_RGMII_RX_CTL__RGMII_RX_CTL 0x1b030
+ MX6QDL_PAD_ENET_TX_EN__ENET_TX_EN 0x1b0b0
+ >;
+ };
+
+ pinctrl_phy_reset: phyrstgrp {
+ fsl,pins = <
+ MX6QDL_PAD_EIM_D23__GPIO3_IO23 0x4001b0b0 /* RGMII Phy Reset */
+ >;
+ };
+
+ pinctrl_pwm4: pwm4grp {
+ fsl,pins = <
+ MX6QDL_PAD_SD1_CMD__PWM4_OUT 0x1b0b1 /* Q7[123] LVDS_BLT_CTRL */
+ >;
+ };
+
+ pinctrl_q7_lcd_power: lcdpwrgrp {
+ fsl,pins = <
+ MX6QDL_PAD_GPIO_7__GPIO1_IO07 0x4001b0b0 /* Q7[111] LVDS_PPEN */
+ >;
+ };
+
+ pinctrl_q7_backlight_enable: blengrp {
+ fsl,pins = <
+ MX6QDL_PAD_GPIO_9__GPIO1_IO09 0x4001b0b0 /* Q7[112] LVDS_BLEN */
+ >;
+ };
+
+ pinctrl_q7_gpio1: q7gpio1grp {
+ fsl,pins = <
+ MX6QDL_PAD_GPIO_8__GPIO1_IO08 0x4001b0b0 /* Q7[186] GPIO1 */
+ >;
+ };
+
+ pinctrl_q7_gpio3: q7gpio3grp {
+ fsl,pins = <
+ MX6QDL_PAD_DISP0_DAT6__GPIO4_IO27 0x4001b0b0 /* Q7[188] GPIO3 */
+ >;
+ };
+
+ pinctrl_q7_gpio5: q7gpio5grp {
+ fsl,pins = <
+ MX6QDL_PAD_KEY_ROW4__GPIO4_IO15 0x4001b0b0 /* Q7[190] GPIO5 */
+ >;
+ };
+
+ pinctrl_q7_gpio6: q7gpio6grp {
+ fsl,pins = <
+ MX6QDL_PAD_GPIO_16__GPIO7_IO11 0x1b0b0 /* Q7[191] GPIO6 */
+ >;
+ };
+
+ pinctrl_q7_spi_cs1: spics1grp {
+ fsl,pins = <
+ MX6QDL_PAD_DISP0_DAT4__GPIO4_IO25 0x4001b0b0 /* Q7[202] SPI_CS1# */
+ >;
+ };
+
+ pinctrl_i2cmux: i2cmuxgrp {
+ fsl,pins = <
+ MX6QDL_PAD_NANDF_WP_B__GPIO6_IO09 0x4001b0b0
+ >;
+ };
+
+ pinctrl_usbotg: usbotggrp {
+ fsl,pins = <
+ MX6QDL_PAD_GPIO_1__USB_OTG_ID 0x17059 /* Q7[92] USB_ID */
+ >;
+ };
+ };
+};
--- /dev/null
+// SPDX-License-Identifier: GPL-2.0-or-later
+/*
+ * Copyright (C) 2020 PHYTEC Messtechnik GmbH
+ * Author: Teresa Remmet <t.remmet@phytec.de>
+ */
+
+/ {
+ wdt-reboot {
+ compatible = "wdt-reboot";
+ wdt = <&wdog1>;
+ u-boot,dm-spl;
+ };
+};
+
+&{/soc@0} {
+ u-boot,dm-pre-reloc;
+ u-boot,dm-spl;
+};
+
+&clk {
+ u-boot,dm-spl;
+ u-boot,dm-pre-reloc;
+ /delete-property/ assigned-clocks;
+ /delete-property/ assigned-clock-parents;
+ /delete-property/ assigned-clock-rates;
+};
+
+&osc_24m {
+ u-boot,dm-spl;
+ u-boot,dm-pre-reloc;
+};
+
+&aips1 {
+ u-boot,dm-spl;
+ u-boot,dm-pre-reloc;
+};
+
+&aips2 {
+ u-boot,dm-spl;
+};
+
+&aips3 {
+ u-boot,dm-spl;
+};
+
+&iomuxc {
+ u-boot,dm-spl;
+};
+
+&pinctrl_uart3 {
+ u-boot,dm-spl;
+};
+
+&pinctrl_usdhc2_gpio {
+ u-boot,dm-spl;
+};
+
+&pinctrl_usdhc2 {
+ u-boot,dm-spl;
+};
+
+&pinctrl_usdhc3 {
+ u-boot,dm-spl;
+};
+
+&gpio1 {
+ u-boot,dm-spl;
+};
+
+&gpio2 {
+ u-boot,dm-spl;
+};
+
+&gpio3 {
+ u-boot,dm-spl;
+};
+
+&gpio4 {
+ u-boot,dm-spl;
+};
+
+&gpio5 {
+ u-boot,dm-spl;
+};
+
+&uart3 {
+ u-boot,dm-spl;
+};
+
+&usdhc2 {
+ u-boot,dm-spl;
+};
+
+&usdhc3 {
+ u-boot,dm-spl;
+};
+
+&wdog1 {
+ u-boot,dm-spl;
+};
--- /dev/null
+// SPDX-License-Identifier: GPL-2.0-or-later
+/*
+ * Copyright (C) 2019-2020 PHYTEC Messtechnik GmbH
+ * Author: Teresa Remmet <t.remmet@phytec.de>
+ */
+
+/dts-v1/;
+
+#include <dt-bindings/net/ti-dp83867.h>
+#include "imx8mm.dtsi"
+
+/ {
+ model = "PHYTEC phyCORE-i.MX8MM";
+ compatible = "phytec,imx8mm-phycore-som", "fsl,imx8mm";
+
+ chosen {
+ stdout-patch = &uart3;
+ };
+
+ reg_usdhc2_vmmc: regulator-usdhc2 {
+ compatible = "regulator-fixed";
+ regulator-name = "VSD_3V3";
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ startup-delay-us = <100>;
+ off-on-delay-us = <12000>;
+ };
+};
+
+/* ethernet */
+&fec1 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_fec1>;
+ phy-mode = "rgmii-id";
+ phy-handle = <ðphy0>;
+ phy-reset-gpios = <&gpio1 7 GPIO_ACTIVE_HIGH>;
+ phy-reset-duration = <1>;
+ phy-reset-post-delay = <1>;
+ status = "okay";
+
+ mdio {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ ethphy0: ethernet-phy@0 {
+ compatible = "ethernet-phy-ieee802.3-c22";
+ reg = <0x0>;
+ ti,rx-internal-delay = <DP83867_RGMIIDCTL_2_00_NS>;
+ ti,tx-internal-delay = <DP83867_RGMIIDCTL_2_00_NS>;
+ ti,fifo-depth = <DP83867_PHYCR_FIFO_DEPTH_4_B_NIB>;
+ ti,clk-output-sel = <DP83867_CLK_O_SEL_OFF>;
+ enet-phy-lane-no-swap;
+ };
+ };
+};
+
+/* i2c eeprom */
+&i2c1 {
+ clock-frequency = <400000>;
+ pinctrl-names = "default", "gpio";
+ pinctrl-0 = <&pinctrl_i2c1>;
+ pinctrl-1 = <&pinctrl_i2c1_gpio>;
+ scl-gpios = <&gpio5 14 GPIO_ACTIVE_HIGH>;
+ sda-gpios = <&gpio5 15 GPIO_ACTIVE_HIGH>;
+ status = "okay";
+
+ /* M24C32-D */
+ i2c_eeprom: eeprom@51 {
+ compatible = "atmel,24c32";
+ reg = <0x51>;
+ u-boot,i2c-offset-len = <2>;
+ };
+
+ /* M24C32-D Identification page */
+ i2c_eeprom_id: eeprom@59 {
+ compatible = "atmel,24c32";
+ reg = <0x59>;
+ u-boot,i2c-offset-len = <2>;
+ };
+};
+
+/* debug console */
+&uart3 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_uart3>;
+ status = "okay";
+};
+
+/* sd-card */
+&usdhc2 {
+ pinctrl-names = "default", "state_100mhz", "state_200mhz";
+ pinctrl-0 = <&pinctrl_usdhc2>, <&pinctrl_usdhc2_gpio>;
+ pinctrl-1 = <&pinctrl_usdhc2_100mhz>, <&pinctrl_usdhc2_gpio>;
+ pinctrl-2 = <&pinctrl_usdhc2_200mhz>, <&pinctrl_usdhc2_gpio>;
+ cd-gpios = <&gpio2 12 GPIO_ACTIVE_LOW>;
+ bus-width = <4>;
+ vmmc-supply = <®_usdhc2_vmmc>;
+ status = "okay";
+};
+
+/* eMMC */
+&usdhc3 {
+ pinctrl-names = "default", "state_100mhz", "state_200mhz";
+ pinctrl-0 = <&pinctrl_usdhc3>;
+ pinctrl-1 = <&pinctrl_usdhc3_100mhz>;
+ pinctrl-2 = <&pinctrl_usdhc3_200mhz>;
+ bus-width = <8>;
+ non-removable;
+ status = "okay";
+};
+
+/* watchdog */
+&wdog1 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_wdog>;
+ fsl,ext-reset-output;
+ status = "okay";
+};
+
+&iomuxc {
+ pinctrl-names = "default";
+
+ pinctrl_fec1: fec1grp {
+ fsl,pins = <
+ MX8MM_IOMUXC_ENET_MDC_ENET1_MDC 0x3
+ MX8MM_IOMUXC_ENET_MDIO_ENET1_MDIO 0x3
+ MX8MM_IOMUXC_ENET_TD3_ENET1_RGMII_TD3 0x1f
+ MX8MM_IOMUXC_ENET_TD2_ENET1_RGMII_TD2 0x1f
+ MX8MM_IOMUXC_ENET_TD1_ENET1_RGMII_TD1 0x1f
+ MX8MM_IOMUXC_ENET_TD0_ENET1_RGMII_TD0 0x1f
+ MX8MM_IOMUXC_ENET_RD3_ENET1_RGMII_RD3 0x91
+ MX8MM_IOMUXC_ENET_RD2_ENET1_RGMII_RD2 0x91
+ MX8MM_IOMUXC_ENET_RD1_ENET1_RGMII_RD1 0x91
+ MX8MM_IOMUXC_ENET_RD0_ENET1_RGMII_RD0 0x91
+ MX8MM_IOMUXC_ENET_TXC_ENET1_RGMII_TXC 0x1f
+ MX8MM_IOMUXC_ENET_RXC_ENET1_RGMII_RXC 0x91
+ MX8MM_IOMUXC_ENET_RX_CTL_ENET1_RGMII_RX_CTL 0x91
+ MX8MM_IOMUXC_ENET_TX_CTL_ENET1_RGMII_TX_CTL 0x1f
+ MX8MM_IOMUXC_GPIO1_IO07_GPIO1_IO7 0x19
+ >;
+ };
+
+ pinctrl_i2c1: i2c1grp {
+ fsl,pins = <
+ MX8MM_IOMUXC_I2C1_SCL_I2C1_SCL 0x400001c3
+ MX8MM_IOMUXC_I2C1_SDA_I2C1_SDA 0x400001c3
+ >;
+ };
+
+ pinctrl_i2c1_gpio: i2c1grp-gpio {
+ fsl,pins = <
+ MX8MM_IOMUXC_I2C1_SCL_GPIO5_IO14 0x1c3
+ MX8MM_IOMUXC_I2C1_SDA_GPIO5_IO15 0x1c3
+ >;
+ };
+
+ pinctrl_uart3: uart3grp {
+ fsl,pins = <
+ MX8MM_IOMUXC_UART3_RXD_UART3_DCE_RX 0x49
+ MX8MM_IOMUXC_UART3_TXD_UART3_DCE_TX 0x49
+ >;
+ };
+
+ pinctrl_usdhc2_gpio: usdhc2grpgpio {
+ fsl,pins = <
+ MX8MM_IOMUXC_SD2_CD_B_GPIO2_IO12 0x41
+ >;
+ };
+
+ pinctrl_usdhc2: usdhc2grp {
+ fsl,pins = <
+ MX8MM_IOMUXC_SD2_CLK_USDHC2_CLK 0x190
+ MX8MM_IOMUXC_SD2_CMD_USDHC2_CMD 0x1d0
+ MX8MM_IOMUXC_SD2_DATA0_USDHC2_DATA0 0x1d0
+ MX8MM_IOMUXC_SD2_DATA1_USDHC2_DATA1 0x1d0
+ MX8MM_IOMUXC_SD2_DATA2_USDHC2_DATA2 0x1d0
+ MX8MM_IOMUXC_SD2_DATA3_USDHC2_DATA3 0x1d0
+ MX8MM_IOMUXC_GPIO1_IO04_USDHC2_VSELECT 0x1d0
+ >;
+ };
+
+ pinctrl_usdhc2_100mhz: usdhc2grp100mhz {
+ fsl,pins = <
+ MX8MM_IOMUXC_SD2_CLK_USDHC2_CLK 0x194
+ MX8MM_IOMUXC_SD2_CMD_USDHC2_CMD 0x1d4
+ MX8MM_IOMUXC_SD2_DATA0_USDHC2_DATA0 0x1d4
+ MX8MM_IOMUXC_SD2_DATA1_USDHC2_DATA1 0x1d4
+ MX8MM_IOMUXC_SD2_DATA2_USDHC2_DATA2 0x1d4
+ MX8MM_IOMUXC_SD2_DATA3_USDHC2_DATA3 0x1d4
+ MX8MM_IOMUXC_GPIO1_IO04_USDHC2_VSELECT 0x1d0
+ >;
+ };
+
+ pinctrl_usdhc2_200mhz: usdhc2grp200mhz {
+ fsl,pins = <
+ MX8MM_IOMUXC_SD2_CLK_USDHC2_CLK 0x196
+ MX8MM_IOMUXC_SD2_CMD_USDHC2_CMD 0x1d6
+ MX8MM_IOMUXC_SD2_DATA0_USDHC2_DATA0 0x1d6
+ MX8MM_IOMUXC_SD2_DATA1_USDHC2_DATA1 0x1d6
+ MX8MM_IOMUXC_SD2_DATA2_USDHC2_DATA2 0x1d6
+ MX8MM_IOMUXC_SD2_DATA3_USDHC2_DATA3 0x1d6
+ MX8MM_IOMUXC_GPIO1_IO04_USDHC2_VSELECT 0x1d0
+ >;
+ };
+
+ pinctrl_usdhc3: usdhc3grp {
+ fsl,pins = <
+ MX8MM_IOMUXC_NAND_WE_B_USDHC3_CLK 0x40000190
+ MX8MM_IOMUXC_NAND_WP_B_USDHC3_CMD 0x1d0
+ MX8MM_IOMUXC_NAND_DATA04_USDHC3_DATA0 0x1d0
+ MX8MM_IOMUXC_NAND_DATA05_USDHC3_DATA1 0x1d0
+ MX8MM_IOMUXC_NAND_DATA06_USDHC3_DATA2 0x1d0
+ MX8MM_IOMUXC_NAND_DATA07_USDHC3_DATA3 0x1d0
+ MX8MM_IOMUXC_NAND_RE_B_USDHC3_DATA4 0x1d0
+ MX8MM_IOMUXC_NAND_CE2_B_USDHC3_DATA5 0x1d0
+ MX8MM_IOMUXC_NAND_CE3_B_USDHC3_DATA6 0x1d0
+ MX8MM_IOMUXC_NAND_CLE_USDHC3_DATA7 0x1d0
+ MX8MM_IOMUXC_NAND_CE1_B_USDHC3_STROBE 0x190
+ >;
+ };
+
+ pinctrl_usdhc3_100mhz: usdhc3grp100mhz {
+ fsl,pins = <
+ MX8MM_IOMUXC_NAND_WE_B_USDHC3_CLK 0x40000194
+ MX8MM_IOMUXC_NAND_WP_B_USDHC3_CMD 0x1d4
+ MX8MM_IOMUXC_NAND_DATA04_USDHC3_DATA0 0x1d4
+ MX8MM_IOMUXC_NAND_DATA05_USDHC3_DATA1 0x1d4
+ MX8MM_IOMUXC_NAND_DATA06_USDHC3_DATA2 0x1d4
+ MX8MM_IOMUXC_NAND_DATA07_USDHC3_DATA3 0x1d4
+ MX8MM_IOMUXC_NAND_RE_B_USDHC3_DATA4 0x1d4
+ MX8MM_IOMUXC_NAND_CE2_B_USDHC3_DATA5 0x1d4
+ MX8MM_IOMUXC_NAND_CE3_B_USDHC3_DATA6 0x1d4
+ MX8MM_IOMUXC_NAND_CLE_USDHC3_DATA7 0x1d4
+ MX8MM_IOMUXC_NAND_CE1_B_USDHC3_STROBE 0x194
+ >;
+ };
+
+ pinctrl_usdhc3_200mhz: usdhc3grp200mhz {
+ fsl,pins = <
+ MX8MM_IOMUXC_NAND_WE_B_USDHC3_CLK 0x40000196
+ MX8MM_IOMUXC_NAND_WP_B_USDHC3_CMD 0x1d6
+ MX8MM_IOMUXC_NAND_DATA04_USDHC3_DATA0 0x1d6
+ MX8MM_IOMUXC_NAND_DATA05_USDHC3_DATA1 0x1d6
+ MX8MM_IOMUXC_NAND_DATA06_USDHC3_DATA2 0x1d6
+ MX8MM_IOMUXC_NAND_DATA07_USDHC3_DATA3 0x1d6
+ MX8MM_IOMUXC_NAND_RE_B_USDHC3_DATA4 0x1d6
+ MX8MM_IOMUXC_NAND_CE2_B_USDHC3_DATA5 0x1d6
+ MX8MM_IOMUXC_NAND_CE3_B_USDHC3_DATA6 0x1d6
+ MX8MM_IOMUXC_NAND_CLE_USDHC3_DATA7 0x1d6
+ MX8MM_IOMUXC_NAND_CE1_B_USDHC3_STROBE 0x196
+ >;
+ };
+
+ pinctrl_wdog: wdoggrp {
+ fsl,pins = <
+ MX8MM_IOMUXC_GPIO1_IO02_WDOG1_WDOG_B 0xc6
+ >;
+ };
+};
ret = thermal_get_temp(thermal_dev, &cpu_tmp);
if (!ret)
- printf(" at %dC\n", cpu_tmp);
+ printf(" at %dC", cpu_tmp);
else
debug(" - invalid sensor data\n");
} else {
debug(" - invalid sensor device\n");
}
+ puts("\n");
#endif
printf("Reset cause: %s\n", get_reset_cause());
select SUPPORT_SPL
select IMX8M_LPDDR4
+config TARGET_PHYCORE_IMX8MM
+ bool "PHYTEC PHYCORE i.MX8MM"
+ select IMX8MM
+ select SUPPORT_SPL
+ select IMX8M_LPDDR4
endchoice
source "board/freescale/imx8mq_evk/Kconfig"
source "board/technexion/pico-imx8mq/Kconfig"
source "board/toradex/verdin-imx8mm/Kconfig"
source "board/beacon/imx8mm/Kconfig"
+source "board/phytec/phycore_imx8mm/Kconfig"
endif
#endif
#ifdef CONFIG_MX53
+#define IMX53_SRTC_LPGR_PERSIST_SECONDARY_BOOT BIT(30)
+
void boot_mode_apply(unsigned cfg_val)
{
- writel(cfg_val, &((struct srtc_regs *)SRTC_BASE_ADDR)->lpgr);
+ void *lpgr = &((struct srtc_regs *)SRTC_BASE_ADDR)->lpgr;
+
+ if (cfg_val == MAKE_CFGVAL_PRIMARY_BOOT)
+ clrbits_le32(lpgr, IMX53_SRTC_LPGR_PERSIST_SECONDARY_BOOT);
+ else if (cfg_val == MAKE_CFGVAL_SECONDARY_BOOT)
+ setbits_le32(lpgr, IMX53_SRTC_LPGR_PERSIST_SECONDARY_BOOT);
+ else
+ writel(cfg_val, lpgr);
+}
+
+int boot_mode_getprisec(void)
+{
+ void *lpgr = &((struct srtc_regs *)SRTC_BASE_ADDR)->lpgr;
+
+ return !!(readl(lpgr) & IMX53_SRTC_LPGR_PERSIST_SECONDARY_BOOT);
}
+
/*
* cfg_val will be used for
* Boot_cfg3[7:0]:Boot_cfg2[7:0]:Boot_cfg1[7:0]
{"esdhc2", MAKE_CFGVAL(0x40, 0x20, 0x08, 0x12)},
{"esdhc3", MAKE_CFGVAL(0x40, 0x20, 0x10, 0x12)},
{"esdhc4", MAKE_CFGVAL(0x40, 0x20, 0x18, 0x12)},
+ {"primary", MAKE_CFGVAL_PRIMARY_BOOT},
+ {"secondary", MAKE_CFGVAL_SECONDARY_BOOT},
{NULL, 0},
};
#endif
depends on MX6Q
select BOARD_LATE_INIT
+config TARGET_GE_B1X5V2
+ bool "General Electric B1x5v2"
+ depends on MX6QDL
+ select BOARD_LATE_INIT
+ select DM
+ select DM_THERMAL
+ select SUPPORT_SPL
+
config TARGET_GW_VENTANA
bool "gw_ventana"
depends on MX6QDL
default "mx6"
source "board/ge/bx50v3/Kconfig"
+source "board/ge/b1x5v2/Kconfig"
source "board/advantech/dms-ba16/Kconfig"
source "board/aristainetos/Kconfig"
source "board/armadeus/opos6uldev/Kconfig"
}
#if defined(CONFIG_MX6Q) || defined(CONFIG_MX6D) || defined(CONFIG_MX6DL) || \
- defined(CONFIG_MX6S)
+ defined(CONFIG_MX6S) || defined(CONFIG_MX6QDL)
static void disable_ldb_di_clock_sources(void)
{
struct mxc_ccm_reg *mxc_ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR;
#include <imx_thermal.h>
#include <mmc.h>
+#define has_err007805() \
+ (is_mx6sl() || is_mx6dl() || is_mx6solo() || is_mx6ull())
+
struct scu_regs {
u32 ctrl;
u32 config;
}
/* Set perclk to source from OSC 24MHz */
- if (is_mx6sl())
+ if (has_err007805())
setbits_le32(&ccm->cscmr1, MXC_CCM_CSCMR1_PER_CLK_SEL_MASK);
imx_wdog_disable_powerdown(); /* Disable PDE bit of WMCR register */
int do_mx7_showclocks(struct cmd_tbl *cmdtp, int flag, int argc,
char *const argv[])
{
- u32 addr = 0;
+
u32 freq;
freq = decode_pll(PLL_A7_SPLL);
printf("PLL_A7_SPLL %8d MHz\n", freq / 1000000);
printf("PLL_A7_APLL %8d MHz\n", freq / 1000000);
freq = decode_pll(PLL_USB);
- printf("PLL_USB %8d MHz\n", freq / 1000000);
+ printf("PLL_USB %8d MHz\n", freq / 1000000);
printf("\n");
printf("USDHC2 %8d kHz\n", mxc_get_clock(MXC_ESDHC2_CLK) / 1000);
printf("I2C4 %8d kHz\n", mxc_get_clock(MXC_I2C_CLK) / 1000);
- addr = (u32) clock_init;
- printf("[%s] addr = 0x%08X\r\n", __func__, addr);
scg_a7_info();
return 0;
+++ /dev/null
-U-Boot for the NXP i.MX8MM EVK board
-
-Quick Start
-===========
-- Build the ARM Trusted firmware binary
-- Get ddr firmware
-- Build U-Boot
-- Boot
-
-Get and Build the ARM Trusted firmware
-======================================
-Note: builddir is U-Boot build directory (source directory for in-tree builds)
-Get ATF from: https://source.codeaurora.org/external/imx/imx-atf
-branch: imx_4.19.35_1.0.0
-$ make PLAT=imx8mm bl31
-$ cp build/imx8mm/release/bl31.bin $(builddir)
-
-Get the ddr firmware
-=============================
-$ wget https://www.nxp.com/lgfiles/NMG/MAD/YOCTO/firmware-imx-8.0.bin
-$ chmod +x firmware-imx-8.0.bin
-$ ./firmware-imx-8.0
-$ cp firmware-imx-8.0/firmware/ddr/synopsys/lpddr4*.bin $(builddir)
-
-Build U-Boot
-============
-$ export CROSS_COMPILE=aarch64-poky-linux-
-$ make imx8mm_evk_defconfig
-$ export ATF_LOAD_ADDR=0x920000
-$ make flash.bin
-
-Burn the flash.bin to MicroSD card offset 33KB
-$sudo dd if=flash.bin of=/dev/sd[x] bs=1024 seek=33
-
-Boot
-====
-Set Boot switch to SD boot
+++ /dev/null
-U-Boot for the NXP i.MX8MN EVK board
-
-Quick Start
-===========
-- Build the ARM Trusted firmware binary
-- Get firmware-imx package
-- Build U-Boot
-- Boot
-
-Get and Build the ARM Trusted firmware
-======================================
-Note: srctree is U-Boot source directory
-Get ATF from: https://source.codeaurora.org/external/imx/imx-atf
-branch: imx_4.19.35_1.1.0
-$ make PLAT=imx8mn bl31
-$ cp build/imx8mn/release/bl31.bin $(srctree)
-
-Get the ddr firmware
-=============================
-$ wget https://www.nxp.com/lgfiles/NMG/MAD/YOCTO/firmware-imx-8.5.bin
-$ chmod +x firmware-imx-8.5.bin
-$ ./firmware-imx-8.5
-$ cp firmware-imx-8.5/firmware/ddr/synopsys/ddr4*.bin $(srctree)
-
-Build U-Boot
-============
-$ export CROSS_COMPILE=aarch64-poky-linux-
-$ make imx8mn_ddr4_evk_defconfig
-$ export ATF_LOAD_ADDR=0x960000
-$ make flash.bin
-
-Burn the flash.bin to MicroSD card offset 32KB
-$sudo dd if=flash.bin of=/dev/sd[x] bs=1024 seek=32
-
-Boot
-====
-Set Boot switch to SD boot
+++ /dev/null
-U-Boot for the NXP i.MX8MP EVK board
-
-Quick Start
-===========
-- Build the ARM Trusted firmware binary
-- Get the firmware-imx package
-- Build U-Boot
-- Boot
-
-Get and Build the ARM Trusted firmware
-======================================
-Note: $(srctree) is the U-Boot source directory
-Get ATF from: https://source.codeaurora.org/external/imx/imx-atf
-branch: imx_5.4.3_2.0.0
-$ make PLAT=imx8mp bl31
-$ sudo cp build/imx8mp/release/bl31.bin $(srctree)
-
-Get the ddr firmware
-====================
-$ wget https://www.nxp.com/lgfiles/NMG/MAD/YOCTO/firmware-imx-8.7.bin
-$ chmod +x firmware-imx-8.7.bin
-$ ./firmware-imx-8.7
-$ sudo cp firmware-imx-8.7/firmware/ddr/synopsys/lpddr4_pmu_train_1d_dmem_201904.bin $(srctree)/lpddr4_pmu_train_1d_dmem.bin
-$ sudo cp firmware-imx-8.7/firmware/ddr/synopsys/lpddr4_pmu_train_1d_imem_201904.bin $(srctree)/lpddr4_pmu_train_1d_imem.bin
-$ sudo cp firmware-imx-8.7/firmware/ddr/synopsys/lpddr4_pmu_train_2d_dmem_201904.bin $(srctree)/lpddr4_pmu_train_2d_dmem.bin
-$ sudo cp firmware-imx-8.7/firmware/ddr/synopsys/lpddr4_pmu_train_2d_imem_201904.bin $(srctree)/lpddr4_pmu_train_2d_imem.bin
-
-Build U-Boot
-============
-$ export CROSS_COMPILE=aarch64-poky-linux-
-$ make imx8mp_evk_defconfig
-$ export ATF_LOAD_ADDR=0x960000
-$ make flash.bin
-
-Burn the flash.bin to the MicroSD card at offset 32KB
-$sudo dd if=flash.bin of=/dev/sd[x] bs=1K seek=32; sync
-
-Boot
-====
-Set Boot switch to SD boot
-Use /dev/ttyUSB2 for U-Boot console
+++ /dev/null
-U-Boot for the NXP i.MX8MQ EVK board
-
-Quick Start
-===========
-- Build the ARM Trusted firmware binary
-- Get ddr and hdmi fimware
-- Build U-Boot
-- Boot
-
-Get and Build the ARM Trusted firmware
-======================================
-Note: srctree is U-Boot source directory
-Get ATF from: https://source.codeaurora.org/external/imx/imx-atf
-branch: imx_4.19.35_1.0.0
-$ make PLAT=imx8mq bl31
-$ cp build/imx8mq/release/bl31.bin $(builddir)
-
-Get the ddr and hdmi firmware
-=============================
-$ wget https://www.nxp.com/lgfiles/NMG/MAD/YOCTO/firmware-imx-7.9.bin
-$ chmod +x firmware-imx-7.9.bin
-$ ./firmware-imx-7.9.bin
-$ cp firmware-imx-7.9/firmware/hdmi/cadence/signed_hdmi_imx8m.bin $(builddir)
-$ cp firmware-imx-7.9/firmware/ddr/synopsys/lpddr4*.bin $(builddir)
-
-Build U-Boot
-============
-$ export CROSS_COMPILE=aarch64-poky-linux-
-$ make imx8mq_evk_defconfig
-$ make flash.bin
-
-Burn the flash.bin to MicroSD card offset 33KB
-$sudo dd if=flash.bin of=/dev/sd[x] bs=1024 seek=33
-
-Boot
-====
-Set Boot switch SW801: 1100 and Bmode: 10 to boot from Micro SD.
+++ /dev/null
-U-Boot for the NXP i.MX8QXP EVK board
-
-Quick Start
-===========
-
-- Build the ARM Trusted firmware binary
-- Get scfw_tcm.bin and ahab-container.img
-- Build U-Boot
-- Flash the binary into the SD card
-- Boot
-
-Get and Build the ARM Trusted firmware
-======================================
-
-$ git clone https://source.codeaurora.org/external/imx/imx-atf
-$ cd imx-atf/
-$ git checkout origin/imx_4.19.35_1.1.0 -b imx_4.19.35_1.1.0
-$ make PLAT=imx8qx bl31
-
-Get scfw_tcm.bin and ahab-container.img
-==============================
-
-$ wget https://www.nxp.com/lgfiles/NMG/MAD/YOCTO/imx-sc-firmware-1.2.7.1.bin
-$ chmod +x imx-sc-firmware-1.2.7.1.bin
-$ ./imx-sc-firmware-1.2.7.1.bin
-$ wget https://www.nxp.com/lgfiles/NMG/MAD/YOCTO/imx-seco-2.3.1.bin
-$ chmod +x imx-seco-2.3.1.bin
-$ ./imx-seco-2.3.1.bin
-
-Copy the following binaries to U-Boot folder:
-
-$ cp imx-atf/build/imx8qx/release/bl31.bin .
-$ cp imx-seco-2.3.1/firmware/seco/mx8qx-ahab-container.img ./ahab-container.img
-$ cp imx-sc-firmware-1.2.7.1/mx8qx-mek-scfw-tcm.bin .
-
-Build U-Boot
-============
-$ make imx8qxp_mek_defconfig
-$ make flash.bin
-
-Flash the binary into the SD card
-=================================
-
-Burn the flash.bin binary to SD card offset 32KB:
-
-$ sudo dd if=flash.bin of=/dev/sd[x] bs=1024 seek=32
-
-Boot
-====
-Set Boot switch SW2: 1100.
+++ /dev/null
-How to use U-Boot on NXP i.MXRT1020 EVK
------------------------------------------------
-
-- Build U-Boot for i.MXRT1020 EVK:
-
-$ make mrproper
-$ make imxrt1020-evk_defconfig
-$ make
-
-This will generate the SPL image called SPL and the u-boot.img.
-
-- Flash the SPL image into the micro SD card:
-
-sudo dd if=SPL of=/dev/sdX bs=1k seek=1; sync
-
-- Flash the u-boot.img image into the micro SD card:
-
-sudo dd if=u-boot.img of=/dev/sdX bs=1k seek=128; sync
-
-- Jumper settings:
-
-SW8: 0 1 1 0
-
-where 0 means bottom position and 1 means top position (from the
-switch label numbers reference).
-
-- Connect the USB cable between the EVK and the PC for the console.
-(The USB console connector is the one close the ethernet connector)
-
-- Insert the micro SD card in the board, power it up and U-Boot messages should
-come up.
+++ /dev/null
-How to use U-Boot on NXP i.MXRT1050 EVK
------------------------------------------------
-
-- Build U-Boot for i.MXRT1050 EVK:
-
-$ make mrproper
-$ make imxrt1050-evk_defconfig
-$ make
-
-This will generate the SPL image called SPL and the u-boot.img.
-
-- Flash the SPL image into the micro SD card:
-
-sudo dd if=SPL of=/dev/sdX bs=1k seek=1; sync
-
-- Flash the u-boot.img image into the micro SD card:
-
-sudo dd if=u-boot.img of=/dev/sdX bs=1k seek=128; sync
-
-- Jumper settings:
-
-SW7: 1 0 1 0
-
-where 0 means bottom position and 1 means top position (from the
-switch label numbers reference).
-
-- Connect the USB cable between the EVK and the PC for the console.
-(The USB console connector is the one close the ethernet connector)
-
-- Insert the micro SD card in the board, power it up and U-Boot messages should
-come up.
+++ /dev/null
-How to use and build U-Boot on mx6sabreauto
--------------------------------------------
-
-mx6sabreauto_defconfig target supports mx6q/mx6dl/mx6qp sabreauto variants.
-
-In order to build it:
-
-$ make mx6sabreauto_defconfig
-
-$ make
-
-This will generate the SPL and u-boot-dtb.img binaries.
-
-- Flash the SPL binary into the SD card:
-
-$ sudo dd if=SPL of=/dev/sdX bs=1K seek=1 && sync
-
-- Flash the u-boot-dtb.img binary into the SD card:
-
-$ sudo dd if=u-boot-dtb.img of=/dev/sdX bs=1K seek=69 && sync
-
-Booting via Falcon mode
------------------------
-
-Write in mx6sabreauto_defconfig the following define below:
-
-CONFIG_SPL_OS_BOOT=y
-
-In order to build it:
-
-$ make mx6sabreauto_defconfig
-
-$ make
-
-This will generate the SPL image called SPL and the u-boot-dtb.img.
-
-- Flash the SPL image into the SD card:
-
-$ sudo dd if=SPL of=/dev/sdb bs=1K seek=1 && sync
-
-- Flash the u-boot-dtb.img image into the SD card:
-
-$ sudo dd if=u-boot-dtb.img of=/dev/sdb bs=1K seek=69 && sync
-
-Create a FAT16 boot partition to store uImage and the dtb file, then copy the files there:
-
-$ sudo cp uImage /media/boot
-
-$ sudo cp imx6dl-sabreauto.dtb /media/boot
-
-Create a partition for root file system and extract it there:
-
-$ sudo tar xvf rootfs.tar.gz -C /media/root
-
-The SD card must have enough space for raw "args" and "kernel".
-To configure Falcon mode for the first time, on U-Boot do the following commands:
-
-- Load dtb file from boot partition:
-
-# load mmc 0:1 ${fdt_addr} imx6dl-sabreauto.dtb
-
-- Load kernel image from boot partition:
-
-# load mmc 0:1 ${loadaddr} uImage
-
-- Write kernel at 2MB offset:
-
-# mmc write ${loadaddr} 0x1000 0x4000
-
-- Setup kernel bootargs:
-
-# setenv bootargs "console=ttymxc3,115200 root=/dev/mmcblk0p1 rootfstype=ext4 rootwait quiet rw"
-
-- Prepare args:
-
-# spl export fdt ${loadaddr} - ${fdt_addr}
-
-- Write args 1MB data (0x800 sectors) to 1MB offset (0x800 sectors)
-
-# mmc write 18000000 0x800 0x800
-
-- Restart the board and then SPL binary will launch the kernel directly.
+++ /dev/null
-How to use and build U-Boot on mx6sabresd
------------------------------------------
-
-The following methods can be used for booting mx6sabresd boards:
-
-1. Booting from SD card
-
-2. Booting from eMMC
-
-3. Booting via Falcon mode (SPL launches the kernel directly)
-
-
-1. Booting from SD card via SPL
--------------------------------
-
-mx6sabresd_defconfig target supports mx6q/mx6dl/mx6qp sabresd variants.
-
-In order to build it:
-
-$ make mx6sabresd_defconfig
-
-$ make
-
-This will generate the SPL and u-boot-dtb.img binaries.
-
-- Flash the SPL binary into the SD card:
-
-$ sudo dd if=SPL of=/dev/sdX bs=1K seek=1 && sync
-
-- Flash the u-boot-dtb.img binary into the SD card:
-
-$ sudo dd if=u-boot-dtb.img of=/dev/sdX bs=1K seek=69 && sync
-
-
-2. Booting from eMMC
---------------------
-
-$ make mx6sabresd_defconfig
-
-$ make
-
-This will generate the SPL and u-boot-dtb.img binaries.
-
-- Boot first from SD card as shown in the previous section
-
-In U-boot change the eMMC partition config:
-
-=> mmc partconf 2 1 0 0
-
-Mount the eMMC in the host PC:
-
-=> ums 0 mmc 2
-
-- Flash SPL and u-boot-dtb.img binaries into the eMMC:
-
-$ sudo dd if=SPL of=/dev/sdX bs=1K seek=1 && sync
-$ sudo dd if=u-boot-dtb.img of=/dev/sdX bs=1K seek=69 && sync
-
-Set SW6 to eMMC 8-bit boot: 11010110
-
-
-3. Booting via Falcon mode
---------------------------
-
-$ make mx6sabresd_defconfig
-$ make
-
-This will generate the SPL image called SPL and the u-boot-dtb.img.
-
-- Flash the SPL image into the SD card:
-
-$ sudo dd if=SPL of=/dev/sdX bs=1K seek=1 oflag=sync status=none && sync
-
-- Flash the u-boot-dtb.img image into the SD card:
-
-$ sudo dd if=u-boot-dtb.img of=/dev/sdX bs=1K seek=69 oflag=sync status=none && sync
-
-Create a partition for root file system and extract it there:
-
-$ sudo tar xvf rootfs.tar.gz -C /media/root
-
-The SD card must have enough space for raw "args" and "kernel".
-To configure Falcon mode for the first time, on U-Boot do the following commands:
-
-- Setup the IP server:
-
-# setenv serverip <server_ip_address>
-
-- Download dtb file:
-
-# dhcp ${fdt_addr} imx6q-sabresd.dtb
-
-- Download kernel image:
-
-# dhcp ${loadaddr} uImage
-
-- Write kernel at 2MB offset:
-
-# mmc write ${loadaddr} 0x1000 0x4000
-
-- Setup kernel bootargs:
-
-# setenv bootargs "console=ttymxc0,115200 root=/dev/mmcblk1p1 rootfstype=ext4 rootwait quiet rw"
-
-- Prepare args:
-
-# spl export fdt ${loadaddr} - ${fdt_addr}
-
-- Write args 1MB data (0x800 sectors) to 1MB offset (0x800 sectors)
-
-# mmc write 18000000 0x800 0x800
-
-- Press KEY_VOL_UP key, power up the board and then SPL binary will
-launch the kernel directly.
--- /dev/null
+if TARGET_GE_B1X5V2
+
+config SYS_BOARD
+ default "b1x5v2"
+
+config SYS_VENDOR
+ default "ge"
+
+config SYS_CONFIG_NAME
+ default "ge_b1x5v2"
+
+source "board/ge/common/Kconfig"
+
+endif
--- /dev/null
+GE B1X5V2 BOARD
+M: Huan 'Kitty' Wang <HuanWang@ge.com>
+M: Ian Ray <ian.ray@ge.com>
+M: Sebastian Reichel <sebastian.reichel@collabora.com>
+S: Maintained
+F: arch/arm/dts/imx6dl-b1x5v2.dts
+F: board/ge/b1x5v2/
+F: configs/ge_b1x5v2_defconfig
+F: include/configs/ge_b1x5v2.h
--- /dev/null
+# SPDX-License-Identifier: GPL-2.0+
+#
+# Copyright 2018-2020 Collabora
+# Copyright 2018-2020 GE
+
+obj-y := b1x5v2.o spl.o
--- /dev/null
+/*
+ * GE B105v2, B125v2, B155v2
+ *
+ * Copyright 2018-2020 GE Inc.
+ * Copyright 2018-2020 Collabora Ltd.
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <asm/arch/clock.h>
+#include <asm/arch/crm_regs.h>
+#include <asm/arch/imx-regs.h>
+#include <asm/arch/iomux.h>
+#include <asm/arch/sys_proto.h>
+#include <asm/gpio.h>
+#include <asm/io.h>
+#include <asm/mach-imx/video.h>
+#include <command.h>
+#include <common.h>
+#include <i2c.h>
+#include <input.h>
+#include <ipu_pixfmt.h>
+#include <linux/delay.h>
+#include <linux/fb.h>
+#include <malloc.h>
+#include <miiphy.h>
+#include <micrel.h>
+#include <netdev.h>
+#include <panel.h>
+#include <rtc.h>
+#include <spi_flash.h>
+#include <version.h>
+
+#include "../common/vpd_reader.h"
+
+DECLARE_GLOBAL_DATA_PTR;
+
+#ifndef CONFIG_SPL_BUILD
+
+#define B1X5V2_GE_VPD_OFFSET 0x0100000
+#define B1X5V2_GE_VPD_SIZE 1022
+
+#define VPD_TYPE_INVALID 0x00
+#define VPD_BLOCK_NETWORK 0x20
+#define VPD_BLOCK_HWID 0x44
+#define VPD_MAC_ADDRESS_LENGTH 6
+
+#define VPD_FLAG_VALID_MAC BIT(1)
+
+#define AR8035_PHY_ID 0x004dd072
+#define AR8035_PHY_DEBUG_ADDR_REG 0x1d
+#define AR8035_PHY_DEBUG_DATA_REG 0x1e
+#define AR8035_HIB_CTRL_REG 0xb
+#define AR8035_HIBERNATE_EN (1 << 15)
+
+static struct vpd_cache {
+ bool is_read;
+ u8 product_id;
+ unsigned char mac[VPD_MAC_ADDRESS_LENGTH];
+ u32 flags;
+} vpd;
+
+enum product_type {
+ PRODUCT_TYPE_B105V2 = 6,
+ PRODUCT_TYPE_B105PV2 = 7,
+ PRODUCT_TYPE_B125V2 = 8,
+ PRODUCT_TYPE_B125PV2 = 9,
+ PRODUCT_TYPE_B155V2 = 10,
+
+ PRODUCT_TYPE_INVALID = 0,
+};
+
+int dram_init(void) {
+ gd->ram_size = imx_ddr_size();
+ return 0;
+}
+
+int power_init_board(void)
+{
+ /* all required PMIC configuration happens via DT */
+ return 0;
+}
+
+static int disable_phy_hibernation(struct phy_device *phydev)
+{
+ unsigned short val;
+
+ if (phydev->drv->uid == AR8035_PHY_ID) {
+ /* Disable hibernation, other configuration has been done by PHY driver */
+ phy_write(phydev, MDIO_DEVAD_NONE, AR8035_PHY_DEBUG_ADDR_REG, AR8035_HIB_CTRL_REG);
+ val = phy_read(phydev, MDIO_DEVAD_NONE, AR8035_PHY_DEBUG_DATA_REG);
+ val &= ~AR8035_HIBERNATE_EN;
+ phy_write(phydev, MDIO_DEVAD_NONE, AR8035_PHY_DEBUG_DATA_REG, val);
+ } else {
+ printf("Unknown PHY: %08x\n", phydev->drv->uid);
+ }
+
+ return 0;
+}
+
+int board_phy_config(struct phy_device *phydev)
+{
+ if (phydev->drv->config)
+ phydev->drv->config(phydev);
+
+ disable_phy_hibernation(phydev);
+
+ return 0;
+}
+
+static int auo_g101evn01_detect(const struct display_info_t *info)
+{
+ char *dev = env_get("devicetype");
+ return !strcmp(dev, "B105v2") || !strcmp(dev, "B105Pv2");
+}
+
+static int auo_g121ean01_detect(const struct display_info_t *info)
+{
+ char *dev = env_get("devicetype");
+ return !strcmp(dev, "B125v2") || !strcmp(dev, "B125Pv2");;
+}
+
+static int auo_g156xtn01_detect(const struct display_info_t *info)
+{
+ char *dev = env_get("devicetype");
+ return !strcmp(dev, "B155v2");
+}
+
+static void b1x5v2_backlight_enable(int percent)
+{
+ struct udevice *panel;
+ int ret;
+
+ ret = uclass_get_device(UCLASS_PANEL, 0, &panel);
+ if (ret) {
+ printf("Could not find panel: %d\n", ret);
+ return;
+ }
+
+ panel_set_backlight(panel, percent);
+ panel_enable_backlight(panel);
+
+}
+
+static void lcd_enable(const struct display_info_t *info)
+{
+ printf("Enable backlight...\n");
+ b1x5v2_backlight_enable(100);
+}
+
+struct display_info_t const displays[] = {
+{
+ .di = 0,
+ .bus = -1,
+ .addr = -1,
+ .pixfmt = IPU_PIX_FMT_RGB24,
+ .detect = auo_g156xtn01_detect,
+ .enable = lcd_enable,
+ .mode = {
+ .name = "AUO G156XTN01",
+ .refresh = 60,
+ .xres = 1368, /* because of i.MX6 limitation, actually 1366 */
+ .yres = 768,
+ .pixclock = 13158, /* 76 MHz in ps */
+ .left_margin = 33,
+ .right_margin = 67,
+ .upper_margin = 4,
+ .lower_margin = 4,
+ .hsync_len = 94,
+ .vsync_len = 30,
+ .sync = FB_SYNC_EXT,
+ .vmode = FB_VMODE_NONINTERLACED
+ }
+},
+{
+ .di = 0,
+ .bus = -1,
+ .addr = -1,
+ .pixfmt = IPU_PIX_FMT_RGB24,
+ .detect = auo_g121ean01_detect,
+ .enable = lcd_enable,
+ .mode = {
+ .name = "AUO G121EAN01.4",
+ .refresh = 60,
+ .xres = 1280,
+ .yres = 800,
+ .pixclock = 14992, /* 66.7 MHz in ps */
+ .left_margin = 8,
+ .right_margin = 58,
+ .upper_margin = 6,
+ .lower_margin = 4,
+ .hsync_len = 70,
+ .vsync_len = 10,
+ .sync = FB_SYNC_EXT,
+ .vmode = FB_VMODE_NONINTERLACED
+ }
+},
+{
+ .di = 0,
+ .bus = -1,
+ .addr = -1,
+ .pixfmt = IPU_PIX_FMT_RGB24,
+ .detect = auo_g101evn01_detect,
+ .enable = lcd_enable,
+ .mode = {
+ .name = "AUO G101EVN01.3",
+ .refresh = 60,
+ .xres = 1280,
+ .yres = 800,
+ .pixclock = 14992, /* 66.7 MHz in ps */
+ .left_margin = 8,
+ .right_margin = 58,
+ .upper_margin = 6,
+ .lower_margin = 4,
+ .hsync_len = 70,
+ .vsync_len = 10,
+ .sync = FB_SYNC_EXT,
+ .vmode = FB_VMODE_NONINTERLACED
+ }
+}
+};
+size_t display_count = ARRAY_SIZE(displays);
+
+static void enable_videopll(void)
+{
+ struct mxc_ccm_reg *ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR;
+ s32 timeout = 100000;
+
+ setbits_le32(&ccm->analog_pll_video, BM_ANADIG_PLL_VIDEO_POWERDOWN);
+
+ /* PLL_VIDEO 455MHz (24MHz * (37+11/12) / 2)
+ * |
+ * PLL5
+ * |
+ * CS2CDR[LDB_DI0_CLK_SEL]
+ * |
+ * +----> LDB_DI0_SERIAL_CLK_ROOT
+ * |
+ * +--> CSCMR2[LDB_DI0_IPU_DIV] --> LDB_DI0_IPU 455 / 7 = 65 MHz
+ */
+
+ clrsetbits_le32(&ccm->analog_pll_video,
+ BM_ANADIG_PLL_VIDEO_DIV_SELECT |
+ BM_ANADIG_PLL_VIDEO_POST_DIV_SELECT,
+ BF_ANADIG_PLL_VIDEO_DIV_SELECT(37) |
+ BF_ANADIG_PLL_VIDEO_POST_DIV_SELECT(1));
+
+ writel(BF_ANADIG_PLL_VIDEO_NUM_A(11), &ccm->analog_pll_video_num);
+ writel(BF_ANADIG_PLL_VIDEO_DENOM_B(12), &ccm->analog_pll_video_denom);
+
+ clrbits_le32(&ccm->analog_pll_video, BM_ANADIG_PLL_VIDEO_POWERDOWN);
+
+ while (timeout--)
+ if (readl(&ccm->analog_pll_video) & BM_ANADIG_PLL_VIDEO_LOCK)
+ break;
+
+ if (timeout < 0)
+ printf("Warning: video pll lock timeout!\n");
+
+ clrsetbits_le32(&ccm->analog_pll_video,
+ BM_ANADIG_PLL_VIDEO_BYPASS,
+ BM_ANADIG_PLL_VIDEO_ENABLE);
+}
+
+static void setup_display(void)
+{
+ struct mxc_ccm_reg *mxc_ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR;
+ struct iomuxc *iomux = (struct iomuxc *)IOMUXC_BASE_ADDR;
+
+ enable_videopll();
+
+ /* When a reset/reboot is performed the display power needs to be turned
+ * off for atleast 500ms. The boot time is ~300ms, we need to wait for
+ * an additional 200ms here. Unfortunately we use external PMIC for
+ * doing the reset, so can not differentiate between POR vs soft reset
+ */
+ mdelay(200);
+
+ /* CCM_CSCMR2 -> ldb_di0_ipu_div [IMX6SDLRM page 839] */
+ /* divide IPU clock by 7 */
+ setbits_le32(&mxc_ccm->cscmr2, MXC_CCM_CSCMR2_LDB_DI0_IPU_DIV);
+
+ /* CCM_CHSCCDR -> ipu1_di0_clk_sel [IMX6SDLRM page 849] */
+ /* Set LDB_DI0 as clock source for IPU_DI0 */
+ clrsetbits_le32(&mxc_ccm->chsccdr,
+ MXC_CCM_CHSCCDR_IPU1_DI0_CLK_SEL_MASK,
+ (CHSCCDR_CLK_SEL_LDB_DI0 <<
+ MXC_CCM_CHSCCDR_IPU1_DI0_CLK_SEL_OFFSET));
+
+ /* Turn on IPU LDB DI0 clocks */
+ setbits_le32(&mxc_ccm->CCGR3, MXC_CCM_CCGR3_LDB_DI0_MASK);
+
+ enable_ipu_clock();
+
+ /* IOMUXC_GPR2 [IMX6SDLRM page 2049] */
+ /* Set LDB Channel 0 in SPWG 24 Bit mode */
+ writel(IOMUXC_GPR2_DI0_VS_POLARITY_ACTIVE_HIGH |
+ IOMUXC_GPR2_BIT_MAPPING_CH0_SPWG |
+ IOMUXC_GPR2_DATA_WIDTH_CH0_24BIT |
+ IOMUXC_GPR2_LVDS_CH0_MODE_ENABLED_DI0,
+ &iomux->gpr[2]);
+
+ /* IOMUXC_GPR3 [IMX6SDLRM page 2051] */
+ /* LVDS0 is connected to IPU DI0 */
+ clrsetbits_le32(&iomux->gpr[3],
+ IOMUXC_GPR3_LVDS0_MUX_CTL_MASK,
+ (IOMUXC_GPR3_MUX_SRC_IPU1_DI0 <<
+ IOMUXC_GPR3_LVDS0_MUX_CTL_OFFSET));
+}
+
+/*
+ * Do not overwrite the console
+ * Use always serial for U-Boot console
+ */
+int overwrite_console(void)
+{
+ return 1;
+}
+
+int board_early_init_f(void)
+{
+ select_ldb_di_clock_source(MXC_PLL5_CLK);
+
+ return 0;
+}
+
+static int eeti_touch_get_model(struct udevice *dev, char *result) {
+ u8 query[68] = {0x67, 0x00, 0x42, 0x00, 0x03, 0x01, 'E', 0x00, 0x00, 0x00};
+ struct i2c_msg qmsg = {
+ .addr = 0x2a,
+ .flags = 0,
+ .len = sizeof(query),
+ .buf = query,
+ };
+ u8 reply[66] = {0};
+ struct i2c_msg rmsg = {
+ .addr = 0x2a,
+ .flags = I2C_M_RD,
+ .len = sizeof(reply),
+ .buf = reply,
+ };
+ int err;
+
+ err = dm_i2c_xfer(dev, &qmsg, 1);
+ if (err)
+ return err;
+
+ /*
+ * device sends IRQ when its ok to read. To keep the code
+ * simple we just wait an arbitrary, long enough time period.
+ */
+ mdelay(10);
+
+ err = dm_i2c_xfer(dev, &rmsg, 1);
+ if (err)
+ return err;
+
+ if (reply[0] != 0x42 || reply[1] != 0x00 ||
+ reply[2] != 0x03 || reply[4] != 'E')
+ return -EPROTO;
+
+ memcpy(result, reply+5, 10);
+ return 0;
+}
+
+static bool b1x5v2_board_is_p_model(void)
+{
+ struct udevice *bus = NULL;
+ struct udevice *dev = NULL;
+ int err;
+
+ err = uclass_get_device_by_name(UCLASS_I2C, "i2c@21a0000", &bus);
+ if (err || !bus) {
+ printf("Could not get I2C bus: %d\n", err);
+ return true;
+ }
+
+ /* The P models do not have this port expander */
+ err = dm_i2c_probe(bus, 0x21, 0, &dev);
+ if (err || !dev) {
+ return true;
+ }
+
+ return false;
+}
+
+static enum product_type b1x5v2_board_type(void)
+{
+ struct udevice *bus = NULL;
+ struct udevice *dev = NULL;
+ char model[11] = {0};
+ int err;
+ int retry;
+
+ err = uclass_get_device_by_name(UCLASS_I2C, "i2c@21a8000", &bus);
+ if (err) {
+ printf("Could not get I2C bus: %d\n", err);
+ return PRODUCT_TYPE_INVALID;
+ }
+
+ err = dm_i2c_probe(bus, 0x41, 0, &dev);
+ if (!err && dev) { /* Ilitek Touchscreen */
+ if (b1x5v2_board_is_p_model()) {
+ return PRODUCT_TYPE_B105PV2;
+ } else {
+ return PRODUCT_TYPE_B105V2;
+ }
+ }
+
+ err = dm_i2c_probe(bus, 0x2a, 0, &dev);
+ if (err || !dev) {
+ printf("Could not find touchscreen: %d\n", err);
+ return PRODUCT_TYPE_INVALID;
+ }
+
+ for (retry = 0; retry < 3; ++retry) {
+ err = eeti_touch_get_model(dev, model);
+ if (!err)
+ break;
+ printf("Retry %d read EETI touchscreen model: %d\n", retry + 1, err);
+ }
+ if (err) {
+ printf("Could not read EETI touchscreen model: %d\n", err);
+ return PRODUCT_TYPE_INVALID;
+ }
+
+ if (!strcmp(model, "Orion_1320")) { /* EETI EXC80H60 */
+ if (b1x5v2_board_is_p_model()) {
+ return PRODUCT_TYPE_B125PV2;
+ } else {
+ return PRODUCT_TYPE_B125V2;
+ }
+ } else if (!strcmp(model, "Orion_1343")) { /* EETI EXC80H84 */
+ return PRODUCT_TYPE_B155V2;
+ }
+
+ printf("Unknown EETI touchscreen model: %s\n", model);
+ return PRODUCT_TYPE_INVALID;
+}
+
+static void set_env_per_board_type(enum product_type type)
+{
+ switch (type) {
+ case PRODUCT_TYPE_B105V2:
+ env_set("resolution", "1280x800");
+ env_set("devicetype", "B105v2");
+ env_set("fdtfile", "imx6dl-b105v2.dtb");
+ break;
+ case PRODUCT_TYPE_B105PV2:
+ env_set("resolution", "1280x800");
+ env_set("devicetype", "B105Pv2");
+ env_set("fdtfile", "imx6dl-b105pv2.dtb");
+ break;
+ case PRODUCT_TYPE_B125V2:
+ env_set("resolution", "1280x800");
+ env_set("devicetype", "B125v2");
+ env_set("fdtfile", "imx6dl-b125v2.dtb");
+ break;
+ case PRODUCT_TYPE_B125PV2:
+ env_set("resolution", "1280x800");
+ env_set("devicetype", "B125Pv2");
+ env_set("fdtfile", "imx6dl-b125pv2.dtb");
+ break;
+ case PRODUCT_TYPE_B155V2:
+ env_set("resolution", "1366x768");
+ env_set("devicetype", "B155v2");
+ env_set("fdtfile", "imx6dl-b155v2.dtb");
+ break;
+ default:
+ break;
+ }
+}
+
+static int b1x5v2_board_type_autodetect(void)
+{
+ enum product_type product = b1x5v2_board_type();
+ if (product != PRODUCT_TYPE_INVALID) {
+ set_env_per_board_type(product);
+ return 0;
+ }
+ return -1;
+}
+
+/*
+ * Extracts MAC and product information from the VPD.
+ */
+static int vpd_callback(struct vpd_cache *vpd, u8 id, u8 version, u8 type,
+ size_t size, u8 const *data)
+{
+ if (type == VPD_TYPE_INVALID)
+ return 0;
+
+ if (id == VPD_BLOCK_HWID && version == 1 && size >= 1) {
+ vpd->product_id = data[0];
+ } else if (id == VPD_BLOCK_NETWORK && version == 1) {
+ if (size >= VPD_MAC_ADDRESS_LENGTH) {
+ memcpy(vpd->mac, data, VPD_MAC_ADDRESS_LENGTH);
+ vpd->flags |= VPD_FLAG_VALID_MAC;
+ }
+ }
+
+ return 0;
+}
+
+static int read_spi_vpd(struct vpd_cache *cache,
+ int (*process_block)(struct vpd_cache *, u8 id, u8 version,
+ u8 type, size_t size, u8 const *data))
+{
+ static const int size = B1X5V2_GE_VPD_SIZE;
+ struct udevice *dev;
+ int ret;
+ u8 *data;
+
+ ret = uclass_get_device_by_name(UCLASS_SPI_FLASH, "m25p80@0", &dev);
+ if (ret)
+ return ret;
+
+ data = malloc(size);
+ if (!data)
+ return -ENOMEM;
+
+ ret = spi_flash_read_dm(dev, B1X5V2_GE_VPD_OFFSET, size, data);
+ if (ret) {
+ free(data);
+ return ret;
+ }
+
+ ret = vpd_reader(size, data, cache, process_block);
+
+ free(data);
+
+ return ret;
+}
+
+int board_init(void)
+{
+ if (!read_spi_vpd(&vpd, vpd_callback)) {
+ vpd.is_read = true;
+ }
+
+ /* address of boot parameters */
+ gd->bd->bi_boot_params = PHYS_SDRAM + 0x100;
+ setup_display();
+
+ return 0;
+}
+
+static void init_bootcause(void)
+{
+ const char *cause;
+
+ /* We care about WDOG only, treating everything else as
+ * a power-on-reset.
+ */
+ if (get_imx_reset_cause() & 0x0010)
+ cause = "WDOG";
+ else
+ cause = "POR";
+
+ env_set("bootcause", cause);
+}
+
+int misc_init_r(void)
+{
+ init_bootcause();
+
+ return 0;
+}
+
+#define M41T62_REG_FLAGS 0xf
+#define M41T62_FLAGS_OF (1 << 2)
+static void check_time(void)
+{
+ struct udevice *rtc = NULL;
+ struct rtc_time tm;
+ u8 val;
+ int ret;
+
+ ret = uclass_get_device_by_name(UCLASS_RTC, "m41t62@68", &rtc);
+ if (ret) {
+ printf("Could not get RTC: %d\n", ret);
+ env_set("rtc_status", "FAIL");
+ return;
+ }
+
+ ret = dm_i2c_read(rtc, M41T62_REG_FLAGS, &val, sizeof(val));
+ if (ret) {
+ printf("Could not read RTC register: %d\n", ret);
+ env_set("rtc_status", "FAIL");
+ return;
+ }
+
+ ret = dm_rtc_reset(rtc);
+ if (ret) {
+ printf("Could not reset RTC: %d\n", ret);
+ env_set("rtc_status", "FAIL");
+ return;
+ }
+
+ if (val & M41T62_FLAGS_OF) {
+ env_set("rtc_status", "STOP");
+ return;
+ }
+
+ ret = dm_rtc_get(rtc, &tm);
+ if (ret) {
+ printf("Could not read RTC: %d\n", ret);
+ env_set("rtc_status", "FAIL");
+ return;
+ }
+
+ if (tm.tm_year > 2037) {
+ tm.tm_sec = 0;
+ tm.tm_min = 0;
+ tm.tm_hour = 0;
+ tm.tm_mday = 1;
+ tm.tm_wday = 2;
+ tm.tm_mon = 1;
+ tm.tm_year = 2036;
+
+ ret = dm_rtc_set(rtc, &tm);
+ if (ret) {
+ printf("Could not update RTC: %d\n", ret);
+ env_set("rtc_status", "FAIL");
+ return;
+ }
+
+ printf("RTC behind 2037, capped to 2036 for userspace handling\n");
+ env_set("rtc_status", "2038");
+ return;
+ }
+
+ env_set("rtc_status", "OK");
+}
+
+static void process_vpd(struct vpd_cache *vpd)
+{
+ if (!vpd->is_read) {
+ printf("VPD wasn't read\n");
+ return;
+ }
+
+ if (vpd->flags & VPD_FLAG_VALID_MAC) {
+ eth_env_set_enetaddr_by_index("eth", 0, vpd->mac);
+ env_set("ethact", "eth0");
+ }
+}
+
+int board_late_init(void)
+{
+ process_vpd(&vpd);
+
+ if (vpd.product_id >= PRODUCT_TYPE_B105V2 &&
+ vpd.product_id <= PRODUCT_TYPE_B155V2) {
+ set_env_per_board_type((enum product_type)vpd.product_id);
+ } else {
+ b1x5v2_board_type_autodetect();
+ }
+
+ printf("Board: GE %s\n", env_get("devicetype"));
+
+ check_time();
+
+ return 0;
+}
+
+#ifdef CONFIG_OF_BOARD_SETUP
+int ft_board_setup(void *blob, struct bd_info *bd)
+{
+ char *rtc_status = env_get("rtc_status");
+
+ fdt_setprop(blob, 0, "ge,boot-ver", version_string,
+ strlen(version_string) + 1);
+ fdt_setprop(blob, 0, "ge,rtc-status", rtc_status,
+ strlen(rtc_status) + 1);
+
+ return 0;
+}
+#endif
+
+static int do_b1x5v2_autodetect(struct cmd_tbl *cmdtp, int flag, int argc, char * const argv[])
+{
+ int err;
+
+ err = b1x5v2_board_type_autodetect();
+ if (!err)
+ printf("Identified %s\n", env_get("devicetype"));
+
+ return 0;
+}
+
+U_BOOT_CMD(
+ autodetect_devtype, 1, 1, do_b1x5v2_autodetect,
+ "autodetect b1x5v2 device type",
+ ""
+);
+
+#endif // CONFIG_SPL_BUILD
--- /dev/null
+/*
+ * GE b1x5v2 - QMX6 SPL
+ *
+ * Copyright 2013, Adeneo Embedded <www.adeneo-embedded.com>
+ * Copyright 2018-2020 GE Inc.
+ * Copyright 2018-2020 Collabora Ltd.
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <asm/arch/clock.h>
+#include <asm/arch/crm_regs.h>
+#include <asm/arch/imx-regs.h>
+#include <asm/arch/iomux.h>
+#include <asm/arch/mx6-pins.h>
+#include <asm/arch/sys_proto.h>
+#include <asm/gpio.h>
+#include <init.h>
+#include <spi.h>
+#include <spi_flash.h>
+#include <spl.h>
+
+#if defined(CONFIG_SPL_BUILD)
+
+#include <asm/arch/mx6-ddr.h>
+
+#define IMX6DQ_DRIVE_STRENGTH_40_OHM 0x30
+#define IMX6DQ_DRIVE_STRENGTH_48_OHM 0x28
+#define IMX6DQ_DRIVE_STRENGTH IMX6DQ_DRIVE_STRENGTH_40_OHM
+
+#define QMX6_DDR_PKE_DISABLED 0x00000000
+#define QMX6_DDR_ODT_60_OHM (2 << 16)
+#define QMX6_DDR_TYPE_DDR3 0x000c0000
+
+#define QMX6_DRAM_SDCKE_PULLUP_100K 0x00003000
+#define QMX6_DRAM_SDBA2_PULLUP_NONE 0x00000000
+
+#define SPI_PAD_CTRL (PAD_CTL_HYS | \
+ PAD_CTL_SPEED_MED | \
+ PAD_CTL_DSE_40ohm | PAD_CTL_SRE_FAST)
+
+#define UART_PAD_CTRL (PAD_CTL_PUS_100K_UP | \
+ PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm | \
+ PAD_CTL_SRE_FAST | PAD_CTL_HYS)
+
+#define SPI1_CS0 IMX_GPIO_NR(3, 19)
+#define POWEROFF IMX_GPIO_NR(4, 25)
+
+static iomux_v3_cfg_t const poweroff_pads[] = {
+ IOMUX_PADS(PAD_DISP0_DAT4__GPIO4_IO25 | MUX_PAD_CTRL(NO_PAD_CTRL)),
+};
+
+static iomux_v3_cfg_t const uart2_pads[] = {
+ IOMUX_PADS(PAD_EIM_D26__UART2_TX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL)),
+ IOMUX_PADS(PAD_EIM_D27__UART2_RX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL)),
+};
+
+static iomux_v3_cfg_t const uart3_pads[] = {
+ IOMUX_PADS(PAD_EIM_D24__UART3_TX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL)),
+ IOMUX_PADS(PAD_EIM_D25__UART3_RX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL)),
+};
+
+static iomux_v3_cfg_t const ecspi1_pads[] = {
+ IOMUX_PADS(PAD_EIM_D16__ECSPI1_SCLK | MUX_PAD_CTRL(SPI_PAD_CTRL)),
+ IOMUX_PADS(PAD_EIM_D17__ECSPI1_MISO | MUX_PAD_CTRL(SPI_PAD_CTRL)),
+ IOMUX_PADS(PAD_EIM_D18__ECSPI1_MOSI | MUX_PAD_CTRL(SPI_PAD_CTRL)),
+ IOMUX_PADS(PAD_EIM_D19__GPIO3_IO19 | MUX_PAD_CTRL(NO_PAD_CTRL)),
+};
+
+static struct mx6dq_iomux_ddr_regs mx6q_ddr_ioregs = {
+ .dram_sdclk_0 = IMX6DQ_DRIVE_STRENGTH,
+ .dram_sdclk_1 = IMX6DQ_DRIVE_STRENGTH,
+ .dram_cas = IMX6DQ_DRIVE_STRENGTH,
+ .dram_ras = IMX6DQ_DRIVE_STRENGTH,
+ .dram_reset = IMX6DQ_DRIVE_STRENGTH,
+ .dram_sdcke0 = QMX6_DRAM_SDCKE_PULLUP_100K,
+ .dram_sdcke1 = QMX6_DRAM_SDCKE_PULLUP_100K,
+ .dram_sdba2 = QMX6_DRAM_SDBA2_PULLUP_NONE,
+ .dram_sdodt0 = IMX6DQ_DRIVE_STRENGTH,
+ .dram_sdodt1 = IMX6DQ_DRIVE_STRENGTH,
+ .dram_sdqs0 = IMX6DQ_DRIVE_STRENGTH,
+ .dram_sdqs1 = IMX6DQ_DRIVE_STRENGTH,
+ .dram_sdqs2 = IMX6DQ_DRIVE_STRENGTH,
+ .dram_sdqs3 = IMX6DQ_DRIVE_STRENGTH,
+ .dram_sdqs4 = IMX6DQ_DRIVE_STRENGTH,
+ .dram_sdqs5 = IMX6DQ_DRIVE_STRENGTH,
+ .dram_sdqs6 = IMX6DQ_DRIVE_STRENGTH,
+ .dram_sdqs7 = IMX6DQ_DRIVE_STRENGTH,
+ .dram_dqm0 = IMX6DQ_DRIVE_STRENGTH,
+ .dram_dqm1 = IMX6DQ_DRIVE_STRENGTH,
+ .dram_dqm2 = IMX6DQ_DRIVE_STRENGTH,
+ .dram_dqm3 = IMX6DQ_DRIVE_STRENGTH,
+ .dram_dqm4 = IMX6DQ_DRIVE_STRENGTH,
+ .dram_dqm5 = IMX6DQ_DRIVE_STRENGTH,
+ .dram_dqm6 = IMX6DQ_DRIVE_STRENGTH,
+ .dram_dqm7 = IMX6DQ_DRIVE_STRENGTH,
+};
+
+static const struct mx6sdl_iomux_ddr_regs mx6dl_ddr_ioregs = {
+ .dram_sdclk_0 = IMX6DQ_DRIVE_STRENGTH,
+ .dram_sdclk_1 = IMX6DQ_DRIVE_STRENGTH,
+ .dram_cas = IMX6DQ_DRIVE_STRENGTH,
+ .dram_ras = IMX6DQ_DRIVE_STRENGTH,
+ .dram_reset = IMX6DQ_DRIVE_STRENGTH,
+ .dram_sdcke0 = QMX6_DRAM_SDCKE_PULLUP_100K,
+ .dram_sdcke1 = QMX6_DRAM_SDCKE_PULLUP_100K,
+ .dram_sdba2 = QMX6_DRAM_SDBA2_PULLUP_NONE,
+ .dram_sdodt0 = IMX6DQ_DRIVE_STRENGTH,
+ .dram_sdodt1 = IMX6DQ_DRIVE_STRENGTH,
+ .dram_sdqs0 = IMX6DQ_DRIVE_STRENGTH,
+ .dram_sdqs1 = IMX6DQ_DRIVE_STRENGTH,
+ .dram_sdqs2 = IMX6DQ_DRIVE_STRENGTH,
+ .dram_sdqs3 = IMX6DQ_DRIVE_STRENGTH,
+ .dram_sdqs4 = IMX6DQ_DRIVE_STRENGTH,
+ .dram_sdqs5 = IMX6DQ_DRIVE_STRENGTH,
+ .dram_sdqs6 = IMX6DQ_DRIVE_STRENGTH,
+ .dram_sdqs7 = IMX6DQ_DRIVE_STRENGTH,
+ .dram_dqm0 = IMX6DQ_DRIVE_STRENGTH,
+ .dram_dqm1 = IMX6DQ_DRIVE_STRENGTH,
+ .dram_dqm2 = IMX6DQ_DRIVE_STRENGTH,
+ .dram_dqm3 = IMX6DQ_DRIVE_STRENGTH,
+ .dram_dqm4 = IMX6DQ_DRIVE_STRENGTH,
+ .dram_dqm5 = IMX6DQ_DRIVE_STRENGTH,
+ .dram_dqm6 = IMX6DQ_DRIVE_STRENGTH,
+ .dram_dqm7 = IMX6DQ_DRIVE_STRENGTH,
+};
+
+static struct mx6dq_iomux_grp_regs mx6q_grp_ioregs = {
+ .grp_ddr_type = QMX6_DDR_TYPE_DDR3,
+ .grp_ddrmode_ctl = QMX6_DDR_ODT_60_OHM,
+ .grp_ddrpke = QMX6_DDR_PKE_DISABLED,
+ .grp_addds = IMX6DQ_DRIVE_STRENGTH,
+ .grp_ctlds = IMX6DQ_DRIVE_STRENGTH,
+ .grp_ddrmode = QMX6_DDR_ODT_60_OHM,
+ .grp_b0ds = IMX6DQ_DRIVE_STRENGTH,
+ .grp_b1ds = IMX6DQ_DRIVE_STRENGTH,
+ .grp_b2ds = IMX6DQ_DRIVE_STRENGTH,
+ .grp_b3ds = IMX6DQ_DRIVE_STRENGTH,
+ .grp_b4ds = IMX6DQ_DRIVE_STRENGTH,
+ .grp_b5ds = IMX6DQ_DRIVE_STRENGTH,
+ .grp_b6ds = IMX6DQ_DRIVE_STRENGTH,
+ .grp_b7ds = IMX6DQ_DRIVE_STRENGTH,
+};
+
+static const struct mx6sdl_iomux_grp_regs mx6sdl_grp_ioregs = {
+ .grp_ddr_type = QMX6_DDR_TYPE_DDR3,
+ .grp_ddrmode_ctl = QMX6_DDR_ODT_60_OHM,
+ .grp_ddrpke = QMX6_DDR_PKE_DISABLED,
+ .grp_addds = IMX6DQ_DRIVE_STRENGTH,
+ .grp_ctlds = IMX6DQ_DRIVE_STRENGTH,
+ .grp_ddrmode = QMX6_DDR_ODT_60_OHM,
+ .grp_b0ds = IMX6DQ_DRIVE_STRENGTH,
+ .grp_b1ds = IMX6DQ_DRIVE_STRENGTH,
+ .grp_b2ds = IMX6DQ_DRIVE_STRENGTH,
+ .grp_b3ds = IMX6DQ_DRIVE_STRENGTH,
+ .grp_b4ds = IMX6DQ_DRIVE_STRENGTH,
+ .grp_b5ds = IMX6DQ_DRIVE_STRENGTH,
+ .grp_b6ds = IMX6DQ_DRIVE_STRENGTH,
+ .grp_b7ds = IMX6DQ_DRIVE_STRENGTH,
+};
+
+const struct mx6_mmdc_calibration mx6q_mmcd_calib = {
+ .p0_mpwldectrl0 = 0x0016001A,
+ .p0_mpwldectrl1 = 0x0023001C,
+ .p1_mpwldectrl0 = 0x0028003A,
+ .p1_mpwldectrl1 = 0x001F002C,
+ .p0_mpdgctrl0 = 0x43440354,
+ .p0_mpdgctrl1 = 0x033C033C,
+ .p1_mpdgctrl0 = 0x43300368,
+ .p1_mpdgctrl1 = 0x03500330,
+ .p0_mprddlctl = 0x3228242E,
+ .p1_mprddlctl = 0x2C2C2636,
+ .p0_mpwrdlctl = 0x36323A38,
+ .p1_mpwrdlctl = 0x42324440,
+};
+
+const struct mx6_mmdc_calibration mx6q_2g_mmcd_calib = {
+ .p0_mpwldectrl0 = 0x00080016,
+ .p0_mpwldectrl1 = 0x001D0016,
+ .p1_mpwldectrl0 = 0x0018002C,
+ .p1_mpwldectrl1 = 0x000D001D,
+ .p0_mpdgctrl0 = 0x43200334,
+ .p0_mpdgctrl1 = 0x0320031C,
+ .p1_mpdgctrl0 = 0x0344034C,
+ .p1_mpdgctrl1 = 0x03380314,
+ .p0_mprddlctl = 0x3E36383A,
+ .p1_mprddlctl = 0x38363240,
+ .p0_mpwrdlctl = 0x36364238,
+ .p1_mpwrdlctl = 0x4230423E,
+};
+
+const struct mx6_mmdc_calibration mx6q_4g_mmcd_calib = {
+ .p0_mpwldectrl0 = 0x00180018,
+ .p0_mpwldectrl1 = 0x00220018,
+ .p1_mpwldectrl0 = 0x00330046,
+ .p1_mpwldectrl1 = 0x002B003D,
+ .p0_mpdgctrl0 = 0x4344034C,
+ .p0_mpdgctrl1 = 0x033C033C,
+ .p1_mpdgctrl0 = 0x03700374,
+ .p1_mpdgctrl1 = 0x03600338,
+ .p0_mprddlctl = 0x443E3E40,
+ .p1_mprddlctl = 0x423E3E48,
+ .p0_mpwrdlctl = 0x3C3C4442,
+ .p1_mpwrdlctl = 0x46384C46,
+};
+
+static const struct mx6_mmdc_calibration mx6s_mmcd_calib = {
+ .p0_mpwldectrl0 = 0x00480049,
+ .p0_mpwldectrl1 = 0x00410044,
+ .p0_mpdgctrl0 = 0x42480248,
+ .p0_mpdgctrl1 = 0x023C023C,
+ .p0_mprddlctl = 0x40424644,
+ .p0_mpwrdlctl = 0x34323034,
+};
+
+static const struct mx6_mmdc_calibration mx6s_2g_mmcd_calib = {
+ .p0_mpwldectrl0 = 0x00450048,
+ .p0_mpwldectrl1 = 0x003B003F,
+ .p0_mpdgctrl0 = 0x424C0248,
+ .p0_mpdgctrl1 = 0x0234023C,
+ .p0_mprddlctl = 0x40444848,
+ .p0_mpwrdlctl = 0x38363232,
+};
+
+static const struct mx6_mmdc_calibration mx6dl_mmcd_calib = {
+ .p0_mpwldectrl0 = 0x0043004B,
+ .p0_mpwldectrl1 = 0x003A003E,
+ .p1_mpwldectrl0 = 0x0047004F,
+ .p1_mpwldectrl1 = 0x004E0061,
+ .p0_mpdgctrl0 = 0x42500250,
+ .p0_mpdgctrl1 = 0x0238023C,
+ .p1_mpdgctrl0 = 0x42640264,
+ .p1_mpdgctrl1 = 0x02500258,
+ .p0_mprddlctl = 0x40424846,
+ .p1_mprddlctl = 0x46484842,
+ .p0_mpwrdlctl = 0x38382C30,
+ .p1_mpwrdlctl = 0x34343430,
+};
+
+static const struct mx6_mmdc_calibration mx6dl_2g_mmcd_calib = {
+ .p0_mpwldectrl0 = 0x00450045,
+ .p0_mpwldectrl1 = 0x00390043,
+ .p1_mpwldectrl0 = 0x0049004D,
+ .p1_mpwldectrl1 = 0x004E0061,
+ .p0_mpdgctrl0 = 0x4240023C,
+ .p0_mpdgctrl1 = 0x0228022C,
+ .p1_mpdgctrl0 = 0x02400244,
+ .p1_mpdgctrl1 = 0x02340238,
+ .p0_mprddlctl = 0x42464648,
+ .p1_mprddlctl = 0x4446463C,
+ .p0_mpwrdlctl = 0x3C38323A,
+ .p1_mpwrdlctl = 0x34323430,
+};
+
+static struct mx6_ddr3_cfg mem_ddr_2g = {
+ .mem_speed = 1600,
+ .density = 2,
+ .width = 16,
+ .banks = 8,
+ .rowaddr = 14,
+ .coladdr = 10,
+ .pagesz = 2,
+ .trcd = 1310,
+ .trcmin = 4875,
+ .trasmin = 3500,
+};
+
+static struct mx6_ddr3_cfg mem_ddr_4g = {
+ .mem_speed = 1600,
+ .density = 4,
+ .width = 16,
+ .banks = 8,
+ .rowaddr = 15,
+ .coladdr = 10,
+ .pagesz = 2,
+ .trcd = 1310,
+ .trcmin = 4875,
+ .trasmin = 3500,
+};
+
+static struct mx6_ddr3_cfg mem_ddr_8g = {
+ .mem_speed = 1600,
+ .density = 8,
+ .width = 16,
+ .banks = 8,
+ .rowaddr = 16,
+ .coladdr = 10,
+ .pagesz = 2,
+ .trcd = 1310,
+ .trcmin = 4875,
+ .trasmin = 3500,
+};
+
+static void spl_dram_init(u8 width, u32 memsize) {
+ struct mx6_ddr_sysinfo sysinfo = {
+ /* width of data bus: 0=16, 1=32, 2=64 */
+ .dsize = width / 32,
+ /* config for full 4GB range so that get_mem_size() works */
+ .cs_density = 32, /* 32Gb per CS */
+
+ .ncs = 1,
+ .cs1_mirror = 0,
+ .rtt_wr = 2,
+ .rtt_nom = 2,
+ .walat = 0,
+ .ralat = 5,
+ .mif3_mode = 3,
+ .bi_on = 1,
+ .sde_to_rst = 0x0d,
+ .rst_to_cke = 0x20,
+ };
+
+ if (is_cpu_type(MXC_CPU_MX6SOLO)) {
+ sysinfo.walat = 1;
+ mx6sdl_dram_iocfg(width, &mx6dl_ddr_ioregs, &mx6sdl_grp_ioregs);
+
+ switch(memsize) {
+ case 512:
+ mx6_dram_cfg(&sysinfo, &mx6s_2g_mmcd_calib, &mem_ddr_2g);
+ break;
+ default:
+ mx6_dram_cfg(&sysinfo, &mx6s_mmcd_calib, &mem_ddr_4g);
+ break;
+ }
+ } else if (is_cpu_type(MXC_CPU_MX6DL)) {
+ sysinfo.walat = 1;
+ mx6sdl_dram_iocfg(width, &mx6dl_ddr_ioregs, &mx6sdl_grp_ioregs);
+
+ switch(memsize) {
+ case 2048:
+ mx6_dram_cfg(&sysinfo, &mx6dl_2g_mmcd_calib, &mem_ddr_4g);
+ break;
+ default:
+ mx6_dram_cfg(&sysinfo, &mx6dl_mmcd_calib, &mem_ddr_2g);
+ break;
+ }
+ } else if (is_cpu_type(MXC_CPU_MX6Q)) {
+ mx6dq_dram_iocfg(width, &mx6q_ddr_ioregs, &mx6q_grp_ioregs);
+
+ switch(memsize) {
+ case 4096:
+ sysinfo.cs_density = 16;
+ sysinfo.ncs = 2;
+ mx6_dram_cfg(&sysinfo, &mx6q_4g_mmcd_calib, &mem_ddr_8g);
+ break;
+ case 2048:
+ mx6_dram_cfg(&sysinfo, &mx6q_2g_mmcd_calib, &mem_ddr_4g);
+ break;
+ default:
+ mx6_dram_cfg(&sysinfo, &mx6q_mmcd_calib, &mem_ddr_2g);
+ break;
+ }
+ }
+}
+
+/* Define a minimal structure so that the part number can be read via SPL */
+#define CFG_MFG_ADDR_OFFSET (spi->size - SZ_16K)
+struct mfgdata {
+ unsigned char tsize;
+ /* size of checksummed part in bytes */
+ unsigned char ckcnt;
+ /* checksum corrected byte */
+ unsigned char cksum;
+ /* decimal serial number, packed BCD */
+ unsigned char serial[6];
+ /* part number, right justified, ASCII */
+ unsigned char pn[16];
+};
+
+static void conv_ascii(unsigned char *dst, unsigned char *src, int len)
+{
+ int remain = len;
+ unsigned char *sptr = src;
+ unsigned char *dptr = dst;
+
+ while (remain) {
+ if (*sptr) {
+ *dptr = *sptr;
+ dptr++;
+ }
+ sptr++;
+ remain--;
+ }
+ *dptr = 0x0;
+}
+
+/*
+ * Returns the total size of the memory [in MB] the board is equipped with
+ *
+ * This is determined via the partnumber which is stored in the
+ * congatec manufacturing area
+ */
+static int get_boardmem_size(struct spi_flash *spi)
+{
+ int ret;
+ int i;
+ int arraysize;
+ char buf[sizeof(struct mfgdata)];
+ struct mfgdata *data = (struct mfgdata *)buf;
+ unsigned char outbuf[32];
+ char partnumbers_2g[4][7] = { "016104", "016105", "016304", "016305" };
+ char partnumbers_4g[2][7] = { "016308", "016318" };
+ char partnumbers_512m[2][7] = { "016203", "616300" };
+
+ ret = spi_flash_read(spi, CFG_MFG_ADDR_OFFSET, sizeof(struct mfgdata),
+ buf);
+ if (ret)
+ return 1024; /* default to 1GByte in case of error */
+
+ conv_ascii(outbuf, data->pn, sizeof(data->pn));
+
+ printf("Detected Congatec QMX6 SOM: %s\n", outbuf);
+
+ /* congatec PN 016104, 016105, 016304, 016305 have 2GiB of RAM */
+ arraysize = sizeof(partnumbers_2g) / sizeof(partnumbers_2g[0]);
+ for (i=0; i < arraysize; i++) {
+ if (!memcmp(outbuf,partnumbers_2g[i],6))
+ return 2048;
+ }
+
+ /* congatec PN 016308, 016318 have 4GiB of RAM */
+ arraysize = sizeof(partnumbers_4g) / sizeof(partnumbers_4g[0]);
+ for (i=0; i < arraysize; i++) {
+ if (!memcmp(outbuf,partnumbers_4g[i],6))
+ return 4096;
+ }
+
+ /* congatec PN 016203, 616300 has 512MiB of RAM */
+ arraysize = sizeof(partnumbers_512m) / sizeof(partnumbers_512m[0]);
+ for (i=0; i < arraysize; i++) {
+ if (!memcmp(outbuf,partnumbers_512m[i],6))
+ return 512;
+ }
+
+ /* default to 1GByte */
+ return 1024;
+}
+
+void reset_cpu(ulong addr)
+{
+}
+
+int board_spi_cs_gpio(unsigned bus, unsigned cs)
+{
+ if (bus == 0 && cs == 0)
+ return (SPI1_CS0);
+ else
+ return -1;
+}
+
+static void memory_init(void) {
+ struct spi_flash *spi;
+ u8 width;
+ u32 size;
+
+ SETUP_IOMUX_PADS(ecspi1_pads);
+ gpio_direction_output(SPI1_CS0, 0);
+
+ spi = spi_flash_probe(CONFIG_ENV_SPI_BUS,
+ CONFIG_ENV_SPI_CS,
+ CONFIG_ENV_SPI_MAX_HZ, CONFIG_ENV_SPI_MODE);
+ if (!spi)
+ panic("Cannot identify board type: SPI-NOR flash module not detected\n");
+
+ /* lock manufacturer area */
+ spi_flash_protect(spi, CFG_MFG_ADDR_OFFSET, SZ_16K, true);
+
+ width = is_cpu_type(MXC_CPU_MX6SOLO) ? 32 : 64;
+ size = get_boardmem_size(spi);
+ printf("Detected Memory Size: %u\n", size);
+
+ spl_dram_init(width, size);
+}
+
+static void ccgr_init(void)
+{
+ struct mxc_ccm_reg *ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR;
+
+ static const uint32_t ccgr0 =
+ MXC_CCM_CCGR0_AIPS_TZ1_MASK |
+ MXC_CCM_CCGR0_AIPS_TZ2_MASK |
+ MXC_CCM_CCGR0_APBHDMA_MASK |
+ MXC_CCM_CCGR0_CAAM_SECURE_MEM_MASK |
+ MXC_CCM_CCGR0_CAAM_WRAPPER_ACLK_MASK |
+ MXC_CCM_CCGR0_CAAM_WRAPPER_IPG_MASK |
+ MXC_CCM_CCGR0_CHEETAH_DBG_CLK_MASK;
+
+ static const uint32_t ccgr1 =
+ MXC_CCM_CCGR1_ECSPI1S_MASK |
+ MXC_CCM_CCGR1_ENET_MASK |
+ MXC_CCM_CCGR1_EPIT1S_MASK |
+ MXC_CCM_CCGR1_EPIT2S_MASK |
+ MXC_CCM_CCGR1_GPT_BUS_MASK;
+
+ static const uint32_t ccgr2 =
+ MXC_CCM_CCGR2_IOMUX_IPT_CLK_IO_MASK |
+ MXC_CCM_CCGR2_IPMUX1_MASK |
+ MXC_CCM_CCGR2_IPMUX2_MASK |
+ MXC_CCM_CCGR2_IPMUX3_MASK |
+ MXC_CCM_CCGR2_IPSYNC_IP2APB_TZASC1_IPGS_MASK |
+ MXC_CCM_CCGR2_IPSYNC_IP2APB_TZASC2_IPG_MASK |
+ MXC_CCM_CCGR2_IPSYNC_VDOA_IPG_MASTER_CLK_MASK;
+
+ static const uint32_t ccgr3 =
+ MXC_CCM_CCGR3_MMDC_CORE_ACLK_FAST_CORE_P0_MASK |
+ MXC_CCM_CCGR3_MMDC_CORE_ACLK_FAST_CORE_P1_MASK |
+ MXC_CCM_CCGR3_MMDC_CORE_IPG_CLK_P0_MASK |
+ MXC_CCM_CCGR3_MMDC_CORE_IPG_CLK_P1_MASK |
+ MXC_CCM_CCGR3_OCRAM_MASK;
+
+ static const uint32_t ccgr4 =
+ MXC_CCM_CCGR4_PL301_MX6QFAST1_S133_MASK |
+ MXC_CCM_CCGR4_PL301_MX6QPER1_BCH_MASK |
+ MXC_CCM_CCGR4_PL301_MX6QPER2_MAINCLK_ENABLE_MASK |
+ MXC_CCM_CCGR4_PWM1_MASK |
+ MXC_CCM_CCGR4_PWM2_MASK |
+ MXC_CCM_CCGR4_PWM3_MASK |
+ MXC_CCM_CCGR4_PWM4_MASK;
+
+ static const uint32_t ccgr5 =
+ MXC_CCM_CCGR5_ROM_MASK |
+ MXC_CCM_CCGR5_SDMA_MASK |
+ MXC_CCM_CCGR5_UART_MASK |
+ MXC_CCM_CCGR5_UART_SERIAL_MASK;
+
+ static const uint32_t ccgr6 =
+ MXC_CCM_CCGR6_USBOH3_MASK |
+ MXC_CCM_CCGR6_USDHC1_MASK |
+ MXC_CCM_CCGR6_USDHC2_MASK |
+ MXC_CCM_CCGR6_SIM1_CLK_MASK |
+ MXC_CCM_CCGR6_SIM2_CLK_MASK;
+
+ writel(ccgr0, &ccm->CCGR0);
+ writel(ccgr1, &ccm->CCGR1);
+ writel(ccgr2, &ccm->CCGR2);
+ writel(ccgr3, &ccm->CCGR3);
+ writel(ccgr4, &ccm->CCGR4);
+ writel(ccgr5, &ccm->CCGR5);
+ writel(ccgr6, &ccm->CCGR6);
+}
+
+void board_init_f(ulong dummy)
+{
+ /* setup clock gating */
+ ccgr_init();
+
+ /* setup AIPS and disable watchdog */
+ arch_cpu_init();
+
+ /* setup AXI */
+ gpr_init();
+
+ /*
+ * setup poweroff GPIO. This controls system power regulator. Once
+ * the power button is released this must be enabled to keep system
+ * running. Not enabling it (or disabling it later) will turn off
+ * the main system regulator and instantly poweroff the system. We
+ * do this very early, to reduce the time users have to press the
+ * power button.
+ */
+ SETUP_IOMUX_PADS(poweroff_pads);
+ gpio_direction_output(POWEROFF, 1);
+
+ /* setup GP timer */
+ timer_init();
+
+ /* iomux */
+ if (CONFIG_MXC_UART_BASE == UART2_BASE)
+ SETUP_IOMUX_PADS(uart2_pads);
+ else if (CONFIG_MXC_UART_BASE == UART3_BASE)
+ SETUP_IOMUX_PADS(uart3_pads);
+
+ /* UART clocks enabled and gd valid - init serial console */
+ preloader_console_init();
+
+ /* Needed for malloc() [used by SPI] to work in SPL prior to board_init_r() */
+ spl_init();
+
+ /* DDR initialization */
+ memory_init();
+}
+
+void spl_board_prepare_for_boot(void)
+{
+ printf("Load normal U-Boot...\n");
+}
+#endif
config SYS_CONFIG_NAME
default "ge_bx50v3"
+source "board/ge/common/Kconfig"
+
endif
-GE_BX50V3 BOARD
+GE BX50V3 BOARD
M: Ian Ray <ian.ray@ge.com>
+M: Sebastian Reichel <sebastian.reichel@collabora.com>
S: Maintained
+F: arch/arm/dts/imx6q-b450v3.dts
+F: arch/arm/dts/imx6q-b650v3.dts
+F: arch/arm/dts/imx6q-b850v3.dts
+F: arch/arm/dts/imx6q-bx50v3*
F: board/ge/bx50v3/
-F: include/configs/ge_bx50v3.h
-F: configs/ge_bx50v3_defconfig
F: configs/ge_b450v3_defconfig
F: configs/ge_b650v3_defconfig
F: configs/ge_b850v3_defconfig
+F: configs/ge_bx50v3_defconfig
+F: include/configs/ge_bx50v3.h
#include <version.h>
#include <stdlib.h>
#include <dm/root.h>
-#include "../common/ge_common.h"
+#include "../common/ge_rtc.h"
#include "../common/vpd_reader.h"
#include "../../../drivers/net/e1000.h"
#include <pci.h>
int board_init(void)
{
- if (!read_vpd(&vpd, vpd_callback)) {
+ if (!read_i2c_vpd(&vpd, vpd_callback)) {
int ret, rescan;
vpd.is_read = true;
--- /dev/null
+config GE_VPD
+ bool "Enable GE VPD Support"
+ default y
+
+config GE_RTC
+ bool "Enable GE RTC Support"
+ default y
#
# Copyright 2017 General Electric Company
-obj-y := vpd_reader.o ge_common.o
+obj-$(CONFIG_GE_VPD) += vpd_reader.o
+obj-$(CONFIG_GE_RTC) += ge_rtc.o
static const u8 ECC_BLOCK_ID = 0xFF;
-static int vpd_reader(size_t size, u8 *data, struct vpd_cache *userdata,
- int (*fn)(struct vpd_cache *, u8 id, u8 version, u8 type,
- size_t size, u8 const *data))
+int vpd_reader(size_t size, u8 *data, struct vpd_cache *userdata,
+ int (*fn)(struct vpd_cache *, u8 id, u8 version, u8 type,
+ size_t size, u8 const *data))
{
if (size < HEADER_BLOCK_LEN || !data || !fn)
return -EINVAL;
}
}
-int read_vpd(struct vpd_cache *cache,
- int (*process_block)(struct vpd_cache *, u8 id, u8 version,
- u8 type, size_t size, u8 const *data))
+int read_i2c_vpd(struct vpd_cache *cache,
+ int (*process_block)(struct vpd_cache *, u8 id, u8 version,
+ u8 type, size_t size, u8 const *data))
{
struct udevice *dev;
int ret;
*
* Returns Non-zero on error. Negative numbers encode errno.
*/
-int read_vpd(struct vpd_cache *cache,
- int (*process_block)(struct vpd_cache *,
- u8 id, u8 version, u8 type,
- size_t size, u8 const *data));
+int read_i2c_vpd(struct vpd_cache *cache,
+ int (*process_block)(struct vpd_cache *, u8 id, u8 version,
+ u8 type, size_t size, u8 const *data));
+
+/*
+ * Read VPD from given data, verify content, call callback for each vital
+ * product data block.
+ *
+ * size: size of the raw VPD data in bytes
+ * data: raw VPD data read from device
+ * cache: structure used by process block to store VPD information
+ * process_block: callback called for each VPD data block
+ *
+ * Returns Non-zero on error. Negative numbers encode errno.
+ */
+
+int vpd_reader(size_t size, u8 *data, struct vpd_cache *cache,
+ int (*process_block)(struct vpd_cache *, u8 id, u8 version, u8 type,
+ size_t size, u8 const *data));
config SYS_CONFIG_NAME
default "mx53ppd"
+source "board/ge/common/Kconfig"
+
endif
-MX53PPD BOARD
+GE PPD BOARD
M: Antti Mäentausta <antti.maentausta@ge.com>
-M: Martyn Welch <martyn.welch@collabora.co.uk>
+M: Ian Ray <ian.ray@ge.com>
+M: Sebastian Reichel <sebastian.reichel@collabora.com>
S: Maintained
-F: board/freescale/mx53ppd/
-F: include/configs/mx53ppd.h
+F: arch/arm/dts/imx53-ppd*
+F: board/ge/mx53ppd/
F: configs/mx53ppd_defconfig
+F: include/configs/mx53ppd.h
#include <watchdog.h>
#include "ppd_gpio.h"
#include <stdlib.h>
-#include "../../ge/common/ge_common.h"
+#include "../../ge/common/ge_rtc.h"
#include "../../ge/common/vpd_reader.h"
DECLARE_GLOBAL_DATA_PTR;
struct vpd_cache vpd;
memset(&vpd, 0, sizeof(vpd));
- res = read_vpd(&vpd, vpd_callback);
+ res = read_i2c_vpd(&vpd, vpd_callback);
if (!res)
process_vpd(&vpd);
else
#include <env.h>
#include <power/pmic.h>
#include <fsl_pmic.h>
+#include <bootstage.h>
#include "kp_id_rev.h"
#define BOOSTER_OFF IMX_GPIO_NR(2, 23)
#define LCD_BACKLIGHT IMX_GPIO_NR(1, 1)
#define KEY1 IMX_GPIO_NR(2, 26)
+#define LED_RED IMX_GPIO_NR(3, 28)
DECLARE_GLOBAL_DATA_PTR;
return ret;
}
+
+#define GPIO_DR 0x0
+#define GPIO_GDIR 0x4
+#define GPIO_ALT1 0x1
+#define GPIO5_BASE 0x53FDC000
+#define IOMUXC_EIM_WAIT 0x53FA81E4
+/* Green LED: GPIO5_0 */
+#define GPIO_GREEN BIT(0)
+
+void show_boot_progress(int status)
+{
+ /*
+ * This BOOTSTAGE_ID is called at very early stage of execution. DM gpio
+ * is not yet initialized.
+ */
+ if (status == BOOTSTAGE_ID_START_UBOOT_F) {
+ /*
+ * After ROM execution the EIM_WAIT PAD is set as ALT0
+ * (according to RM it shall be ALT1 after reset). To use it as
+ * GPIO we need to set it to ALT1.
+ */
+ setbits_le32(((uint32_t *)(IOMUXC_EIM_WAIT)), GPIO_ALT1);
+
+ /* Configure green LED GPIO pin direction */
+ setbits_le32(((uint32_t *)(GPIO5_BASE + GPIO_GDIR)),
+ GPIO_GREEN);
+ /* Turn on green LED */
+ setbits_le32(((uint32_t *)(GPIO5_BASE + GPIO_DR)), GPIO_GREEN);
+ }
+
+ /*
+ * This BOOTSTAGE_ID is called just before handling execution to kernel
+ * - i.e. gpio subsystem is already initialized
+ */
+ if (status == BOOTSTAGE_ID_BOOTM_HANDOFF) {
+ /*
+ * Off green LED - the same approach - i.e. non dm gpio
+ * (*bits_le32) is used as in the very early stage.
+ */
+ clrbits_le32(((uint32_t *)(GPIO5_BASE + GPIO_DR)),
+ GPIO_GREEN);
+
+ /*
+ * On red LED
+ */
+ gpio_request(LED_RED, "LED_RED_ERROR");
+ gpio_direction_output(LED_RED, 1);
+ }
+}
--- /dev/null
+if TARGET_PHYCORE_IMX8MM
+
+config SYS_BOARD
+ default "phycore_imx8mm"
+
+config SYS_VENDOR
+ default "phytec"
+
+config SYS_CONFIG_NAME
+ default "phycore_imx8mm"
+
+endif
--- /dev/null
+phyCORE-i.MX8M Mini
+M: Teresa Remmet <t.remmet@phytec.de>
+W: https://www.phytec.eu/product-eu/system-on-modules/phycore-imx-8m-mini-nano/
+S: Maintained
+F: arch/arm/dts/phycore-imx8mm.dts
+F: arch/arm/dts/phycore-imx8mm-u-boot.dtsi
+F: board/phytec/phycore_imx8mm/
+F: configs/phycore-imx8mm_defconfig
+F: include/configs/phycore_imx8mm.h
--- /dev/null
+# SPDX-License-Identifier: GPL-2.0-or-later
+#
+# Copyright (C) 2019-2020 PHYTEC Messtechnik GmbH
+# Author: Teresa Remmet <t.remmet@phytec.de>
+
+obj-y += phycore-imx8mm.o
+
+ifdef CONFIG_SPL_BUILD
+obj-y += spl.o
+obj-$(CONFIG_IMX8M_LPDDR4) += lpddr4_timing.o
+endif
--- /dev/null
+// SPDX-License-Identifier: GPL-2.0-or-later
+/*
+ * Copyright (C) 2020 PHYTEC Messtechnik GmbH
+ *
+ * Generated code from MX8M_DDR_tool
+ */
+
+#include <linux/kernel.h>
+#include <asm/arch/ddr.h>
+
+static struct dram_cfg_param ddr_ddrc_cfg[] = {
+ /** Initialize DDRC registers **/
+ {0x3d400304, 0x1},
+ {0x3d400030, 0x1},
+ {0x3d400000, 0xa1080020},
+ {0x3d400020, 0x223},
+ {0x3d400024, 0x3a980},
+ {0x3d400064, 0x5b00d2},
+ {0x3d4000d0, 0xc00305ba},
+ {0x3d4000d4, 0x940000},
+ {0x3d4000dc, 0xd4002d},
+ {0x3d4000e0, 0x310000},
+ {0x3d4000e8, 0x66004d},
+ {0x3d4000ec, 0x16004d},
+ {0x3d400100, 0x191e1920},
+ {0x3d400104, 0x60630},
+ {0x3d40010c, 0xb0b000},
+ {0x3d400110, 0xe04080e},
+ {0x3d400114, 0x2040c0c},
+ {0x3d400118, 0x1010007},
+ {0x3d40011c, 0x401},
+ {0x3d400130, 0x20600},
+ {0x3d400134, 0xc100002},
+ {0x3d400138, 0xd8},
+ {0x3d400144, 0x96004b},
+ {0x3d400180, 0x2ee0017},
+ {0x3d400184, 0x2605b8e},
+ {0x3d400188, 0x0},
+ {0x3d400190, 0x497820a},
+ {0x3d400194, 0x80303},
+ {0x3d4001b4, 0x170a},
+ {0x3d4001a0, 0xe0400018},
+ {0x3d4001a4, 0xdf00e4},
+ {0x3d4001a8, 0x80000000},
+ {0x3d4001b0, 0x11},
+ {0x3d4001c0, 0x1},
+ {0x3d4001c4, 0x1},
+ {0x3d4000f4, 0xc99},
+ {0x3d400108, 0x70e1617},
+ {0x3d400200, 0x1f},
+ {0x3d40020c, 0x0},
+ {0x3d400210, 0x1f1f},
+ {0x3d400204, 0x80808},
+ {0x3d400214, 0x7070707},
+ {0x3d400218, 0x7070707},
+ {0x3d400250, 0x29001701},
+ {0x3d400254, 0x2c},
+ {0x3d40025c, 0x4000030},
+ {0x3d400264, 0x900093e7},
+ {0x3d40026c, 0x2005574},
+ {0x3d400400, 0x111},
+ {0x3d400408, 0x72ff},
+ {0x3d400494, 0x2100e07},
+ {0x3d400498, 0x620096},
+ {0x3d40049c, 0x1100e07},
+ {0x3d4004a0, 0xc8012c},
+ {0x3d402020, 0x21},
+ {0x3d402024, 0x7d00},
+ {0x3d402050, 0x20d040},
+ {0x3d402064, 0xc001c},
+ {0x3d4020dc, 0x840000},
+ {0x3d4020e0, 0x310000},
+ {0x3d4020e8, 0x66004d},
+ {0x3d4020ec, 0x16004d},
+ {0x3d402100, 0xa040305},
+ {0x3d402104, 0x30407},
+ {0x3d402108, 0x203060b},
+ {0x3d40210c, 0x505000},
+ {0x3d402110, 0x2040202},
+ {0x3d402114, 0x2030202},
+ {0x3d402118, 0x1010004},
+ {0x3d40211c, 0x301},
+ {0x3d402130, 0x20300},
+ {0x3d402134, 0xa100002},
+ {0x3d402138, 0x1d},
+ {0x3d402144, 0x14000a},
+ {0x3d402180, 0x640004},
+ {0x3d402190, 0x3818200},
+ {0x3d402194, 0x80303},
+ {0x3d4021b4, 0x100},
+ {0x3d4020f4, 0xc99},
+ {0x3d403020, 0x21},
+ {0x3d403024, 0x1f40},
+ {0x3d403050, 0x20d040},
+ {0x3d403064, 0x30007},
+ {0x3d4030dc, 0x840000},
+ {0x3d4030e0, 0x310000},
+ {0x3d4030e8, 0x66004d},
+ {0x3d4030ec, 0x16004d},
+ {0x3d403100, 0xa010102},
+ {0x3d403104, 0x30404},
+ {0x3d403108, 0x203060b},
+ {0x3d40310c, 0x505000},
+ {0x3d403110, 0x2040202},
+ {0x3d403114, 0x2030202},
+ {0x3d403118, 0x1010004},
+ {0x3d40311c, 0x301},
+ {0x3d403130, 0x20300},
+ {0x3d403134, 0xa100002},
+ {0x3d403138, 0x8},
+ {0x3d403144, 0x50003},
+ {0x3d403180, 0x190004},
+ {0x3d403190, 0x3818200},
+ {0x3d403194, 0x80303},
+ {0x3d4031b4, 0x100},
+ {0x3d4030f4, 0xc99},
+ {0x3d400028, 0x0},
+};
+
+/* PHY Initialize Configuration */
+static struct dram_cfg_param ddr_ddrphy_cfg[] = {
+ {0x100a0, 0x0},
+ {0x100a1, 0x1},
+ {0x100a2, 0x2},
+ {0x100a3, 0x3},
+ {0x100a4, 0x4},
+ {0x100a5, 0x5},
+ {0x100a6, 0x6},
+ {0x100a7, 0x7},
+ {0x110a0, 0x0},
+ {0x110a1, 0x1},
+ {0x110a2, 0x3},
+ {0x110a3, 0x4},
+ {0x110a4, 0x5},
+ {0x110a5, 0x2},
+ {0x110a6, 0x7},
+ {0x110a7, 0x6},
+ {0x120a0, 0x0},
+ {0x120a1, 0x1},
+ {0x120a2, 0x3},
+ {0x120a3, 0x2},
+ {0x120a4, 0x5},
+ {0x120a5, 0x4},
+ {0x120a6, 0x7},
+ {0x120a7, 0x6},
+ {0x130a0, 0x0},
+ {0x130a1, 0x1},
+ {0x130a2, 0x2},
+ {0x130a3, 0x3},
+ {0x130a4, 0x4},
+ {0x130a5, 0x5},
+ {0x130a6, 0x6},
+ {0x130a7, 0x7},
+ {0x1005f, 0x1ff},
+ {0x1015f, 0x1ff},
+ {0x1105f, 0x1ff},
+ {0x1115f, 0x1ff},
+ {0x1205f, 0x1ff},
+ {0x1215f, 0x1ff},
+ {0x1305f, 0x1ff},
+ {0x1315f, 0x1ff},
+ {0x11005f, 0x1ff},
+ {0x11015f, 0x1ff},
+ {0x11105f, 0x1ff},
+ {0x11115f, 0x1ff},
+ {0x11205f, 0x1ff},
+ {0x11215f, 0x1ff},
+ {0x11305f, 0x1ff},
+ {0x11315f, 0x1ff},
+ {0x21005f, 0x1ff},
+ {0x21015f, 0x1ff},
+ {0x21105f, 0x1ff},
+ {0x21115f, 0x1ff},
+ {0x21205f, 0x1ff},
+ {0x21215f, 0x1ff},
+ {0x21305f, 0x1ff},
+ {0x21315f, 0x1ff},
+ {0x55, 0x1ff},
+ {0x1055, 0x1ff},
+ {0x2055, 0x1ff},
+ {0x3055, 0x1ff},
+ {0x4055, 0x1ff},
+ {0x5055, 0x1ff},
+ {0x6055, 0x1ff},
+ {0x7055, 0x1ff},
+ {0x8055, 0x1ff},
+ {0x9055, 0x1ff},
+ {0x200c5, 0x19},
+ {0x1200c5, 0x7},
+ {0x2200c5, 0x7},
+ {0x2002e, 0x2},
+ {0x12002e, 0x2},
+ {0x22002e, 0x2},
+ {0x90204, 0x0},
+ {0x190204, 0x0},
+ {0x290204, 0x0},
+ {0x20024, 0x1ab},
+ {0x2003a, 0x0},
+ {0x120024, 0x1ab},
+ {0x2003a, 0x0},
+ {0x220024, 0x1ab},
+ {0x2003a, 0x0},
+ {0x20056, 0x3},
+ {0x120056, 0xa},
+ {0x220056, 0xa},
+ {0x1004d, 0xe00},
+ {0x1014d, 0xe00},
+ {0x1104d, 0xe00},
+ {0x1114d, 0xe00},
+ {0x1204d, 0xe00},
+ {0x1214d, 0xe00},
+ {0x1304d, 0xe00},
+ {0x1314d, 0xe00},
+ {0x11004d, 0xe00},
+ {0x11014d, 0xe00},
+ {0x11104d, 0xe00},
+ {0x11114d, 0xe00},
+ {0x11204d, 0xe00},
+ {0x11214d, 0xe00},
+ {0x11304d, 0xe00},
+ {0x11314d, 0xe00},
+ {0x21004d, 0xe00},
+ {0x21014d, 0xe00},
+ {0x21104d, 0xe00},
+ {0x21114d, 0xe00},
+ {0x21204d, 0xe00},
+ {0x21214d, 0xe00},
+ {0x21304d, 0xe00},
+ {0x21314d, 0xe00},
+ {0x10049, 0xeba},
+ {0x10149, 0xeba},
+ {0x11049, 0xeba},
+ {0x11149, 0xeba},
+ {0x12049, 0xeba},
+ {0x12149, 0xeba},
+ {0x13049, 0xeba},
+ {0x13149, 0xeba},
+ {0x110049, 0xeba},
+ {0x110149, 0xeba},
+ {0x111049, 0xeba},
+ {0x111149, 0xeba},
+ {0x112049, 0xeba},
+ {0x112149, 0xeba},
+ {0x113049, 0xeba},
+ {0x113149, 0xeba},
+ {0x210049, 0xeba},
+ {0x210149, 0xeba},
+ {0x211049, 0xeba},
+ {0x211149, 0xeba},
+ {0x212049, 0xeba},
+ {0x212149, 0xeba},
+ {0x213049, 0xeba},
+ {0x213149, 0xeba},
+ {0x43, 0x63},
+ {0x1043, 0x63},
+ {0x2043, 0x63},
+ {0x3043, 0x63},
+ {0x4043, 0x63},
+ {0x5043, 0x63},
+ {0x6043, 0x63},
+ {0x7043, 0x63},
+ {0x8043, 0x63},
+ {0x9043, 0x63},
+ {0x20018, 0x3},
+ {0x20075, 0x4},
+ {0x20050, 0x0},
+ {0x20008, 0x2ee},
+ {0x120008, 0x64},
+ {0x220008, 0x19},
+ {0x20088, 0x9},
+ {0x200b2, 0xdc},
+ {0x10043, 0x5a1},
+ {0x10143, 0x5a1},
+ {0x11043, 0x5a1},
+ {0x11143, 0x5a1},
+ {0x12043, 0x5a1},
+ {0x12143, 0x5a1},
+ {0x13043, 0x5a1},
+ {0x13143, 0x5a1},
+ {0x1200b2, 0xdc},
+ {0x110043, 0x5a1},
+ {0x110143, 0x5a1},
+ {0x111043, 0x5a1},
+ {0x111143, 0x5a1},
+ {0x112043, 0x5a1},
+ {0x112143, 0x5a1},
+ {0x113043, 0x5a1},
+ {0x113143, 0x5a1},
+ {0x2200b2, 0xdc},
+ {0x210043, 0x5a1},
+ {0x210143, 0x5a1},
+ {0x211043, 0x5a1},
+ {0x211143, 0x5a1},
+ {0x212043, 0x5a1},
+ {0x212143, 0x5a1},
+ {0x213043, 0x5a1},
+ {0x213143, 0x5a1},
+ {0x200fa, 0x1},
+ {0x1200fa, 0x1},
+ {0x2200fa, 0x1},
+ {0x20019, 0x1},
+ {0x120019, 0x1},
+ {0x220019, 0x1},
+ {0x200f0, 0x660},
+ {0x200f1, 0x0},
+ {0x200f2, 0x4444},
+ {0x200f3, 0x8888},
+ {0x200f4, 0x5665},
+ {0x200f5, 0x0},
+ {0x200f6, 0x0},
+ {0x200f7, 0xf000},
+ {0x20025, 0x0},
+ {0x2002d, 0x0},
+ {0x12002d, 0x0},
+ {0x22002d, 0x0},
+ {0x200c7, 0x21},
+ {0x1200c7, 0x21},
+ {0x2200c7, 0x21},
+ {0x200ca, 0x24},
+ {0x1200ca, 0x24},
+ {0x2200ca, 0x24},
+};
+
+/* ddr phy trained csr */
+static struct dram_cfg_param ddr_ddrphy_trained_csr[] = {
+ { 0x200b2, 0x0 },
+ { 0x1200b2, 0x0 },
+ { 0x2200b2, 0x0 },
+ { 0x200cb, 0x0 },
+ { 0x10043, 0x0 },
+ { 0x110043, 0x0 },
+ { 0x210043, 0x0 },
+ { 0x10143, 0x0 },
+ { 0x110143, 0x0 },
+ { 0x210143, 0x0 },
+ { 0x11043, 0x0 },
+ { 0x111043, 0x0 },
+ { 0x211043, 0x0 },
+ { 0x11143, 0x0 },
+ { 0x111143, 0x0 },
+ { 0x211143, 0x0 },
+ { 0x12043, 0x0 },
+ { 0x112043, 0x0 },
+ { 0x212043, 0x0 },
+ { 0x12143, 0x0 },
+ { 0x112143, 0x0 },
+ { 0x212143, 0x0 },
+ { 0x13043, 0x0 },
+ { 0x113043, 0x0 },
+ { 0x213043, 0x0 },
+ { 0x13143, 0x0 },
+ { 0x113143, 0x0 },
+ { 0x213143, 0x0 },
+ { 0x80, 0x0 },
+ { 0x100080, 0x0 },
+ { 0x200080, 0x0 },
+ { 0x1080, 0x0 },
+ { 0x101080, 0x0 },
+ { 0x201080, 0x0 },
+ { 0x2080, 0x0 },
+ { 0x102080, 0x0 },
+ { 0x202080, 0x0 },
+ { 0x3080, 0x0 },
+ { 0x103080, 0x0 },
+ { 0x203080, 0x0 },
+ { 0x4080, 0x0 },
+ { 0x104080, 0x0 },
+ { 0x204080, 0x0 },
+ { 0x5080, 0x0 },
+ { 0x105080, 0x0 },
+ { 0x205080, 0x0 },
+ { 0x6080, 0x0 },
+ { 0x106080, 0x0 },
+ { 0x206080, 0x0 },
+ { 0x7080, 0x0 },
+ { 0x107080, 0x0 },
+ { 0x207080, 0x0 },
+ { 0x8080, 0x0 },
+ { 0x108080, 0x0 },
+ { 0x208080, 0x0 },
+ { 0x9080, 0x0 },
+ { 0x109080, 0x0 },
+ { 0x209080, 0x0 },
+ { 0x10080, 0x0 },
+ { 0x110080, 0x0 },
+ { 0x210080, 0x0 },
+ { 0x10180, 0x0 },
+ { 0x110180, 0x0 },
+ { 0x210180, 0x0 },
+ { 0x11080, 0x0 },
+ { 0x111080, 0x0 },
+ { 0x211080, 0x0 },
+ { 0x11180, 0x0 },
+ { 0x111180, 0x0 },
+ { 0x211180, 0x0 },
+ { 0x12080, 0x0 },
+ { 0x112080, 0x0 },
+ { 0x212080, 0x0 },
+ { 0x12180, 0x0 },
+ { 0x112180, 0x0 },
+ { 0x212180, 0x0 },
+ { 0x13080, 0x0 },
+ { 0x113080, 0x0 },
+ { 0x213080, 0x0 },
+ { 0x13180, 0x0 },
+ { 0x113180, 0x0 },
+ { 0x213180, 0x0 },
+ { 0x10081, 0x0 },
+ { 0x110081, 0x0 },
+ { 0x210081, 0x0 },
+ { 0x10181, 0x0 },
+ { 0x110181, 0x0 },
+ { 0x210181, 0x0 },
+ { 0x11081, 0x0 },
+ { 0x111081, 0x0 },
+ { 0x211081, 0x0 },
+ { 0x11181, 0x0 },
+ { 0x111181, 0x0 },
+ { 0x211181, 0x0 },
+ { 0x12081, 0x0 },
+ { 0x112081, 0x0 },
+ { 0x212081, 0x0 },
+ { 0x12181, 0x0 },
+ { 0x112181, 0x0 },
+ { 0x212181, 0x0 },
+ { 0x13081, 0x0 },
+ { 0x113081, 0x0 },
+ { 0x213081, 0x0 },
+ { 0x13181, 0x0 },
+ { 0x113181, 0x0 },
+ { 0x213181, 0x0 },
+ { 0x100d0, 0x0 },
+ { 0x1100d0, 0x0 },
+ { 0x2100d0, 0x0 },
+ { 0x101d0, 0x0 },
+ { 0x1101d0, 0x0 },
+ { 0x2101d0, 0x0 },
+ { 0x110d0, 0x0 },
+ { 0x1110d0, 0x0 },
+ { 0x2110d0, 0x0 },
+ { 0x111d0, 0x0 },
+ { 0x1111d0, 0x0 },
+ { 0x2111d0, 0x0 },
+ { 0x120d0, 0x0 },
+ { 0x1120d0, 0x0 },
+ { 0x2120d0, 0x0 },
+ { 0x121d0, 0x0 },
+ { 0x1121d0, 0x0 },
+ { 0x2121d0, 0x0 },
+ { 0x130d0, 0x0 },
+ { 0x1130d0, 0x0 },
+ { 0x2130d0, 0x0 },
+ { 0x131d0, 0x0 },
+ { 0x1131d0, 0x0 },
+ { 0x2131d0, 0x0 },
+ { 0x100d1, 0x0 },
+ { 0x1100d1, 0x0 },
+ { 0x2100d1, 0x0 },
+ { 0x101d1, 0x0 },
+ { 0x1101d1, 0x0 },
+ { 0x2101d1, 0x0 },
+ { 0x110d1, 0x0 },
+ { 0x1110d1, 0x0 },
+ { 0x2110d1, 0x0 },
+ { 0x111d1, 0x0 },
+ { 0x1111d1, 0x0 },
+ { 0x2111d1, 0x0 },
+ { 0x120d1, 0x0 },
+ { 0x1120d1, 0x0 },
+ { 0x2120d1, 0x0 },
+ { 0x121d1, 0x0 },
+ { 0x1121d1, 0x0 },
+ { 0x2121d1, 0x0 },
+ { 0x130d1, 0x0 },
+ { 0x1130d1, 0x0 },
+ { 0x2130d1, 0x0 },
+ { 0x131d1, 0x0 },
+ { 0x1131d1, 0x0 },
+ { 0x2131d1, 0x0 },
+ { 0x10068, 0x0 },
+ { 0x10168, 0x0 },
+ { 0x10268, 0x0 },
+ { 0x10368, 0x0 },
+ { 0x10468, 0x0 },
+ { 0x10568, 0x0 },
+ { 0x10668, 0x0 },
+ { 0x10768, 0x0 },
+ { 0x10868, 0x0 },
+ { 0x11068, 0x0 },
+ { 0x11168, 0x0 },
+ { 0x11268, 0x0 },
+ { 0x11368, 0x0 },
+ { 0x11468, 0x0 },
+ { 0x11568, 0x0 },
+ { 0x11668, 0x0 },
+ { 0x11768, 0x0 },
+ { 0x11868, 0x0 },
+ { 0x12068, 0x0 },
+ { 0x12168, 0x0 },
+ { 0x12268, 0x0 },
+ { 0x12368, 0x0 },
+ { 0x12468, 0x0 },
+ { 0x12568, 0x0 },
+ { 0x12668, 0x0 },
+ { 0x12768, 0x0 },
+ { 0x12868, 0x0 },
+ { 0x13068, 0x0 },
+ { 0x13168, 0x0 },
+ { 0x13268, 0x0 },
+ { 0x13368, 0x0 },
+ { 0x13468, 0x0 },
+ { 0x13568, 0x0 },
+ { 0x13668, 0x0 },
+ { 0x13768, 0x0 },
+ { 0x13868, 0x0 },
+ { 0x10069, 0x0 },
+ { 0x10169, 0x0 },
+ { 0x10269, 0x0 },
+ { 0x10369, 0x0 },
+ { 0x10469, 0x0 },
+ { 0x10569, 0x0 },
+ { 0x10669, 0x0 },
+ { 0x10769, 0x0 },
+ { 0x10869, 0x0 },
+ { 0x11069, 0x0 },
+ { 0x11169, 0x0 },
+ { 0x11269, 0x0 },
+ { 0x11369, 0x0 },
+ { 0x11469, 0x0 },
+ { 0x11569, 0x0 },
+ { 0x11669, 0x0 },
+ { 0x11769, 0x0 },
+ { 0x11869, 0x0 },
+ { 0x12069, 0x0 },
+ { 0x12169, 0x0 },
+ { 0x12269, 0x0 },
+ { 0x12369, 0x0 },
+ { 0x12469, 0x0 },
+ { 0x12569, 0x0 },
+ { 0x12669, 0x0 },
+ { 0x12769, 0x0 },
+ { 0x12869, 0x0 },
+ { 0x13069, 0x0 },
+ { 0x13169, 0x0 },
+ { 0x13269, 0x0 },
+ { 0x13369, 0x0 },
+ { 0x13469, 0x0 },
+ { 0x13569, 0x0 },
+ { 0x13669, 0x0 },
+ { 0x13769, 0x0 },
+ { 0x13869, 0x0 },
+ { 0x1008c, 0x0 },
+ { 0x11008c, 0x0 },
+ { 0x21008c, 0x0 },
+ { 0x1018c, 0x0 },
+ { 0x11018c, 0x0 },
+ { 0x21018c, 0x0 },
+ { 0x1108c, 0x0 },
+ { 0x11108c, 0x0 },
+ { 0x21108c, 0x0 },
+ { 0x1118c, 0x0 },
+ { 0x11118c, 0x0 },
+ { 0x21118c, 0x0 },
+ { 0x1208c, 0x0 },
+ { 0x11208c, 0x0 },
+ { 0x21208c, 0x0 },
+ { 0x1218c, 0x0 },
+ { 0x11218c, 0x0 },
+ { 0x21218c, 0x0 },
+ { 0x1308c, 0x0 },
+ { 0x11308c, 0x0 },
+ { 0x21308c, 0x0 },
+ { 0x1318c, 0x0 },
+ { 0x11318c, 0x0 },
+ { 0x21318c, 0x0 },
+ { 0x1008d, 0x0 },
+ { 0x11008d, 0x0 },
+ { 0x21008d, 0x0 },
+ { 0x1018d, 0x0 },
+ { 0x11018d, 0x0 },
+ { 0x21018d, 0x0 },
+ { 0x1108d, 0x0 },
+ { 0x11108d, 0x0 },
+ { 0x21108d, 0x0 },
+ { 0x1118d, 0x0 },
+ { 0x11118d, 0x0 },
+ { 0x21118d, 0x0 },
+ { 0x1208d, 0x0 },
+ { 0x11208d, 0x0 },
+ { 0x21208d, 0x0 },
+ { 0x1218d, 0x0 },
+ { 0x11218d, 0x0 },
+ { 0x21218d, 0x0 },
+ { 0x1308d, 0x0 },
+ { 0x11308d, 0x0 },
+ { 0x21308d, 0x0 },
+ { 0x1318d, 0x0 },
+ { 0x11318d, 0x0 },
+ { 0x21318d, 0x0 },
+ { 0x100c0, 0x0 },
+ { 0x1100c0, 0x0 },
+ { 0x2100c0, 0x0 },
+ { 0x101c0, 0x0 },
+ { 0x1101c0, 0x0 },
+ { 0x2101c0, 0x0 },
+ { 0x102c0, 0x0 },
+ { 0x1102c0, 0x0 },
+ { 0x2102c0, 0x0 },
+ { 0x103c0, 0x0 },
+ { 0x1103c0, 0x0 },
+ { 0x2103c0, 0x0 },
+ { 0x104c0, 0x0 },
+ { 0x1104c0, 0x0 },
+ { 0x2104c0, 0x0 },
+ { 0x105c0, 0x0 },
+ { 0x1105c0, 0x0 },
+ { 0x2105c0, 0x0 },
+ { 0x106c0, 0x0 },
+ { 0x1106c0, 0x0 },
+ { 0x2106c0, 0x0 },
+ { 0x107c0, 0x0 },
+ { 0x1107c0, 0x0 },
+ { 0x2107c0, 0x0 },
+ { 0x108c0, 0x0 },
+ { 0x1108c0, 0x0 },
+ { 0x2108c0, 0x0 },
+ { 0x110c0, 0x0 },
+ { 0x1110c0, 0x0 },
+ { 0x2110c0, 0x0 },
+ { 0x111c0, 0x0 },
+ { 0x1111c0, 0x0 },
+ { 0x2111c0, 0x0 },
+ { 0x112c0, 0x0 },
+ { 0x1112c0, 0x0 },
+ { 0x2112c0, 0x0 },
+ { 0x113c0, 0x0 },
+ { 0x1113c0, 0x0 },
+ { 0x2113c0, 0x0 },
+ { 0x114c0, 0x0 },
+ { 0x1114c0, 0x0 },
+ { 0x2114c0, 0x0 },
+ { 0x115c0, 0x0 },
+ { 0x1115c0, 0x0 },
+ { 0x2115c0, 0x0 },
+ { 0x116c0, 0x0 },
+ { 0x1116c0, 0x0 },
+ { 0x2116c0, 0x0 },
+ { 0x117c0, 0x0 },
+ { 0x1117c0, 0x0 },
+ { 0x2117c0, 0x0 },
+ { 0x118c0, 0x0 },
+ { 0x1118c0, 0x0 },
+ { 0x2118c0, 0x0 },
+ { 0x120c0, 0x0 },
+ { 0x1120c0, 0x0 },
+ { 0x2120c0, 0x0 },
+ { 0x121c0, 0x0 },
+ { 0x1121c0, 0x0 },
+ { 0x2121c0, 0x0 },
+ { 0x122c0, 0x0 },
+ { 0x1122c0, 0x0 },
+ { 0x2122c0, 0x0 },
+ { 0x123c0, 0x0 },
+ { 0x1123c0, 0x0 },
+ { 0x2123c0, 0x0 },
+ { 0x124c0, 0x0 },
+ { 0x1124c0, 0x0 },
+ { 0x2124c0, 0x0 },
+ { 0x125c0, 0x0 },
+ { 0x1125c0, 0x0 },
+ { 0x2125c0, 0x0 },
+ { 0x126c0, 0x0 },
+ { 0x1126c0, 0x0 },
+ { 0x2126c0, 0x0 },
+ { 0x127c0, 0x0 },
+ { 0x1127c0, 0x0 },
+ { 0x2127c0, 0x0 },
+ { 0x128c0, 0x0 },
+ { 0x1128c0, 0x0 },
+ { 0x2128c0, 0x0 },
+ { 0x130c0, 0x0 },
+ { 0x1130c0, 0x0 },
+ { 0x2130c0, 0x0 },
+ { 0x131c0, 0x0 },
+ { 0x1131c0, 0x0 },
+ { 0x2131c0, 0x0 },
+ { 0x132c0, 0x0 },
+ { 0x1132c0, 0x0 },
+ { 0x2132c0, 0x0 },
+ { 0x133c0, 0x0 },
+ { 0x1133c0, 0x0 },
+ { 0x2133c0, 0x0 },
+ { 0x134c0, 0x0 },
+ { 0x1134c0, 0x0 },
+ { 0x2134c0, 0x0 },
+ { 0x135c0, 0x0 },
+ { 0x1135c0, 0x0 },
+ { 0x2135c0, 0x0 },
+ { 0x136c0, 0x0 },
+ { 0x1136c0, 0x0 },
+ { 0x2136c0, 0x0 },
+ { 0x137c0, 0x0 },
+ { 0x1137c0, 0x0 },
+ { 0x2137c0, 0x0 },
+ { 0x138c0, 0x0 },
+ { 0x1138c0, 0x0 },
+ { 0x2138c0, 0x0 },
+ { 0x100c1, 0x0 },
+ { 0x1100c1, 0x0 },
+ { 0x2100c1, 0x0 },
+ { 0x101c1, 0x0 },
+ { 0x1101c1, 0x0 },
+ { 0x2101c1, 0x0 },
+ { 0x102c1, 0x0 },
+ { 0x1102c1, 0x0 },
+ { 0x2102c1, 0x0 },
+ { 0x103c1, 0x0 },
+ { 0x1103c1, 0x0 },
+ { 0x2103c1, 0x0 },
+ { 0x104c1, 0x0 },
+ { 0x1104c1, 0x0 },
+ { 0x2104c1, 0x0 },
+ { 0x105c1, 0x0 },
+ { 0x1105c1, 0x0 },
+ { 0x2105c1, 0x0 },
+ { 0x106c1, 0x0 },
+ { 0x1106c1, 0x0 },
+ { 0x2106c1, 0x0 },
+ { 0x107c1, 0x0 },
+ { 0x1107c1, 0x0 },
+ { 0x2107c1, 0x0 },
+ { 0x108c1, 0x0 },
+ { 0x1108c1, 0x0 },
+ { 0x2108c1, 0x0 },
+ { 0x110c1, 0x0 },
+ { 0x1110c1, 0x0 },
+ { 0x2110c1, 0x0 },
+ { 0x111c1, 0x0 },
+ { 0x1111c1, 0x0 },
+ { 0x2111c1, 0x0 },
+ { 0x112c1, 0x0 },
+ { 0x1112c1, 0x0 },
+ { 0x2112c1, 0x0 },
+ { 0x113c1, 0x0 },
+ { 0x1113c1, 0x0 },
+ { 0x2113c1, 0x0 },
+ { 0x114c1, 0x0 },
+ { 0x1114c1, 0x0 },
+ { 0x2114c1, 0x0 },
+ { 0x115c1, 0x0 },
+ { 0x1115c1, 0x0 },
+ { 0x2115c1, 0x0 },
+ { 0x116c1, 0x0 },
+ { 0x1116c1, 0x0 },
+ { 0x2116c1, 0x0 },
+ { 0x117c1, 0x0 },
+ { 0x1117c1, 0x0 },
+ { 0x2117c1, 0x0 },
+ { 0x118c1, 0x0 },
+ { 0x1118c1, 0x0 },
+ { 0x2118c1, 0x0 },
+ { 0x120c1, 0x0 },
+ { 0x1120c1, 0x0 },
+ { 0x2120c1, 0x0 },
+ { 0x121c1, 0x0 },
+ { 0x1121c1, 0x0 },
+ { 0x2121c1, 0x0 },
+ { 0x122c1, 0x0 },
+ { 0x1122c1, 0x0 },
+ { 0x2122c1, 0x0 },
+ { 0x123c1, 0x0 },
+ { 0x1123c1, 0x0 },
+ { 0x2123c1, 0x0 },
+ { 0x124c1, 0x0 },
+ { 0x1124c1, 0x0 },
+ { 0x2124c1, 0x0 },
+ { 0x125c1, 0x0 },
+ { 0x1125c1, 0x0 },
+ { 0x2125c1, 0x0 },
+ { 0x126c1, 0x0 },
+ { 0x1126c1, 0x0 },
+ { 0x2126c1, 0x0 },
+ { 0x127c1, 0x0 },
+ { 0x1127c1, 0x0 },
+ { 0x2127c1, 0x0 },
+ { 0x128c1, 0x0 },
+ { 0x1128c1, 0x0 },
+ { 0x2128c1, 0x0 },
+ { 0x130c1, 0x0 },
+ { 0x1130c1, 0x0 },
+ { 0x2130c1, 0x0 },
+ { 0x131c1, 0x0 },
+ { 0x1131c1, 0x0 },
+ { 0x2131c1, 0x0 },
+ { 0x132c1, 0x0 },
+ { 0x1132c1, 0x0 },
+ { 0x2132c1, 0x0 },
+ { 0x133c1, 0x0 },
+ { 0x1133c1, 0x0 },
+ { 0x2133c1, 0x0 },
+ { 0x134c1, 0x0 },
+ { 0x1134c1, 0x0 },
+ { 0x2134c1, 0x0 },
+ { 0x135c1, 0x0 },
+ { 0x1135c1, 0x0 },
+ { 0x2135c1, 0x0 },
+ { 0x136c1, 0x0 },
+ { 0x1136c1, 0x0 },
+ { 0x2136c1, 0x0 },
+ { 0x137c1, 0x0 },
+ { 0x1137c1, 0x0 },
+ { 0x2137c1, 0x0 },
+ { 0x138c1, 0x0 },
+ { 0x1138c1, 0x0 },
+ { 0x2138c1, 0x0 },
+ { 0x10020, 0x0 },
+ { 0x110020, 0x0 },
+ { 0x210020, 0x0 },
+ { 0x11020, 0x0 },
+ { 0x111020, 0x0 },
+ { 0x211020, 0x0 },
+ { 0x12020, 0x0 },
+ { 0x112020, 0x0 },
+ { 0x212020, 0x0 },
+ { 0x13020, 0x0 },
+ { 0x113020, 0x0 },
+ { 0x213020, 0x0 },
+ { 0x20072, 0x0 },
+ { 0x20073, 0x0 },
+ { 0x20074, 0x0 },
+ { 0x100aa, 0x0 },
+ { 0x110aa, 0x0 },
+ { 0x120aa, 0x0 },
+ { 0x130aa, 0x0 },
+ { 0x20010, 0x0 },
+ { 0x120010, 0x0 },
+ { 0x220010, 0x0 },
+ { 0x20011, 0x0 },
+ { 0x120011, 0x0 },
+ { 0x220011, 0x0 },
+ { 0x100ae, 0x0 },
+ { 0x1100ae, 0x0 },
+ { 0x2100ae, 0x0 },
+ { 0x100af, 0x0 },
+ { 0x1100af, 0x0 },
+ { 0x2100af, 0x0 },
+ { 0x110ae, 0x0 },
+ { 0x1110ae, 0x0 },
+ { 0x2110ae, 0x0 },
+ { 0x110af, 0x0 },
+ { 0x1110af, 0x0 },
+ { 0x2110af, 0x0 },
+ { 0x120ae, 0x0 },
+ { 0x1120ae, 0x0 },
+ { 0x2120ae, 0x0 },
+ { 0x120af, 0x0 },
+ { 0x1120af, 0x0 },
+ { 0x2120af, 0x0 },
+ { 0x130ae, 0x0 },
+ { 0x1130ae, 0x0 },
+ { 0x2130ae, 0x0 },
+ { 0x130af, 0x0 },
+ { 0x1130af, 0x0 },
+ { 0x2130af, 0x0 },
+ { 0x20020, 0x0 },
+ { 0x120020, 0x0 },
+ { 0x220020, 0x0 },
+ { 0x100a0, 0x0 },
+ { 0x100a1, 0x0 },
+ { 0x100a2, 0x0 },
+ { 0x100a3, 0x0 },
+ { 0x100a4, 0x0 },
+ { 0x100a5, 0x0 },
+ { 0x100a6, 0x0 },
+ { 0x100a7, 0x0 },
+ { 0x110a0, 0x0 },
+ { 0x110a1, 0x0 },
+ { 0x110a2, 0x0 },
+ { 0x110a3, 0x0 },
+ { 0x110a4, 0x0 },
+ { 0x110a5, 0x0 },
+ { 0x110a6, 0x0 },
+ { 0x110a7, 0x0 },
+ { 0x120a0, 0x0 },
+ { 0x120a1, 0x0 },
+ { 0x120a2, 0x0 },
+ { 0x120a3, 0x0 },
+ { 0x120a4, 0x0 },
+ { 0x120a5, 0x0 },
+ { 0x120a6, 0x0 },
+ { 0x120a7, 0x0 },
+ { 0x130a0, 0x0 },
+ { 0x130a1, 0x0 },
+ { 0x130a2, 0x0 },
+ { 0x130a3, 0x0 },
+ { 0x130a4, 0x0 },
+ { 0x130a5, 0x0 },
+ { 0x130a6, 0x0 },
+ { 0x130a7, 0x0 },
+ { 0x2007c, 0x0 },
+ { 0x12007c, 0x0 },
+ { 0x22007c, 0x0 },
+ { 0x2007d, 0x0 },
+ { 0x12007d, 0x0 },
+ { 0x22007d, 0x0 },
+ { 0x400fd, 0x0 },
+ { 0x400c0, 0x0 },
+ { 0x90201, 0x0 },
+ { 0x190201, 0x0 },
+ { 0x290201, 0x0 },
+ { 0x90202, 0x0 },
+ { 0x190202, 0x0 },
+ { 0x290202, 0x0 },
+ { 0x90203, 0x0 },
+ { 0x190203, 0x0 },
+ { 0x290203, 0x0 },
+ { 0x90204, 0x0 },
+ { 0x190204, 0x0 },
+ { 0x290204, 0x0 },
+ { 0x90205, 0x0 },
+ { 0x190205, 0x0 },
+ { 0x290205, 0x0 },
+ { 0x90206, 0x0 },
+ { 0x190206, 0x0 },
+ { 0x290206, 0x0 },
+ { 0x90207, 0x0 },
+ { 0x190207, 0x0 },
+ { 0x290207, 0x0 },
+ { 0x90208, 0x0 },
+ { 0x190208, 0x0 },
+ { 0x290208, 0x0 },
+ { 0x10062, 0x0 },
+ { 0x10162, 0x0 },
+ { 0x10262, 0x0 },
+ { 0x10362, 0x0 },
+ { 0x10462, 0x0 },
+ { 0x10562, 0x0 },
+ { 0x10662, 0x0 },
+ { 0x10762, 0x0 },
+ { 0x10862, 0x0 },
+ { 0x11062, 0x0 },
+ { 0x11162, 0x0 },
+ { 0x11262, 0x0 },
+ { 0x11362, 0x0 },
+ { 0x11462, 0x0 },
+ { 0x11562, 0x0 },
+ { 0x11662, 0x0 },
+ { 0x11762, 0x0 },
+ { 0x11862, 0x0 },
+ { 0x12062, 0x0 },
+ { 0x12162, 0x0 },
+ { 0x12262, 0x0 },
+ { 0x12362, 0x0 },
+ { 0x12462, 0x0 },
+ { 0x12562, 0x0 },
+ { 0x12662, 0x0 },
+ { 0x12762, 0x0 },
+ { 0x12862, 0x0 },
+ { 0x13062, 0x0 },
+ { 0x13162, 0x0 },
+ { 0x13262, 0x0 },
+ { 0x13362, 0x0 },
+ { 0x13462, 0x0 },
+ { 0x13562, 0x0 },
+ { 0x13662, 0x0 },
+ { 0x13762, 0x0 },
+ { 0x13862, 0x0 },
+ { 0x20077, 0x0 },
+ { 0x10001, 0x0 },
+ { 0x11001, 0x0 },
+ { 0x12001, 0x0 },
+ { 0x13001, 0x0 },
+ { 0x10040, 0x0 },
+ { 0x10140, 0x0 },
+ { 0x10240, 0x0 },
+ { 0x10340, 0x0 },
+ { 0x10440, 0x0 },
+ { 0x10540, 0x0 },
+ { 0x10640, 0x0 },
+ { 0x10740, 0x0 },
+ { 0x10840, 0x0 },
+ { 0x10030, 0x0 },
+ { 0x10130, 0x0 },
+ { 0x10230, 0x0 },
+ { 0x10330, 0x0 },
+ { 0x10430, 0x0 },
+ { 0x10530, 0x0 },
+ { 0x10630, 0x0 },
+ { 0x10730, 0x0 },
+ { 0x10830, 0x0 },
+ { 0x11040, 0x0 },
+ { 0x11140, 0x0 },
+ { 0x11240, 0x0 },
+ { 0x11340, 0x0 },
+ { 0x11440, 0x0 },
+ { 0x11540, 0x0 },
+ { 0x11640, 0x0 },
+ { 0x11740, 0x0 },
+ { 0x11840, 0x0 },
+ { 0x11030, 0x0 },
+ { 0x11130, 0x0 },
+ { 0x11230, 0x0 },
+ { 0x11330, 0x0 },
+ { 0x11430, 0x0 },
+ { 0x11530, 0x0 },
+ { 0x11630, 0x0 },
+ { 0x11730, 0x0 },
+ { 0x11830, 0x0 },
+ { 0x12040, 0x0 },
+ { 0x12140, 0x0 },
+ { 0x12240, 0x0 },
+ { 0x12340, 0x0 },
+ { 0x12440, 0x0 },
+ { 0x12540, 0x0 },
+ { 0x12640, 0x0 },
+ { 0x12740, 0x0 },
+ { 0x12840, 0x0 },
+ { 0x12030, 0x0 },
+ { 0x12130, 0x0 },
+ { 0x12230, 0x0 },
+ { 0x12330, 0x0 },
+ { 0x12430, 0x0 },
+ { 0x12530, 0x0 },
+ { 0x12630, 0x0 },
+ { 0x12730, 0x0 },
+ { 0x12830, 0x0 },
+ { 0x13040, 0x0 },
+ { 0x13140, 0x0 },
+ { 0x13240, 0x0 },
+ { 0x13340, 0x0 },
+ { 0x13440, 0x0 },
+ { 0x13540, 0x0 },
+ { 0x13640, 0x0 },
+ { 0x13740, 0x0 },
+ { 0x13840, 0x0 },
+ { 0x13030, 0x0 },
+ { 0x13130, 0x0 },
+ { 0x13230, 0x0 },
+ { 0x13330, 0x0 },
+ { 0x13430, 0x0 },
+ { 0x13530, 0x0 },
+ { 0x13630, 0x0 },
+ { 0x13730, 0x0 },
+ { 0x13830, 0x0 },
+};
+
+/* P0 message block paremeter for training firmware */
+struct dram_cfg_param ddr_fsp0_cfg[] = {
+ {0xd0000, 0x0},
+ {0x54003, 0xbb8},
+ {0x54004, 0x2},
+ {0x54005, 0x2228},
+ {0x54006, 0x11},
+ {0x54008, 0x131f},
+ {0x54009, 0xc8},
+ {0x5400b, 0x2},
+ {0x5400d, 0x100},
+ {0x54012, 0x110},
+ {0x54019, 0x2dd4},
+ {0x5401a, 0x31},
+ {0x5401b, 0x4d66},
+ {0x5401c, 0x4d00},
+ {0x5401e, 0x16},
+ {0x5401f, 0x2dd4},
+ {0x54020, 0x31},
+ {0x54021, 0x4d66},
+ {0x54022, 0x4d00},
+ {0x54024, 0x16},
+ {0x5402b, 0x1000},
+ {0x5402c, 0x1},
+ {0x54032, 0xd400},
+ {0x54033, 0x312d},
+ {0x54034, 0x6600},
+ {0x54035, 0x4d},
+ {0x54036, 0x4d},
+ {0x54037, 0x1600},
+ {0x54038, 0xd400},
+ {0x54039, 0x312d},
+ {0x5403a, 0x6600},
+ {0x5403b, 0x4d},
+ {0x5403c, 0x4d},
+ {0x5403d, 0x1600},
+ {0xd0000, 0x1},
+};
+
+/* P1 message block paremeter for training firmware */
+static struct dram_cfg_param ddr_fsp1_cfg[] = {
+ {0xd0000, 0x0},
+ {0x54002, 0x101},
+ {0x54003, 0x190},
+ {0x54004, 0x2},
+ {0x54005, 0x2228},
+ {0x54006, 0x11},
+ {0x54008, 0x121f},
+ {0x54009, 0xc8},
+ {0x5400b, 0x2},
+ {0x5400d, 0x100},
+ {0x54012, 0x110},
+ {0x54019, 0x84},
+ {0x5401a, 0x31},
+ {0x5401b, 0x4d66},
+ {0x5401c, 0x4d00},
+ {0x5401e, 0x16},
+ {0x5401f, 0x84},
+ {0x54020, 0x31},
+ {0x54021, 0x4d66},
+ {0x54022, 0x4d00},
+ {0x54024, 0x16},
+ {0x5402b, 0x1000},
+ {0x5402c, 0x1},
+ {0x54032, 0x8400},
+ {0x54033, 0x3100},
+ {0x54034, 0x6600},
+ {0x54035, 0x4d},
+ {0x54036, 0x4d},
+ {0x54037, 0x1600},
+ {0x54038, 0x8400},
+ {0x54039, 0x3100},
+ {0x5403a, 0x6600},
+ {0x5403b, 0x4d},
+ {0x5403c, 0x4d},
+ {0x5403d, 0x1600},
+ {0xd0000, 0x1},
+};
+
+/* P2 message block paremeter for training firmware */
+static struct dram_cfg_param ddr_fsp2_cfg[] = {
+ {0xd0000, 0x0},
+ {0x54002, 0x102},
+ {0x54003, 0x64},
+ {0x54004, 0x2},
+ {0x54005, 0x2228},
+ {0x54006, 0x11},
+ {0x54008, 0x121f},
+ {0x54009, 0xc8},
+ {0x5400b, 0x2},
+ {0x5400d, 0x100},
+ {0x54012, 0x110},
+ {0x54019, 0x84},
+ {0x5401a, 0x31},
+ {0x5401b, 0x4d66},
+ {0x5401c, 0x4d00},
+ {0x5401e, 0x16},
+ {0x5401f, 0x84},
+ {0x54020, 0x31},
+ {0x54021, 0x4d66},
+ {0x54022, 0x4d00},
+ {0x54024, 0x16},
+ {0x5402b, 0x1000},
+ {0x5402c, 0x1},
+ {0x54032, 0x8400},
+ {0x54033, 0x3100},
+ {0x54034, 0x6600},
+ {0x54035, 0x4d},
+ {0x54036, 0x4d},
+ {0x54037, 0x1600},
+ {0x54038, 0x8400},
+ {0x54039, 0x3100},
+ {0x5403a, 0x6600},
+ {0x5403b, 0x4d},
+ {0x5403c, 0x4d},
+ {0x5403d, 0x1600},
+ {0xd0000, 0x1},
+};
+
+/* P0 2D message block paremeter for training firmware */
+static struct dram_cfg_param ddr_fsp0_2d_cfg[] = {
+ {0xd0000, 0x0},
+ {0x54003, 0xbb8},
+ {0x54004, 0x2},
+ {0x54005, 0x2228},
+ {0x54006, 0x11},
+ {0x54008, 0x61},
+ {0x54009, 0xc8},
+ {0x5400b, 0x2},
+ {0x5400f, 0x100},
+ {0x54010, 0x1f7f},
+ {0x54012, 0x110},
+ {0x54019, 0x2dd4},
+ {0x5401a, 0x31},
+ {0x5401b, 0x4d66},
+ {0x5401c, 0x4d00},
+ {0x5401e, 0x16},
+ {0x5401f, 0x2dd4},
+ {0x54020, 0x31},
+ {0x54021, 0x4d66},
+ {0x54022, 0x4d00},
+ {0x54024, 0x16},
+ {0x5402b, 0x1000},
+ {0x5402c, 0x1},
+ {0x54032, 0xd400},
+ {0x54033, 0x312d},
+ {0x54034, 0x6600},
+ {0x54035, 0x4d},
+ {0x54036, 0x4d},
+ {0x54037, 0x1600},
+ {0x54038, 0xd400},
+ {0x54039, 0x312d},
+ {0x5403a, 0x6600},
+ {0x5403b, 0x4d},
+ {0x5403c, 0x4d},
+ {0x5403d, 0x1600},
+ { 0xd0000, 0x1 },
+};
+
+/* DRAM PHY init engine image */
+static struct dram_cfg_param ddr_phy_pie[] = {
+ {0xd0000, 0x0},
+ {0x90000, 0x10},
+ {0x90001, 0x400},
+ {0x90002, 0x10e},
+ {0x90003, 0x0},
+ {0x90004, 0x0},
+ {0x90005, 0x8},
+ {0x90029, 0xb},
+ {0x9002a, 0x480},
+ {0x9002b, 0x109},
+ {0x9002c, 0x8},
+ {0x9002d, 0x448},
+ {0x9002e, 0x139},
+ {0x9002f, 0x8},
+ {0x90030, 0x478},
+ {0x90031, 0x109},
+ {0x90032, 0x0},
+ {0x90033, 0xe8},
+ {0x90034, 0x109},
+ {0x90035, 0x2},
+ {0x90036, 0x10},
+ {0x90037, 0x139},
+ {0x90038, 0xf},
+ {0x90039, 0x7c0},
+ {0x9003a, 0x139},
+ {0x9003b, 0x44},
+ {0x9003c, 0x630},
+ {0x9003d, 0x159},
+ {0x9003e, 0x14f},
+ {0x9003f, 0x630},
+ {0x90040, 0x159},
+ {0x90041, 0x47},
+ {0x90042, 0x630},
+ {0x90043, 0x149},
+ {0x90044, 0x4f},
+ {0x90045, 0x630},
+ {0x90046, 0x179},
+ {0x90047, 0x8},
+ {0x90048, 0xe0},
+ {0x90049, 0x109},
+ {0x9004a, 0x0},
+ {0x9004b, 0x7c8},
+ {0x9004c, 0x109},
+ {0x9004d, 0x0},
+ {0x9004e, 0x1},
+ {0x9004f, 0x8},
+ {0x90050, 0x0},
+ {0x90051, 0x45a},
+ {0x90052, 0x9},
+ {0x90053, 0x0},
+ {0x90054, 0x448},
+ {0x90055, 0x109},
+ {0x90056, 0x40},
+ {0x90057, 0x630},
+ {0x90058, 0x179},
+ {0x90059, 0x1},
+ {0x9005a, 0x618},
+ {0x9005b, 0x109},
+ {0x9005c, 0x40c0},
+ {0x9005d, 0x630},
+ {0x9005e, 0x149},
+ {0x9005f, 0x8},
+ {0x90060, 0x4},
+ {0x90061, 0x48},
+ {0x90062, 0x4040},
+ {0x90063, 0x630},
+ {0x90064, 0x149},
+ {0x90065, 0x0},
+ {0x90066, 0x4},
+ {0x90067, 0x48},
+ {0x90068, 0x40},
+ {0x90069, 0x630},
+ {0x9006a, 0x149},
+ {0x9006b, 0x10},
+ {0x9006c, 0x4},
+ {0x9006d, 0x18},
+ {0x9006e, 0x0},
+ {0x9006f, 0x4},
+ {0x90070, 0x78},
+ {0x90071, 0x549},
+ {0x90072, 0x630},
+ {0x90073, 0x159},
+ {0x90074, 0xd49},
+ {0x90075, 0x630},
+ {0x90076, 0x159},
+ {0x90077, 0x94a},
+ {0x90078, 0x630},
+ {0x90079, 0x159},
+ {0x9007a, 0x441},
+ {0x9007b, 0x630},
+ {0x9007c, 0x149},
+ {0x9007d, 0x42},
+ {0x9007e, 0x630},
+ {0x9007f, 0x149},
+ {0x90080, 0x1},
+ {0x90081, 0x630},
+ {0x90082, 0x149},
+ {0x90083, 0x0},
+ {0x90084, 0xe0},
+ {0x90085, 0x109},
+ {0x90086, 0xa},
+ {0x90087, 0x10},
+ {0x90088, 0x109},
+ {0x90089, 0x9},
+ {0x9008a, 0x3c0},
+ {0x9008b, 0x149},
+ {0x9008c, 0x9},
+ {0x9008d, 0x3c0},
+ {0x9008e, 0x159},
+ {0x9008f, 0x18},
+ {0x90090, 0x10},
+ {0x90091, 0x109},
+ {0x90092, 0x0},
+ {0x90093, 0x3c0},
+ {0x90094, 0x109},
+ {0x90095, 0x18},
+ {0x90096, 0x4},
+ {0x90097, 0x48},
+ {0x90098, 0x18},
+ {0x90099, 0x4},
+ {0x9009a, 0x58},
+ {0x9009b, 0xa},
+ {0x9009c, 0x10},
+ {0x9009d, 0x109},
+ {0x9009e, 0x2},
+ {0x9009f, 0x10},
+ {0x900a0, 0x109},
+ {0x900a1, 0x5},
+ {0x900a2, 0x7c0},
+ {0x900a3, 0x109},
+ {0x900a4, 0x10},
+ {0x900a5, 0x10},
+ {0x900a6, 0x109},
+ {0x40000, 0x811},
+ {0x40020, 0x880},
+ {0x40040, 0x0},
+ {0x40060, 0x0},
+ {0x40001, 0x4008},
+ {0x40021, 0x83},
+ {0x40041, 0x4f},
+ {0x40061, 0x0},
+ {0x40002, 0x4040},
+ {0x40022, 0x83},
+ {0x40042, 0x51},
+ {0x40062, 0x0},
+ {0x40003, 0x811},
+ {0x40023, 0x880},
+ {0x40043, 0x0},
+ {0x40063, 0x0},
+ {0x40004, 0x720},
+ {0x40024, 0xf},
+ {0x40044, 0x1740},
+ {0x40064, 0x0},
+ {0x40005, 0x16},
+ {0x40025, 0x83},
+ {0x40045, 0x4b},
+ {0x40065, 0x0},
+ {0x40006, 0x716},
+ {0x40026, 0xf},
+ {0x40046, 0x2001},
+ {0x40066, 0x0},
+ {0x40007, 0x716},
+ {0x40027, 0xf},
+ {0x40047, 0x2800},
+ {0x40067, 0x0},
+ {0x40008, 0x716},
+ {0x40028, 0xf},
+ {0x40048, 0xf00},
+ {0x40068, 0x0},
+ {0x40009, 0x720},
+ {0x40029, 0xf},
+ {0x40049, 0x1400},
+ {0x40069, 0x0},
+ {0x4000a, 0xe08},
+ {0x4002a, 0xc15},
+ {0x4004a, 0x0},
+ {0x4006a, 0x0},
+ {0x4000b, 0x623},
+ {0x4002b, 0x15},
+ {0x4004b, 0x0},
+ {0x4006b, 0x0},
+ {0x4000c, 0x4028},
+ {0x4002c, 0x80},
+ {0x4004c, 0x0},
+ {0x4006c, 0x0},
+ {0x4000d, 0xe08},
+ {0x4002d, 0xc1a},
+ {0x4004d, 0x0},
+ {0x4006d, 0x0},
+ {0x4000e, 0x623},
+ {0x4002e, 0x1a},
+ {0x4004e, 0x0},
+ {0x4006e, 0x0},
+ {0x4000f, 0x4040},
+ {0x4002f, 0x80},
+ {0x4004f, 0x0},
+ {0x4006f, 0x0},
+ {0x40010, 0x2604},
+ {0x40030, 0x15},
+ {0x40050, 0x0},
+ {0x40070, 0x0},
+ {0x40011, 0x708},
+ {0x40031, 0x5},
+ {0x40051, 0x0},
+ {0x40071, 0x2002},
+ {0x40012, 0x8},
+ {0x40032, 0x80},
+ {0x40052, 0x0},
+ {0x40072, 0x0},
+ {0x40013, 0x2604},
+ {0x40033, 0x1a},
+ {0x40053, 0x0},
+ {0x40073, 0x0},
+ {0x40014, 0x708},
+ {0x40034, 0xa},
+ {0x40054, 0x0},
+ {0x40074, 0x2002},
+ {0x40015, 0x4040},
+ {0x40035, 0x80},
+ {0x40055, 0x0},
+ {0x40075, 0x0},
+ {0x40016, 0x60a},
+ {0x40036, 0x15},
+ {0x40056, 0x1200},
+ {0x40076, 0x0},
+ {0x40017, 0x61a},
+ {0x40037, 0x15},
+ {0x40057, 0x1300},
+ {0x40077, 0x0},
+ {0x40018, 0x60a},
+ {0x40038, 0x1a},
+ {0x40058, 0x1200},
+ {0x40078, 0x0},
+ {0x40019, 0x642},
+ {0x40039, 0x1a},
+ {0x40059, 0x1300},
+ {0x40079, 0x0},
+ {0x4001a, 0x4808},
+ {0x4003a, 0x880},
+ {0x4005a, 0x0},
+ {0x4007a, 0x0},
+ {0x900a7, 0x0},
+ {0x900a8, 0x790},
+ {0x900a9, 0x11a},
+ {0x900aa, 0x8},
+ {0x900ab, 0x7aa},
+ {0x900ac, 0x2a},
+ {0x900ad, 0x10},
+ {0x900ae, 0x7b2},
+ {0x900af, 0x2a},
+ {0x900b0, 0x0},
+ {0x900b1, 0x7c8},
+ {0x900b2, 0x109},
+ {0x900b3, 0x10},
+ {0x900b4, 0x2a8},
+ {0x900b5, 0x129},
+ {0x900b6, 0x8},
+ {0x900b7, 0x370},
+ {0x900b8, 0x129},
+ {0x900b9, 0xa},
+ {0x900ba, 0x3c8},
+ {0x900bb, 0x1a9},
+ {0x900bc, 0xc},
+ {0x900bd, 0x408},
+ {0x900be, 0x199},
+ {0x900bf, 0x14},
+ {0x900c0, 0x790},
+ {0x900c1, 0x11a},
+ {0x900c2, 0x8},
+ {0x900c3, 0x4},
+ {0x900c4, 0x18},
+ {0x900c5, 0xe},
+ {0x900c6, 0x408},
+ {0x900c7, 0x199},
+ {0x900c8, 0x8},
+ {0x900c9, 0x8568},
+ {0x900ca, 0x108},
+ {0x900cb, 0x18},
+ {0x900cc, 0x790},
+ {0x900cd, 0x16a},
+ {0x900ce, 0x8},
+ {0x900cf, 0x1d8},
+ {0x900d0, 0x169},
+ {0x900d1, 0x10},
+ {0x900d2, 0x8558},
+ {0x900d3, 0x168},
+ {0x900d4, 0x70},
+ {0x900d5, 0x788},
+ {0x900d6, 0x16a},
+ {0x900d7, 0x1ff8},
+ {0x900d8, 0x85a8},
+ {0x900d9, 0x1e8},
+ {0x900da, 0x50},
+ {0x900db, 0x798},
+ {0x900dc, 0x16a},
+ {0x900dd, 0x60},
+ {0x900de, 0x7a0},
+ {0x900df, 0x16a},
+ {0x900e0, 0x8},
+ {0x900e1, 0x8310},
+ {0x900e2, 0x168},
+ {0x900e3, 0x8},
+ {0x900e4, 0xa310},
+ {0x900e5, 0x168},
+ {0x900e6, 0xa},
+ {0x900e7, 0x408},
+ {0x900e8, 0x169},
+ {0x900e9, 0x6e},
+ {0x900ea, 0x0},
+ {0x900eb, 0x68},
+ {0x900ec, 0x0},
+ {0x900ed, 0x408},
+ {0x900ee, 0x169},
+ {0x900ef, 0x0},
+ {0x900f0, 0x8310},
+ {0x900f1, 0x168},
+ {0x900f2, 0x0},
+ {0x900f3, 0xa310},
+ {0x900f4, 0x168},
+ {0x900f5, 0x1ff8},
+ {0x900f6, 0x85a8},
+ {0x900f7, 0x1e8},
+ {0x900f8, 0x68},
+ {0x900f9, 0x798},
+ {0x900fa, 0x16a},
+ {0x900fb, 0x78},
+ {0x900fc, 0x7a0},
+ {0x900fd, 0x16a},
+ {0x900fe, 0x68},
+ {0x900ff, 0x790},
+ {0x90100, 0x16a},
+ {0x90101, 0x8},
+ {0x90102, 0x8b10},
+ {0x90103, 0x168},
+ {0x90104, 0x8},
+ {0x90105, 0xab10},
+ {0x90106, 0x168},
+ {0x90107, 0xa},
+ {0x90108, 0x408},
+ {0x90109, 0x169},
+ {0x9010a, 0x58},
+ {0x9010b, 0x0},
+ {0x9010c, 0x68},
+ {0x9010d, 0x0},
+ {0x9010e, 0x408},
+ {0x9010f, 0x169},
+ {0x90110, 0x0},
+ {0x90111, 0x8b10},
+ {0x90112, 0x168},
+ {0x90113, 0x0},
+ {0x90114, 0xab10},
+ {0x90115, 0x168},
+ {0x90116, 0x0},
+ {0x90117, 0x1d8},
+ {0x90118, 0x169},
+ {0x90119, 0x80},
+ {0x9011a, 0x790},
+ {0x9011b, 0x16a},
+ {0x9011c, 0x18},
+ {0x9011d, 0x7aa},
+ {0x9011e, 0x6a},
+ {0x9011f, 0xa},
+ {0x90120, 0x0},
+ {0x90121, 0x1e9},
+ {0x90122, 0x8},
+ {0x90123, 0x8080},
+ {0x90124, 0x108},
+ {0x90125, 0xf},
+ {0x90126, 0x408},
+ {0x90127, 0x169},
+ {0x90128, 0xc},
+ {0x90129, 0x0},
+ {0x9012a, 0x68},
+ {0x9012b, 0x9},
+ {0x9012c, 0x0},
+ {0x9012d, 0x1a9},
+ {0x9012e, 0x0},
+ {0x9012f, 0x408},
+ {0x90130, 0x169},
+ {0x90131, 0x0},
+ {0x90132, 0x8080},
+ {0x90133, 0x108},
+ {0x90134, 0x8},
+ {0x90135, 0x7aa},
+ {0x90136, 0x6a},
+ {0x90137, 0x0},
+ {0x90138, 0x8568},
+ {0x90139, 0x108},
+ {0x9013a, 0xb7},
+ {0x9013b, 0x790},
+ {0x9013c, 0x16a},
+ {0x9013d, 0x1f},
+ {0x9013e, 0x0},
+ {0x9013f, 0x68},
+ {0x90140, 0x8},
+ {0x90141, 0x8558},
+ {0x90142, 0x168},
+ {0x90143, 0xf},
+ {0x90144, 0x408},
+ {0x90145, 0x169},
+ {0x90146, 0xc},
+ {0x90147, 0x0},
+ {0x90148, 0x68},
+ {0x90149, 0x0},
+ {0x9014a, 0x408},
+ {0x9014b, 0x169},
+ {0x9014c, 0x0},
+ {0x9014d, 0x8558},
+ {0x9014e, 0x168},
+ {0x9014f, 0x8},
+ {0x90150, 0x3c8},
+ {0x90151, 0x1a9},
+ {0x90152, 0x3},
+ {0x90153, 0x370},
+ {0x90154, 0x129},
+ {0x90155, 0x20},
+ {0x90156, 0x2aa},
+ {0x90157, 0x9},
+ {0x90158, 0x0},
+ {0x90159, 0x400},
+ {0x9015a, 0x10e},
+ {0x9015b, 0x8},
+ {0x9015c, 0xe8},
+ {0x9015d, 0x109},
+ {0x9015e, 0x0},
+ {0x9015f, 0x8140},
+ {0x90160, 0x10c},
+ {0x90161, 0x10},
+ {0x90162, 0x8138},
+ {0x90163, 0x10c},
+ {0x90164, 0x8},
+ {0x90165, 0x7c8},
+ {0x90166, 0x101},
+ {0x90167, 0x8},
+ {0x90168, 0x0},
+ {0x90169, 0x8},
+ {0x9016a, 0x8},
+ {0x9016b, 0x448},
+ {0x9016c, 0x109},
+ {0x9016d, 0xf},
+ {0x9016e, 0x7c0},
+ {0x9016f, 0x109},
+ {0x90170, 0x0},
+ {0x90171, 0xe8},
+ {0x90172, 0x109},
+ {0x90173, 0x47},
+ {0x90174, 0x630},
+ {0x90175, 0x109},
+ {0x90176, 0x8},
+ {0x90177, 0x618},
+ {0x90178, 0x109},
+ {0x90179, 0x8},
+ {0x9017a, 0xe0},
+ {0x9017b, 0x109},
+ {0x9017c, 0x0},
+ {0x9017d, 0x7c8},
+ {0x9017e, 0x109},
+ {0x9017f, 0x8},
+ {0x90180, 0x8140},
+ {0x90181, 0x10c},
+ {0x90182, 0x0},
+ {0x90183, 0x1},
+ {0x90184, 0x8},
+ {0x90185, 0x8},
+ {0x90186, 0x4},
+ {0x90187, 0x8},
+ {0x90188, 0x8},
+ {0x90189, 0x7c8},
+ {0x9018a, 0x101},
+ {0x90006, 0x0},
+ {0x90007, 0x0},
+ {0x90008, 0x8},
+ {0x90009, 0x0},
+ {0x9000a, 0x0},
+ {0x9000b, 0x0},
+ {0xd00e7, 0x400},
+ {0x90017, 0x0},
+ {0x9001f, 0x2a},
+ {0x90026, 0x6a},
+ {0x400d0, 0x0},
+ {0x400d1, 0x101},
+ {0x400d2, 0x105},
+ {0x400d3, 0x107},
+ {0x400d4, 0x10f},
+ {0x400d5, 0x202},
+ {0x400d6, 0x20a},
+ {0x400d7, 0x20b},
+ {0x2003a, 0x2},
+ {0x2000b, 0x5d},
+ {0x2000c, 0xbb},
+ {0x2000d, 0x753},
+ {0x2000e, 0x2c},
+ {0x12000b, 0xc},
+ {0x12000c, 0x19},
+ {0x12000d, 0xfa},
+ {0x12000e, 0x10},
+ {0x22000b, 0x3},
+ {0x22000c, 0x6},
+ {0x22000d, 0x3e},
+ {0x22000e, 0x10},
+ {0x9000c, 0x0},
+ {0x9000d, 0x173},
+ {0x9000e, 0x60},
+ {0x9000f, 0x6110},
+ {0x90010, 0x2152},
+ {0x90011, 0xdfbd},
+ {0x90012, 0x60},
+ {0x90013, 0x6152},
+ {0x20010, 0x5a},
+ {0x20011, 0x3},
+ {0x120010, 0x5a},
+ {0x120011, 0x3},
+ {0x220010, 0x5a},
+ {0x220011, 0x3},
+ {0x40080, 0xe0},
+ {0x40081, 0x12},
+ {0x40082, 0xe0},
+ {0x40083, 0x12},
+ {0x40084, 0xe0},
+ {0x40085, 0x12},
+ {0x140080, 0xe0},
+ {0x140081, 0x12},
+ {0x140082, 0xe0},
+ {0x140083, 0x12},
+ {0x140084, 0xe0},
+ {0x140085, 0x12},
+ {0x240080, 0xe0},
+ {0x240081, 0x12},
+ {0x240082, 0xe0},
+ {0x240083, 0x12},
+ {0x240084, 0xe0},
+ {0x240085, 0x12},
+ {0x400fd, 0xf},
+ {0x10011, 0x1},
+ {0x10012, 0x1},
+ {0x10013, 0x180},
+ {0x10018, 0x1},
+ {0x10002, 0x6209},
+ {0x100b2, 0x1},
+ {0x101b4, 0x1},
+ {0x102b4, 0x1},
+ {0x103b4, 0x1},
+ {0x104b4, 0x1},
+ {0x105b4, 0x1},
+ {0x106b4, 0x1},
+ {0x107b4, 0x1},
+ {0x108b4, 0x1},
+ {0x11011, 0x1},
+ {0x11012, 0x1},
+ {0x11013, 0x180},
+ {0x11018, 0x1},
+ {0x11002, 0x6209},
+ {0x110b2, 0x1},
+ {0x111b4, 0x1},
+ {0x112b4, 0x1},
+ {0x113b4, 0x1},
+ {0x114b4, 0x1},
+ {0x115b4, 0x1},
+ {0x116b4, 0x1},
+ {0x117b4, 0x1},
+ {0x118b4, 0x1},
+ {0x12011, 0x1},
+ {0x12012, 0x1},
+ {0x12013, 0x180},
+ {0x12018, 0x1},
+ {0x12002, 0x6209},
+ {0x120b2, 0x1},
+ {0x121b4, 0x1},
+ {0x122b4, 0x1},
+ {0x123b4, 0x1},
+ {0x124b4, 0x1},
+ {0x125b4, 0x1},
+ {0x126b4, 0x1},
+ {0x127b4, 0x1},
+ {0x128b4, 0x1},
+ {0x13011, 0x1},
+ {0x13012, 0x1},
+ {0x13013, 0x180},
+ {0x13018, 0x1},
+ {0x13002, 0x6209},
+ {0x130b2, 0x1},
+ {0x131b4, 0x1},
+ {0x132b4, 0x1},
+ {0x133b4, 0x1},
+ {0x134b4, 0x1},
+ {0x135b4, 0x1},
+ {0x136b4, 0x1},
+ {0x137b4, 0x1},
+ {0x138b4, 0x1},
+ {0x2003a, 0x2},
+ {0xc0080, 0x2},
+ {0xd0000, 0x1}
+};
+
+static struct dram_fsp_msg ddr_dram_fsp_msg[] = {
+ {
+ /* P0 3000mts 1D */
+ .drate = 3000,
+ .fw_type = FW_1D_IMAGE,
+ .fsp_cfg = ddr_fsp0_cfg,
+ .fsp_cfg_num = ARRAY_SIZE(ddr_fsp0_cfg),
+ },
+ {
+ /* P1 400mts 1D */
+ .drate = 400,
+ .fw_type = FW_1D_IMAGE,
+ .fsp_cfg = ddr_fsp1_cfg,
+ .fsp_cfg_num = ARRAY_SIZE(ddr_fsp1_cfg),
+ },
+ {
+ /* P2 100mts 1D */
+ .drate = 100,
+ .fw_type = FW_1D_IMAGE,
+ .fsp_cfg = ddr_fsp2_cfg,
+ .fsp_cfg_num = ARRAY_SIZE(ddr_fsp2_cfg),
+ },
+ {
+ /* P0 3000mts 2D */
+ .drate = 3000,
+ .fw_type = FW_2D_IMAGE,
+ .fsp_cfg = ddr_fsp0_2d_cfg,
+ .fsp_cfg_num = ARRAY_SIZE(ddr_fsp0_2d_cfg),
+ },
+};
+
+/* ddr timing config params */
+struct dram_timing_info dram_timing = {
+ .ddrc_cfg = ddr_ddrc_cfg,
+ .ddrc_cfg_num = ARRAY_SIZE(ddr_ddrc_cfg),
+ .ddrphy_cfg = ddr_ddrphy_cfg,
+ .ddrphy_cfg_num = ARRAY_SIZE(ddr_ddrphy_cfg),
+ .fsp_msg = ddr_dram_fsp_msg,
+ .fsp_msg_num = ARRAY_SIZE(ddr_dram_fsp_msg),
+ .ddrphy_trained_csr = ddr_ddrphy_trained_csr,
+ .ddrphy_trained_csr_num = ARRAY_SIZE(ddr_ddrphy_trained_csr),
+ .ddrphy_pie = ddr_phy_pie,
+ .ddrphy_pie_num = ARRAY_SIZE(ddr_phy_pie),
+ .fsp_table = { 3000, 400, 100, },
+};
--- /dev/null
+// SPDX-License-Identifier: GPL-2.0-or-later
+/*
+ * Copyright (C) 2019-2020 PHYTEC Messtechnik GmbH
+ * Author: Teresa Remmet <t.remmet@phytec.de>
+ */
+
+#include <common.h>
+#include <asm/arch/sys_proto.h>
+#include <asm/io.h>
+#include <asm/mach-imx/boot_mode.h>
+#include <env.h>
+#include <miiphy.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+static int setup_fec(void)
+{
+ struct iomuxc_gpr_base_regs *gpr =
+ (struct iomuxc_gpr_base_regs *)IOMUXC_GPR_BASE_ADDR;
+
+ /* Use 125M anatop REF_CLK1 for ENET1, not from external */
+ clrsetbits_le32(&gpr->gpr[1], 0x2000, 0);
+
+ return 0;
+}
+
+int board_init(void)
+{
+ setup_fec();
+
+ return 0;
+}
+
+int board_mmc_get_env_dev(int devno)
+{
+ return devno;
+}
+
+int board_late_init(void)
+{
+ switch (get_boot_device()) {
+ case SD2_BOOT:
+ env_set_ulong("mmcdev", 1);
+ break;
+ case MMC3_BOOT:
+ env_set_ulong("mmcdev", 2);
+ break;
+ default:
+ break;
+ }
+
+ return 0;
+}
--- /dev/null
+// SPDX-License-Identifier: GPL-2.0-or-later
+/*
+ * Copyright (C) 2019-2020 PHYTEC Messtechnik GmbH
+ * Author: Teresa Remmet <t.remmet@phytec.de>
+ */
+
+#include <common.h>
+#include <asm/arch/clock.h>
+#include <asm/arch/ddr.h>
+#include <asm/arch/imx8mm_pins.h>
+#include <asm/arch/sys_proto.h>
+#include <asm/mach-imx/boot_mode.h>
+#include <asm/mach-imx/iomux-v3.h>
+#include <dm/device.h>
+#include <dm/uclass.h>
+#include <hang.h>
+#include <init.h>
+#include <log.h>
+#include <spl.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+int spl_board_boot_device(enum boot_device boot_dev_spl)
+{
+ switch (boot_dev_spl) {
+ case SD2_BOOT:
+ case MMC2_BOOT:
+ return BOOT_DEVICE_MMC1;
+ case SD3_BOOT:
+ case MMC3_BOOT:
+ return BOOT_DEVICE_MMC2;
+ case QSPI_BOOT:
+ return BOOT_DEVICE_NOR;
+ case USB_BOOT:
+ return BOOT_DEVICE_BOARD;
+ default:
+ return BOOT_DEVICE_NONE;
+ }
+}
+
+void spl_dram_init(void)
+{
+ ddr_init(&dram_timing);
+}
+
+void spl_board_init(void)
+{
+ /* Serial download mode */
+ if (is_usb_boot()) {
+ puts("Back to ROM, SDP\n");
+ restore_boot_params();
+ }
+ puts("Normal Boot\n");
+}
+
+#ifdef CONFIG_SPL_LOAD_FIT
+int board_fit_config_name_match(const char *name)
+{
+ /* Just empty function now - can't decide what to choose */
+ debug("%s: %s\n", __func__, name);
+
+ return 0;
+}
+#endif
+
+#define UART_PAD_CTRL (PAD_CTL_DSE6 | PAD_CTL_FSEL1)
+#define WDOG_PAD_CTRL (PAD_CTL_DSE6 | PAD_CTL_ODE)
+
+static iomux_v3_cfg_t const uart_pads[] = {
+ IMX8MM_PAD_UART3_RXD_UART3_RX | MUX_PAD_CTRL(UART_PAD_CTRL),
+ IMX8MM_PAD_UART3_TXD_UART3_TX | MUX_PAD_CTRL(UART_PAD_CTRL),
+};
+
+static iomux_v3_cfg_t const wdog_pads[] = {
+ IMX8MM_PAD_GPIO1_IO02_WDOG1_WDOG_B | MUX_PAD_CTRL(WDOG_PAD_CTRL),
+};
+
+int board_early_init_f(void)
+{
+ struct wdog_regs *wdog = (struct wdog_regs *)WDOG1_BASE_ADDR;
+
+ imx_iomux_v3_setup_multiple_pads(wdog_pads, ARRAY_SIZE(wdog_pads));
+
+ set_wdog_reset(wdog);
+
+ imx_iomux_v3_setup_multiple_pads(uart_pads, ARRAY_SIZE(uart_pads));
+
+ return 0;
+}
+
+void board_init_f(ulong dummy)
+{
+ struct udevice *dev;
+ int ret;
+
+ arch_cpu_init();
+
+ init_uart_clk(2);
+
+ board_early_init_f();
+
+ timer_init();
+
+ preloader_console_init();
+
+ /* Clear the BSS. */
+ memset(__bss_start, 0, __bss_end - __bss_start);
+
+ ret = spl_early_init();
+ if (ret) {
+ debug("spl_early_init() failed: %d\n", ret);
+ hang();
+ }
+
+ ret = uclass_get_device_by_name(UCLASS_CLK,
+ "clock-controller@30380000", &dev);
+ if (ret < 0) {
+ printf("Failed to find clock node. Check device tree\n");
+ hang();
+ }
+
+ enable_tzc380();
+
+ /* DDR initialization */
+ spl_dram_init();
+
+ board_init_r(NULL, 0);
+}
--- /dev/null
+CONFIG_ARM=y
+CONFIG_ARCH_MX6=y
+CONFIG_MX6QDL=y
+CONFIG_SYS_TEXT_BASE=0x17800000
+CONFIG_SPL_GPIO_SUPPORT=y
+CONFIG_SPL_LIBCOMMON_SUPPORT=y
+CONFIG_SPL_LIBGENERIC_SUPPORT=y
+CONFIG_SYS_MALLOC_F_LEN=0x4000
+CONFIG_NR_DRAM_BANKS=1
+CONFIG_ENV_SIZE=0x2000
+CONFIG_ENV_OFFSET=0xC0000
+CONFIG_ENV_SECT_SIZE=0x10000
+CONFIG_SYS_SPI_U_BOOT_OFFS=0x11400
+# CONFIG_GE_RTC is not set
+CONFIG_TARGET_GE_B1X5V2=y
+CONFIG_SPL_TEXT_BASE=0x00908000
+CONFIG_SPL_SERIAL_SUPPORT=y
+CONFIG_BOOTCOUNT_BOOTLIMIT=10
+CONFIG_SPL=y
+CONFIG_DEBUG_UART_BASE=0x21ec000
+CONFIG_DEBUG_UART_CLOCK=24000000
+CONFIG_SPL_LIBDISK_SUPPORT=y
+CONFIG_SPL_SPI_FLASH_SUPPORT=y
+CONFIG_SPL_SPI_SUPPORT=y
+CONFIG_SPL_PAYLOAD="u-boot.img"
+CONFIG_DEFAULT_DEVICE_TREE="imx6dl-b1x5v2"
+CONFIG_DEBUG_UART=y
+CONFIG_FIT=y
+CONFIG_OF_BOARD_SETUP=y
+CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=arch/arm/mach-imx/spl_sd.cfg"
+CONFIG_BOOTDELAY=1
+CONFIG_SYS_CONSOLE_OVERWRITE_ROUTINE=y
+CONFIG_LOG_MAX_LEVEL=8
+CONFIG_LOG_DEFAULT_LEVEL=4
+CONFIG_SUPPORT_RAW_INITRD=y
+CONFIG_DEFAULT_FDT_FILE="imx6dl-b1x5v2.dtb"
+CONFIG_MISC_INIT_R=y
+CONFIG_BOUNCE_BUFFER=y
+CONFIG_BOARD_EARLY_INIT_F=y
+CONFIG_SPL_SPI_LOAD=y
+CONFIG_SPL_USB_HOST_SUPPORT=y
+CONFIG_SPL_USB_GADGET=y
+CONFIG_SPL_USB_SDP_SUPPORT=y
+CONFIG_HUSH_PARSER=y
+CONFIG_CMD_BOOTZ=y
+CONFIG_CMD_GREPENV=y
+CONFIG_CMD_MEMINFO=y
+CONFIG_CMD_DM=y
+CONFIG_CMD_GPIO=y
+CONFIG_CMD_I2C=y
+CONFIG_CMD_MMC=y
+CONFIG_CMD_POWEROFF=y
+CONFIG_CMD_SPI=y
+CONFIG_CMD_USB=y
+CONFIG_CMD_USB_SDP=y
+CONFIG_CMD_DHCP=y
+CONFIG_CMD_MII=y
+CONFIG_CMD_PING=y
+CONFIG_CMD_SNTP=y
+CONFIG_CMD_DNS=y
+CONFIG_CMD_BMP=y
+CONFIG_CMD_BOOTCOUNT=y
+CONFIG_CMD_CACHE=y
+CONFIG_CMD_CLS=y
+CONFIG_CMD_TIME=y
+CONFIG_CMD_PMIC=y
+CONFIG_CMD_REGULATOR=y
+CONFIG_CMD_EXT2=y
+CONFIG_CMD_EXT4=y
+CONFIG_CMD_EXT4_WRITE=y
+CONFIG_CMD_FAT=y
+CONFIG_CMD_FS_GENERIC=y
+CONFIG_CMD_LOG=y
+# CONFIG_SPL_DOS_PARTITION is not set
+CONFIG_OF_CONTROL=y
+CONFIG_ENV_IS_IN_SPI_FLASH=y
+CONFIG_BOOTCOUNT_LIMIT=y
+CONFIG_DM_BOOTCOUNT=y
+CONFIG_DM_BOOTCOUNT_SPI_FLASH=y
+CONFIG_DM_PCA953X=y
+CONFIG_DM_I2C=y
+CONFIG_SYS_I2C_MXC=y
+CONFIG_I2C_MUX=y
+CONFIG_I2C_MUX_GPIO=y
+CONFIG_LED=y
+CONFIG_LED_GPIO=y
+CONFIG_DM_MMC=y
+CONFIG_FSL_USDHC=y
+CONFIG_DM_SPI_FLASH=y
+CONFIG_SF_DEFAULT_MODE=0
+CONFIG_SF_DEFAULT_SPEED=20000000
+CONFIG_SPI_FLASH_SST=y
+CONFIG_SPI_FLASH_WINBOND=y
+CONFIG_PHYLIB=y
+CONFIG_PHY_ATHEROS=y
+CONFIG_DM_ETH=y
+CONFIG_DM_MDIO=y
+CONFIG_DM_ETH_PHY=y
+CONFIG_FEC_MXC=y
+CONFIG_MII=y
+CONFIG_PINCTRL=y
+CONFIG_PINCTRL_IMX6=y
+CONFIG_DM_PMIC=y
+# CONFIG_SPL_PMIC_CHILDREN is not set
+CONFIG_DM_PMIC_PFUZE100=y
+CONFIG_DM_REGULATOR=y
+CONFIG_DM_REGULATOR_FIXED=y
+CONFIG_DM_REGULATOR_GPIO=y
+CONFIG_DM_PWM=y
+CONFIG_PWM_IMX=y
+CONFIG_DM_RTC=y
+CONFIG_RTC_M41T62=y
+CONFIG_DM_SERIAL=y
+CONFIG_MXC_UART=y
+CONFIG_SPI=y
+CONFIG_DM_SPI=y
+CONFIG_MXC_SPI=y
+CONFIG_SYSRESET=y
+CONFIG_SYSRESET_CMD_POWEROFF=y
+CONFIG_POWEROFF_GPIO=y
+CONFIG_SYSRESET_WATCHDOG=y
+CONFIG_IMX_THERMAL=y
+CONFIG_USB=y
+CONFIG_DM_USB=y
+CONFIG_USB_STORAGE=y
+CONFIG_USB_KEYBOARD=y
+CONFIG_USB_GADGET=y
+CONFIG_USB_GADGET_MANUFACTURER="Congatec"
+CONFIG_USB_GADGET_VENDOR_NUM=0x0525
+CONFIG_USB_GADGET_PRODUCT_NUM=0xa4a5
+CONFIG_CI_UDC=y
+CONFIG_USB_GADGET_DOWNLOAD=y
+CONFIG_DM_VIDEO=y
+CONFIG_VIDEO_IPUV3=y
+CONFIG_WATCHDOG_TIMEOUT_MSECS=30000
+CONFIG_IMX_WATCHDOG=y
+CONFIG_BCH=y
CONFIG_FIT=y
CONFIG_SUPPORT_RAW_INITRD=y
CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/freescale/mx53loco/imximage.cfg"
+CONFIG_SHOW_BOOT_PROGRESS=y
CONFIG_AUTOBOOT_KEYED=y
CONFIG_AUTOBOOT_STOP_STR="."
CONFIG_SILENT_CONSOLE=y
--- /dev/null
+CONFIG_ARM=y
+CONFIG_ARCH_IMX8M=y
+CONFIG_SYS_TEXT_BASE=0x40200000
+CONFIG_SPL_GPIO_SUPPORT=y
+CONFIG_SPL_LIBCOMMON_SUPPORT=y
+CONFIG_SPL_LIBGENERIC_SUPPORT=y
+CONFIG_SYS_MALLOC_F_LEN=0x10000
+CONFIG_ENV_SIZE=0x10000
+CONFIG_ENV_OFFSET=0x3C0000
+CONFIG_SYS_I2C_MXC_I2C1=y
+CONFIG_SYS_I2C_MXC_I2C2=y
+CONFIG_SYS_I2C_MXC_I2C3=y
+CONFIG_DM_GPIO=y
+CONFIG_SPL_TEXT_BASE=0x7E1000
+CONFIG_TARGET_PHYCORE_IMX8MM=y
+CONFIG_SPL_MMC_SUPPORT=y
+CONFIG_SPL_SERIAL_SUPPORT=y
+CONFIG_SPL_DRIVERS_MISC_SUPPORT=y
+CONFIG_SPL=y
+CONFIG_ENV_OFFSET_REDUND=0x3E0000
+CONFIG_DEFAULT_DEVICE_TREE="phycore-imx8mm"
+CONFIG_FIT=y
+CONFIG_FIT_EXTERNAL_OFFSET=0x3000
+CONFIG_SPL_LOAD_FIT=y
+CONFIG_SPL_FIT_GENERATOR="arch/arm/mach-imx/mkimage_fit_atf.sh"
+CONFIG_OF_SYSTEM_SETUP=y
+CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=arch/arm/mach-imx/imx8m/imximage-8mm-lpddr4.cfg"
+CONFIG_DEFAULT_FDT_FILE="oftree"
+CONFIG_BOARD_LATE_INIT=y
+CONFIG_SPL_BOARD_INIT=y
+CONFIG_SPL_SEPARATE_BSS=y
+CONFIG_SPL_I2C_SUPPORT=y
+CONFIG_SPL_POWER_SUPPORT=y
+CONFIG_SPL_WATCHDOG_SUPPORT=y
+CONFIG_HUSH_PARSER=y
+CONFIG_SYS_PROMPT="u-boot=> "
+# CONFIG_CMD_EXPORTENV is not set
+# CONFIG_CMD_IMPORTENV is not set
+# CONFIG_CMD_CRC32 is not set
+CONFIG_CMD_EEPROM=y
+CONFIG_CMD_FUSE=y
+CONFIG_CMD_GPIO=y
+CONFIG_CMD_I2C=y
+CONFIG_CMD_MMC=y
+CONFIG_CMD_DHCP=y
+CONFIG_CMD_MII=y
+CONFIG_CMD_PING=y
+CONFIG_CMD_CACHE=y
+CONFIG_CMD_REGULATOR=y
+CONFIG_CMD_EXT2=y
+CONFIG_CMD_EXT4=y
+CONFIG_CMD_EXT4_WRITE=y
+CONFIG_CMD_FAT=y
+CONFIG_OF_CONTROL=y
+CONFIG_SPL_OF_CONTROL=y
+CONFIG_ENV_OVERWRITE=y
+CONFIG_ENV_IS_IN_MMC=y
+CONFIG_SYS_REDUNDAND_ENVIRONMENT=y
+CONFIG_SYS_RELOC_GD_ENV_ADDR=y
+CONFIG_SYS_MMC_ENV_DEV=2
+CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG=y
+CONFIG_SPL_DM=y
+CONFIG_SPL_CLK_COMPOSITE_CCF=y
+CONFIG_CLK_COMPOSITE_CCF=y
+CONFIG_SPL_CLK_IMX8MM=y
+CONFIG_CLK_IMX8MM=y
+CONFIG_MXC_GPIO=y
+CONFIG_DM_I2C=y
+CONFIG_SYS_I2C_MXC=y
+CONFIG_MISC=y
+CONFIG_I2C_EEPROM=y
+CONFIG_SYS_I2C_EEPROM_ADDR=0x51
+CONFIG_SYS_EEPROM_SIZE=4096
+CONFIG_SYS_EEPROM_PAGE_WRITE_BITS=5
+CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS=5
+CONFIG_SYS_I2C_EEPROM_ADDR_LEN=2
+CONFIG_SYS_I2C_EEPROM_ADDR_OVERFLOW=0x0
+CONFIG_DM_MMC=y
+CONFIG_SUPPORT_EMMC_BOOT=y
+CONFIG_MMC_IO_VOLTAGE=y
+CONFIG_MMC_UHS_SUPPORT=y
+CONFIG_MMC_HS400_ES_SUPPORT=y
+CONFIG_MMC_HS400_SUPPORT=y
+CONFIG_FSL_ESDHC_IMX=y
+CONFIG_PHYLIB=y
+CONFIG_PHY_TI_DP83867=y
+CONFIG_DM_ETH=y
+CONFIG_PHY_GIGE=y
+CONFIG_FEC_MXC=y
+CONFIG_MII=y
+CONFIG_PINCTRL=y
+CONFIG_SPL_PINCTRL=y
+CONFIG_PINCTRL_IMX8M=y
+CONFIG_DM_REGULATOR=y
+CONFIG_DM_REGULATOR_FIXED=y
+CONFIG_DM_REGULATOR_GPIO=y
+CONFIG_MXC_UART=y
+CONFIG_SYSRESET=y
+CONFIG_SPL_SYSRESET=y
+CONFIG_SYSRESET_PSCI=y
+CONFIG_SYSRESET_WATCHDOG=y
+CONFIG_DM_THERMAL=y
+CONFIG_IMX_WATCHDOG=y
# CONFIG_BOOTM_NETBSD is not set
CONFIG_CMD_ASKENV=y
# CONFIG_CMD_EXPORTENV is not set
-# CONFIG_CMD_IMPORTENV is not set
# CONFIG_CMD_CRC32 is not set
CONFIG_CMD_MEMTEST=y
CONFIG_SYS_MEMTEST_START=0x40000000
CONFIG_SYSRESET_WATCHDOG=y
CONFIG_DM_THERMAL=y
CONFIG_IMX_WATCHDOG=y
+CONFIG_OF_LIBFDT_OVERLAY=y
--- /dev/null
+.. SPDX-License-Identifier: GPL-2.0+
+
+imx8mm_evk
+==========
+
+U-Boot for the NXP i.MX8MM EVK board
+
+Quick Start
+-----------
+
+- Build the ARM Trusted firmware binary
+- Get ddr firmware
+- Build U-Boot
+- Boot
+
+Get and Build the ARM Trusted firmware
+--------------------------------------
+
+Note: builddir is U-Boot build directory (source directory for in-tree builds)
+Get ATF from: https://source.codeaurora.org/external/imx/imx-atf
+branch: imx_4.19.35_1.0.0
+
+.. code-block:: bash
+
+ $ make PLAT=imx8mm bl31
+ $ cp build/imx8mm/release/bl31.bin $(builddir)
+
+Get the ddr firmware
+--------------------
+
+.. code-block:: bash
+
+ $ wget https://www.nxp.com/lgfiles/NMG/MAD/YOCTO/firmware-imx-8.0.bin
+ $ chmod +x firmware-imx-8.0.bin
+ $ ./firmware-imx-8.0
+ $ cp firmware-imx-8.0/firmware/ddr/synopsys/lpddr4*.bin $(builddir)
+
+Build U-Boot
+------------
+
+.. code-block:: bash
+
+ $ export CROSS_COMPILE=aarch64-poky-linux-
+ $ make imx8mm_evk_defconfig
+ $ export ATF_LOAD_ADDR=0x920000
+ $ make flash.bin
+
+Burn the flash.bin to MicroSD card offset 33KB:
+
+.. code-block:: bash
+
+ $sudo dd if=flash.bin of=/dev/sd[x] bs=1024 seek=33 conv=notrunc
+
+Boot
+----
+Set Boot switch to SD boot
--- /dev/null
+.. SPDX-License-Identifier: GPL-2.0+
+
+imx8mn_evk
+==========
+
+U-Boot for the NXP i.MX8MN EVK board
+
+Quick Start
+-----------
+
+- Build the ARM Trusted firmware binary
+- Get firmware-imx package
+- Build U-Boot
+- Boot
+
+Get and Build the ARM Trusted firmware
+--------------------------------------
+
+Note: srctree is U-Boot source directory
+Get ATF from: https://source.codeaurora.org/external/imx/imx-atf
+branch: imx_4.19.35_1.1.0
+
+.. code-block:: bash
+
+ $ make PLAT=imx8mn bl31
+ $ cp build/imx8mn/release/bl31.bin $(srctree)
+
+Get the ddr firmware
+--------------------
+
+.. code-block:: bash
+
+ $ wget https://www.nxp.com/lgfiles/NMG/MAD/YOCTO/firmware-imx-8.5.bin
+ $ chmod +x firmware-imx-8.5.bin
+ $ ./firmware-imx-8.5
+ $ cp firmware-imx-8.5/firmware/ddr/synopsys/ddr4*.bin $(srctree)
+
+Build U-Boot
+------------
+
+.. code-block:: bash
+
+ $ export CROSS_COMPILE=aarch64-poky-linux-
+ $ make imx8mn_ddr4_evk_defconfig
+ $ export ATF_LOAD_ADDR=0x960000
+ $ make flash.bin
+
+Burn the flash.bin to MicroSD card offset 32KB:
+
+.. code-block:: bash
+
+ $sudo dd if=flash.bin of=/dev/sd[x] bs=1024 seek=32 conv=notrunc
+
+Boot
+----
+
+Set Boot switch to SD boot
--- /dev/null
+.. SPDX-License-Identifier: GPL-2.0+
+
+imx8mp_evk
+==========
+
+U-Boot for the NXP i.MX8MP EVK board
+
+Quick Start
+-----------
+
+- Build the ARM Trusted firmware binary
+- Get the firmware-imx package
+- Build U-Boot
+- Boot
+
+Get and Build the ARM Trusted firmware
+--------------------------------------
+
+Note: $(srctree) is the U-Boot source directory
+Get ATF from: https://source.codeaurora.org/external/imx/imx-atf
+branch: imx_5.4.3_2.0.0
+
+.. code-block:: bash
+
+ $ make PLAT=imx8mp bl31
+ $ sudo cp build/imx8mp/release/bl31.bin $(srctree)
+
+Get the ddr firmware
+--------------------
+
+.. code-block:: bash
+
+ $ wget https://www.nxp.com/lgfiles/NMG/MAD/YOCTO/firmware-imx-8.7.bin
+ $ chmod +x firmware-imx-8.7.bin
+ $ ./firmware-imx-8.7
+ $ sudo cp firmware-imx-8.7/firmware/ddr/synopsys/lpddr4_pmu_train_1d_dmem_201904.bin $(srctree)/lpddr4_pmu_train_1d_dmem.bin
+ $ sudo cp firmware-imx-8.7/firmware/ddr/synopsys/lpddr4_pmu_train_1d_imem_201904.bin $(srctree)/lpddr4_pmu_train_1d_imem.bin
+ $ sudo cp firmware-imx-8.7/firmware/ddr/synopsys/lpddr4_pmu_train_2d_dmem_201904.bin $(srctree)/lpddr4_pmu_train_2d_dmem.bin
+ $ sudo cp firmware-imx-8.7/firmware/ddr/synopsys/lpddr4_pmu_train_2d_imem_201904.bin $(srctree)/lpddr4_pmu_train_2d_imem.bin
+
+Build U-Boot
+------------
+
+.. code-block:: bash
+
+ $ export CROSS_COMPILE=aarch64-poky-linux-
+ $ make imx8mp_evk_defconfig
+ $ export ATF_LOAD_ADDR=0x960000
+ $ make flash.bin
+
+Burn the flash.bin to the MicroSD card at offset 32KB:
+
+.. code-block:: bash
+
+ $sudo dd if=flash.bin of=/dev/sd[x] bs=1K seek=32 conv=notrunc; sync
+
+Boot
+----
+
+Set Boot switch to SD boot
+Use /dev/ttyUSB2 for U-Boot console
--- /dev/null
+.. SPDX-License-Identifier: GPL-2.0+
+
+imx8mq_evk
+==========
+
+U-Boot for the NXP i.MX8MQ EVK board
+
+Quick Start
+-----------
+
+- Build the ARM Trusted firmware binary
+- Get ddr and hdmi fimware
+- Build U-Boot
+- Boot
+
+Get and Build the ARM Trusted firmware
+--------------------------------------
+
+Note: srctree is U-Boot source directory
+Get ATF from: https://source.codeaurora.org/external/imx/imx-atf
+branch: imx_4.19.35_1.0.0
+
+.. code-block:: bash
+
+ $ make PLAT=imx8mq bl31
+ $ cp build/imx8mq/release/bl31.bin $(builddir)
+
+Get the ddr and hdmi firmware
+-----------------------------
+
+.. code-block:: bash
+
+ $ wget https://www.nxp.com/lgfiles/NMG/MAD/YOCTO/firmware-imx-7.9.bin
+ $ chmod +x firmware-imx-7.9.bin
+ $ ./firmware-imx-7.9.bin
+ $ cp firmware-imx-7.9/firmware/hdmi/cadence/signed_hdmi_imx8m.bin $(builddir)
+ $ cp firmware-imx-7.9/firmware/ddr/synopsys/lpddr4*.bin $(builddir)
+
+Build U-Boot
+------------
+
+.. code-block:: bash
+
+ $ export CROSS_COMPILE=aarch64-poky-linux-
+ $ make imx8mq_evk_defconfig
+ $ make flash.bin
+
+Burn the flash.bin to MicroSD card offset 33KB:
+
+.. code-block:: bash
+
+ $sudo dd if=flash.bin of=/dev/sd[x] bs=1024 seek=33 conv=notrunc
+
+Boot
+----
+Set Boot switch SW801: 1100 and Bmode: 10 to boot from Micro SD.
--- /dev/null
+.. SPDX-License-Identifier: GPL-2.0+
+
+imx8qxp_mek
+===========
+
+U-Boot for the NXP i.MX8QXP EVK board
+
+Quick Start
+-----------
+
+- Build the ARM Trusted firmware binary
+- Get scfw_tcm.bin and ahab-container.img
+- Build U-Boot
+- Flash the binary into the SD card
+- Boot
+
+Get and Build the ARM Trusted firmware
+--------------------------------------
+
+.. code-block:: bash
+
+ $ git clone https://source.codeaurora.org/external/imx/imx-atf
+ $ cd imx-atf/
+ $ git checkout origin/imx_4.19.35_1.1.0 -b imx_4.19.35_1.1.0
+ $ make PLAT=imx8qx bl31
+
+Get scfw_tcm.bin and ahab-container.img
+---------------------------------------
+
+.. code-block:: bash
+
+ $ wget https://www.nxp.com/lgfiles/NMG/MAD/YOCTO/imx-sc-firmware-1.2.7.1.bin
+ $ chmod +x imx-sc-firmware-1.2.7.1.bin
+ $ ./imx-sc-firmware-1.2.7.1.bin
+ $ wget https://www.nxp.com/lgfiles/NMG/MAD/YOCTO/imx-seco-2.3.1.bin
+ $ chmod +x imx-seco-2.3.1.bin
+ $ ./imx-seco-2.3.1.bin
+
+Copy the following binaries to U-Boot folder:
+
+.. code-block:: bash
+
+ $ cp imx-atf/build/imx8qx/release/bl31.bin .
+ $ cp imx-seco-2.3.1/firmware/seco/mx8qx-ahab-container.img ./ahab-container.img
+ $ cp imx-sc-firmware-1.2.7.1/mx8qx-mek-scfw-tcm.bin .
+
+Build U-Boot
+------------
+
+.. code-block:: bash
+
+ $ make imx8qxp_mek_defconfig
+ $ make flash.bin
+
+Flash the binary into the SD card
+---------------------------------
+
+Burn the flash.bin binary to SD card offset 32KB:
+
+.. code-block:: bash
+
+ $ sudo dd if=flash.bin of=/dev/sd[x] bs=1024 seek=32 conv=notrunc
+
+Boot
+----
+Set Boot switch SW2: 1100.
--- /dev/null
+.. SPDX-License-Identifier: GPL-2.0+
+
+imxrt1020-evk
+=============
+
+How to use U-Boot on NXP i.MXRT1020 EVK
+---------------------------------------
+
+- Build U-Boot for i.MXRT1020 EVK:
+
+.. code-block:: bash
+
+ $ make mrproper
+ $ make imxrt1020-evk_defconfig
+ $ make
+
+This will generate the SPL image called SPL and the u-boot.img.
+
+- Flash the SPL image into the micro SD card:
+
+.. code-block:: bash
+
+ $sudo dd if=SPL of=/dev/sdX bs=1k seek=1 conv=notrunc; sync
+
+- Flash the u-boot.img image into the micro SD card:
+
+.. code-block:: bash
+
+ $sudo dd if=u-boot.img of=/dev/sdX bs=1k seek=128 conv=notrunc; sync
+
+- Jumper settings::
+
+ SW8: 0 1 1 0
+
+where 0 means bottom position and 1 means top position (from the
+switch label numbers reference).
+
+- Connect the USB cable between the EVK and the PC for the console.
+ The USB console connector is the one close the ethernet connector
+
+- Insert the micro SD card in the board, power it up and U-Boot messages should come up.
--- /dev/null
+.. SPDX-License-Identifier: GPL-2.0+
+
+imxrt1050-evk
+=============
+
+How to use U-Boot on NXP i.MXRT1050 EVK
+---------------------------------------
+
+- Build U-Boot for i.MXRT1050 EVK:
+
+.. code-block:: bash
+
+ $ make mrproper
+ $ make imxrt1050-evk_defconfig
+ $ make
+
+This will generate the SPL image called SPL and the u-boot.img.
+
+- Flash the SPL image into the micro SD card:
+
+.. code-block:: bash
+
+ $sudo dd if=SPL of=/dev/sdX bs=1k seek=1 conv=notrunc; sync
+
+- Flash the u-boot.img image into the micro SD card:
+
+.. code-block:: bash
+
+ $sudo dd if=u-boot.img of=/dev/sdX bs=1k seek=128 conv=notrunc; sync
+
+- Jumper settings::
+
+ SW7: 1 0 1 0
+
+where 0 means bottom position and 1 means top position (from the
+switch label numbers reference).
+
+- Connect the USB cable between the EVK and the PC for the console.
+ The USB console connector is the one close the ethernet connector
+
+- Insert the micro SD card in the board, power it up and U-Boot messages should come up.
:maxdepth: 2
b4860qds
+ imx8mm_evk
+ imx8mn_evk
+ imx8mp_evk
+ imx8mq_evk
+ imx8qxp_mek
+ imxrt1020-evk
+ imxrt1050-evk
+ mx6sabreauto
+ mx6sabresd
+ mx6ul_14x14_evk
+ mx6ullevk
--- /dev/null
+.. SPDX-License-Identifier: GPL-2.0+
+
+mx6sabreauto
+============
+
+How to use and build U-Boot on mx6sabreauto
+-------------------------------------------
+
+mx6sabreauto_defconfig target supports mx6q/mx6dl/mx6qp sabreauto variants.
+
+In order to build it:
+
+.. code-block:: bash
+
+ $ make mx6sabreauto_defconfig
+ $ make
+
+This will generate the SPL and u-boot-dtb.img binaries.
+
+- Flash the SPL binary into the SD card:
+
+.. code-block:: bash
+
+ $ sudo dd if=SPL of=/dev/sdX bs=1K seek=1 conv=notrunc && sync
+
+- Flash the u-boot-dtb.img binary into the SD card:
+
+.. code-block:: bash
+
+ $ sudo dd if=u-boot-dtb.img of=/dev/sdX bs=1K seek=69 conv=notrunc && sync
+
+Booting via Falcon mode
+-----------------------
+
+Write in mx6sabreauto_defconfig the following define below:
+
+CONFIG_SPL_OS_BOOT=y
+
+In order to build it:
+
+.. code-block:: bash
+
+ $ make mx6sabreauto_defconfig
+ $ make
+
+This will generate the SPL image called SPL and the u-boot-dtb.img.
+
+- Flash the SPL image into the SD card:
+
+.. code-block:: bash
+
+ $ sudo dd if=SPL of=/dev/sdb bs=1K seek=1 conv=notrunc && sync
+
+- Flash the u-boot-dtb.img image into the SD card:
+
+.. code-block:: bash
+
+ $ sudo dd if=u-boot-dtb.img of=/dev/sdb bs=1K seek=69 conv=notrunc && sync
+
+Create a FAT16 boot partition to store uImage and the dtb file, then copy the files there:
+
+.. code-block:: bash
+
+ $ sudo cp uImage /media/boot
+ $ sudo cp imx6dl-sabreauto.dtb /media/boot
+
+Create a partition for root file system and extract it there:
+
+.. code-block:: bash
+
+ $ sudo tar xvf rootfs.tar.gz -C /media/root
+
+The SD card must have enough space for raw "args" and "kernel".
+To configure Falcon mode for the first time, on U-Boot do the following commands:
+
+- Load dtb file from boot partition::
+
+ # load mmc 0:1 ${fdt_addr} imx6dl-sabreauto.dtb
+
+- Load kernel image from boot partition::
+
+ # load mmc 0:1 ${loadaddr} uImage
+
+- Write kernel at 2MB offset::
+
+ # mmc write ${loadaddr} 0x1000 0x4000
+
+- Setup kernel bootargs::
+
+ # setenv bootargs "console=ttymxc3,115200 root=/dev/mmcblk0p1 rootfstype=ext4 rootwait quiet rw"
+
+- Prepare args::
+
+ # spl export fdt ${loadaddr} - ${fdt_addr}
+
+- Write args 1MB data (0x800 sectors) to 1MB offset (0x800 sectors)::
+
+ # mmc write 18000000 0x800 0x800
+
+- Restart the board and then SPL binary will launch the kernel directly.
--- /dev/null
+.. SPDX-License-Identifier: GPL-2.0+
+
+mx6sabresd
+==========
+
+How to use and build U-Boot on mx6sabresd
+-----------------------------------------
+
+The following methods can be used for booting mx6sabresd boards:
+
+1. Booting from SD card
+
+2. Booting from eMMC
+
+3. Booting via Falcon mode (SPL launches the kernel directly)
+
+
+1. Booting from SD card via SPL
+-------------------------------
+
+mx6sabresd_defconfig target supports mx6q/mx6dl/mx6qp sabresd variants.
+
+In order to build it:
+
+.. code-block:: bash
+
+ $ make mx6sabresd_defconfig
+ $ make
+
+This will generate the SPL and u-boot-dtb.img binaries.
+
+- Flash the SPL binary into the SD card:
+
+.. code-block:: bash
+
+ $ sudo dd if=SPL of=/dev/sdX bs=1K seek=1 conv=notrunc && sync
+
+- Flash the u-boot-dtb.img binary into the SD card:
+
+.. code-block:: bash
+
+ $ sudo dd if=u-boot-dtb.img of=/dev/sdX bs=1K seek=69 conv=notrunc && sync
+
+2. Booting from eMMC
+--------------------
+
+.. code-block:: bash
+
+ $ make mx6sabresd_defconfig
+ $ make
+
+This will generate the SPL and u-boot-dtb.img binaries.
+
+- Boot first from SD card as shown in the previous section
+
+In U-boot change the eMMC partition config::
+
+ => mmc partconf 2 1 0 0
+
+Mount the eMMC in the host PC::
+
+ => ums 0 mmc 2
+
+- Flash SPL and u-boot-dtb.img binaries into the eMMC:
+
+.. code-block:: bash
+
+ $ sudo dd if=SPL of=/dev/sdX bs=1K seek=1 conv=notrunc && sync
+ $ sudo dd if=u-boot-dtb.img of=/dev/sdX bs=1K seek=69 conv=notrunc && sync
+
+Set SW6 to eMMC 8-bit boot: 11010110
+
+3. Booting via Falcon mode
+--------------------------
+
+.. code-block:: bash
+
+ $ make mx6sabresd_defconfig
+ $ make
+
+This will generate the SPL image called SPL and the u-boot-dtb.img.
+
+- Flash the SPL image into the SD card
+
+.. code-block:: bash
+
+ $ sudo dd if=SPL of=/dev/sdX bs=1K seek=1 oflag=sync status=none conv=notrunc && sync
+
+- Flash the u-boot-dtb.img image into the SD card
+
+.. code-block:: bash
+
+ $ sudo dd if=u-boot-dtb.img of=/dev/sdX bs=1K seek=69 oflag=sync status=none conv=notrunc && sync
+
+Create a partition for root file system and extract it there
+
+.. code-block:: bash
+
+ $ sudo tar xvf rootfs.tar.gz -C /media/root
+
+The SD card must have enough space for raw "args" and "kernel".
+To configure Falcon mode for the first time, on U-Boot do the following commands:
+
+- Setup the IP server::
+
+ # setenv serverip <server_ip_address>
+
+- Download dtb file::
+
+ # dhcp ${fdt_addr} imx6q-sabresd.dtb
+
+- Download kernel image::
+
+ # dhcp ${loadaddr} uImage
+
+- Write kernel at 2MB offset::
+
+ # mmc write ${loadaddr} 0x1000 0x4000
+
+- Setup kernel bootargs::
+
+ # setenv bootargs "console=ttymxc0,115200 root=/dev/mmcblk1p1 rootfstype=ext4 rootwait quiet rw"
+
+- Prepare args::
+
+ # spl export fdt ${loadaddr} - ${fdt_addr}
+
+- Write args 1MB data (0x800 sectors) to 1MB offset (0x800 sectors)::
+
+ # mmc write 18000000 0x800 0x800
+
+- Press KEY_VOL_UP key, power up the board and then SPL binary will launch the kernel directly.
+.. SPDX-License-Identifier: GPL-2.0+
+
+mx6ul_14x14_evk
+===============
+
How to use U-Boot on Freescale MX6UL 14x14 EVK
-----------------------------------------------
- Build U-Boot for MX6UL 14x14 EVK:
-$ make mrproper
-$ make mx6ul_14x14_evk_defconfig
-$ make
+.. code-block:: bash
+
+ $ make mrproper
+ $ make mx6ul_14x14_evk_defconfig
+ $ make
This will generate the SPL image called SPL and the u-boot.img.
- Flash the SPL image into the micro SD card:
-sudo dd if=SPL of=/dev/mmcblk0 bs=1k seek=1; sync
+.. code-block:: bash
+
+ sudo dd if=SPL of=/dev/mmcblk0 bs=1k seek=1 conv=notrunc; sync
- Flash the u-boot.img image into the micro SD card:
-sudo dd if=u-boot.img of=/dev/mmcblk0 bs=1k seek=69; sync
+.. code-block:: bash
-- Jumper settings:
+ sudo dd if=u-boot.img of=/dev/mmcblk0 bs=1k seek=69 conv=notrunc; sync
-SW601: 0 0 1 0
-Sw602: 1 0
+- Jumper settings::
+
+ SW601: 0 0 1 0
+ Sw602: 1 0
where 0 means bottom position and 1 means top position (from the
switch label numbers reference).
- Connect the USB cable between the EVK and the PC for the console.
-(The USB console connector is the one close the push buttons)
+ The USB console connector is the one close the push buttons
-- Insert the micro SD card in the board, power it up and U-Boot messages should
-come up.
+- Insert the micro SD card in the board, power it up and U-Boot messages should come up.
2. Booting via Serial Download Protocol (SDP)
---------------------------------------------
The mx6ulevk board can boot from USB OTG port using the SDP, target will
enter in SDP mode in case an SD Card is not connect or boot switches are
-set as below:
+set as below::
-Sw602: 0 1
-SW601: x x x x
+ Sw602: 0 1
+ SW601: x x x x
The following tools can be used to boot via SDP, for both tools you must
connect an USB cable in USB OTG port.
The following script should be created to boot SPL + u-boot-dtb.img binaries:
- $ cat uuu_script
- uuu_version 1.1.4
+.. code-block:: bash
+
+ $ cat uuu_script
+ uuu_version 1.1.4
- SDP: boot -f SPL
- SDPU: write -f u-boot-dtb.img -addr 0x877fffc0
- SDPU: jump -addr 0x877fffc0
- SDPU: done
+ SDP: boot -f SPL
+ SDPU: write -f u-boot-dtb.img -addr 0x877fffc0
+ SDPU: jump -addr 0x877fffc0
+ SDPU: done
Please note that the address above is calculated based on SYS_TEXT_BASE address:
Power on the target and run the following command from U-Boot root directory:
- $ sudo ./uuu uuu_script
+.. code-block:: bash
+
+ $ sudo ./uuu uuu_script
- Method 2: imx usb loader tool (imx_usb):
Build the source code and run the following commands from U-Boot root
directory:
- $ sudo ./imx_usb SPL
- $ sudo ./imx_usb u-boot-dtb.img
+.. code-block:: bash
+
+ $ sudo ./imx_usb SPL
+ $ sudo ./imx_usb u-boot-dtb.img
+.. SPDX-License-Identifier: GPL-2.0+
+
+mx6ullevk
+=========
+
How to use U-Boot on Freescale MX6ULL 14x14 EVK
-----------------------------------------------
+-----------------------------------------------
- First make sure you have installed the dtc package (device tree compiler):
-$ sudo apt-get install device-tree-compiler
+.. code-block:: bash
+
+ $ sudo apt-get install device-tree-compiler
- Build U-Boot for MX6ULL 14x14 EVK:
-$ make mrproper
-$ make mx6ull_14x14_evk_defconfig
-$ make
+.. code-block:: bash
+
+ $ make mrproper
+ $ make mx6ull_14x14_evk_defconfig
+ $ make
This generates the u-boot-dtb.imx image in the current directory.
- Flash the u-boot-dtb.imx image into the micro SD card:
-$ sudo dd if=u-boot-dtb.imx of=/dev/sdb bs=1K seek=1 && sync
+.. code-block:: bash
+
+ $ sudo dd if=u-boot-dtb.imx of=/dev/sdb bs=1K seek=1 conv=notrunc && sync
-- Jumper settings:
+- Jumper settings::
-SW601: 0 0 1 0
-Sw602: 1 0
+ SW601: 0 0 1 0
+ Sw602: 1 0
Where 0 means bottom position and 1 means top position (from the switch label
numbers reference).
pointing to the underlying i2c eeprom device) and an optional 'offset'
property are supported.
+config DM_BOOTCOUNT_SPI_FLASH
+ bool "Support SPI flash devices as a backing store for bootcount"
+ depends on DM_SPI_FLASH
+ help
+ Enabled reading/writing the bootcount in a DM SPI flash device.
+ The wrapper device is to be specified with the compatible string
+ 'u-boot,bootcount-spi-flash' and the 'spi-flash'-property (a phandle
+ pointing to the underlying SPI flash device) and an optional 'offset'
+ property are supported.
+
config BOOTCOUNT_MEM
bool "Support memory based bootcounter"
help
obj-$(CONFIG_DM_BOOTCOUNT) += bootcount-uclass.o
obj-$(CONFIG_DM_BOOTCOUNT_RTC) += rtc.o
obj-$(CONFIG_DM_BOOTCOUNT_I2C_EEPROM) += i2c-eeprom.o
+obj-$(CONFIG_DM_BOOTCOUNT_SPI_FLASH) += spi-flash.o
--- /dev/null
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * (C) Copyright 2019 Collabora
+ * (C) Copyright 2019 GE
+ */
+
+#include <common.h>
+#include <bootcount.h>
+#include <dm.h>
+#include <spi_flash.h>
+
+static const u8 bootcount_magic = 0xbc;
+
+struct bootcount_spi_flash_priv {
+ struct udevice *spi_flash;
+ u32 offset;
+};
+
+static int bootcount_spi_flash_update(struct udevice *dev, u32 offset, u32 len, const void *buf)
+{
+ struct spi_flash *flash = dev_get_uclass_priv(dev);
+ u32 sector_size = flash->sector_size;
+ u32 sector_offset = offset % sector_size;
+ u32 sector = offset - sector_offset;
+ int err = 0;
+
+ /* code only supports updating a single sector */
+ if (sector_offset + len > sector_size)
+ return -ENOSYS;
+
+ u8 *buffer = malloc(sector_size);
+ if (!buffer)
+ return -ENOMEM;
+
+ err = spi_flash_read_dm(dev, sector, sector_size, buffer);
+ if (err < 0)
+ goto out;
+
+ memcpy(buffer + sector_offset, buf, len);
+
+ err = spi_flash_erase_dm(dev, sector, sector_size);
+ if (err < 0)
+ goto out;
+
+ err = spi_flash_write_dm(dev, sector, sector_size, buffer);
+ if (err < 0)
+ goto out;
+
+out:
+ free(buffer);
+ return err;
+}
+
+static int bootcount_spi_flash_set(struct udevice *dev, const u32 a)
+{
+ struct bootcount_spi_flash_priv *priv = dev_get_priv(dev);
+ const u16 val = bootcount_magic << 8 | (a & 0xff);
+
+ if (bootcount_spi_flash_update(priv->spi_flash, priv->offset, 2, &val) < 0) {
+ debug("%s: write failed\n", __func__);
+ return -EIO;
+ }
+
+ return 0;
+}
+
+static int bootcount_spi_flash_get(struct udevice *dev, u32 *a)
+{
+ struct bootcount_spi_flash_priv *priv = dev_get_priv(dev);
+ u16 val;
+
+ if (spi_flash_read_dm(priv->spi_flash, priv->offset, 2, &val) < 0) {
+ debug("%s: read failed\n", __func__);
+ return -EIO;
+ }
+
+ if (val >> 8 == bootcount_magic) {
+ *a = val & 0xff;
+ return 0;
+ }
+
+ debug("%s: bootcount magic does not match on %04x\n", __func__, val);
+ return -EIO;
+}
+
+static int bootcount_spi_flash_probe(struct udevice *dev)
+{
+ struct ofnode_phandle_args phandle_args;
+ struct bootcount_spi_flash_priv *priv = dev_get_priv(dev);
+ struct udevice *spi_flash;
+
+ if (dev_read_phandle_with_args(dev, "spi-flash", NULL, 0, 0, &phandle_args)) {
+ debug("%s: spi-flash backing device not specified\n", dev->name);
+ return -ENOENT;
+ }
+
+ if (uclass_get_device_by_ofnode(UCLASS_SPI_FLASH, phandle_args.node, &spi_flash)) {
+ debug("%s: could not get backing device\n", dev->name);
+ return -ENODEV;
+ }
+
+ priv->spi_flash = spi_flash;
+ priv->offset = dev_read_u32_default(dev, "offset", 0);
+
+ return 0;
+}
+
+static const struct bootcount_ops bootcount_spi_flash_ops = {
+ .get = bootcount_spi_flash_get,
+ .set = bootcount_spi_flash_set,
+};
+
+static const struct udevice_id bootcount_spi_flash_ids[] = {
+ { .compatible = "u-boot,bootcount-spi-flash" },
+ { }
+};
+
+U_BOOT_DRIVER(bootcount_spi_flash) = {
+ .name = "bootcount-spi-flash",
+ .id = UCLASS_BOOTCOUNT,
+ .priv_auto_alloc_size = sizeof(struct bootcount_spi_flash_priv),
+ .probe = bootcount_spi_flash_probe,
+ .of_match = bootcount_spi_flash_ids,
+ .ops = &bootcount_spi_flash_ops,
+};
#include <log.h>
#include <rtc.h>
#include <i2c.h>
+#include <linux/log2.h>
+#include <linux/delay.h>
#define M41T62_REG_SSEC 0
#define M41T62_REG_SEC 1
#define M41T62_ALMON_SQWE (1 << 6) /* SQWE: SQW Enable Bit */
#define M41T62_ALHOUR_HT (1 << 6) /* HT: Halt Update Bit */
#define M41T62_FLAGS_AF (1 << 6) /* AF: Alarm Flag Bit */
+#define M41T62_FLAGS_OF (1 << 2) /* OF: Oscillator Flag Bit */
#define M41T62_FLAGS_BATT_LOW (1 << 4) /* BL: Battery Low Bit */
+#define M41T62_WDAY_SQW_FREQ_MASK 0xf0
+#define M41T62_WDAY_SQW_FREQ_SHIFT 4
+
+#define M41T62_SQW_MAX_FREQ 32768
+
#define M41T62_FEATURE_HT (1 << 0)
#define M41T62_FEATURE_BL (1 << 1)
return 0;
}
-static int m41t62_rtc_reset(struct udevice *dev)
+static int m41t62_sqw_enable(struct udevice *dev, bool enable)
{
u8 val;
+ int ret;
+
+ ret = dm_i2c_read(dev, M41T62_REG_ALARM_MON, &val, sizeof(val));
+ if (ret)
+ return ret;
+
+ if (enable)
+ val |= M41T62_ALMON_SQWE;
+ else
+ val &= ~M41T62_ALMON_SQWE;
+
+ return dm_i2c_write(dev, M41T62_REG_ALARM_MON, &val, sizeof(val));
+}
+
+static int m41t62_sqw_set_rate(struct udevice *dev, unsigned int rate)
+{
+ u8 val, newval, sqwrateval;
+ int ret;
+
+ if (rate >= M41T62_SQW_MAX_FREQ)
+ sqwrateval = 1;
+ else if (rate >= M41T62_SQW_MAX_FREQ / 4)
+ sqwrateval = 2;
+ else if (rate)
+ sqwrateval = 15 - ilog2(rate);
+
+ ret = dm_i2c_read(dev, M41T62_REG_WDAY, &val, sizeof(val));
+ if (ret)
+ return ret;
+
+ newval = val;
+ newval &= ~M41T62_WDAY_SQW_FREQ_MASK;
+ newval |= (sqwrateval << M41T62_WDAY_SQW_FREQ_SHIFT);
+
+ /*
+ * Try to avoid writing unchanged values. Writing to this register
+ * will reset the internal counter pipeline and thus affect system
+ * time.
+ */
+ if (newval == val)
+ return 0;
+
+ return dm_i2c_write(dev, M41T62_REG_WDAY, &newval, sizeof(newval));
+}
+
+static int m41t62_rtc_restart_osc(struct udevice *dev)
+{
+ u8 val;
+ int ret;
+
+ /* 0. check if oscillator failure happened */
+ ret = dm_i2c_read(dev, M41T62_REG_FLAGS, &val, sizeof(val));
+ if (ret)
+ return ret;
+ if (!(val & M41T62_FLAGS_OF))
+ return 0;
+
+ ret = dm_i2c_read(dev, M41T62_REG_SEC, &val, sizeof(val));
+ if (ret)
+ return ret;
+
+ /* 1. Set stop bit */
+ val |= M41T62_SEC_ST;
+ ret = dm_i2c_write(dev, M41T62_REG_ALARM_HOUR, &val, sizeof(val));
+ if (ret)
+ return ret;
+
+ /* 2. Clear stop bit */
+ val &= ~M41T62_SEC_ST;
+ ret = dm_i2c_write(dev, M41T62_REG_ALARM_HOUR, &val, sizeof(val));
+ if (ret)
+ return ret;
+
+ /* 3. wait 4 seconds */
+ mdelay(4000);
+
+ ret = dm_i2c_read(dev, M41T62_REG_FLAGS, &val, sizeof(val));
+ if (ret)
+ return ret;
+
+ /* 4. clear M41T62_FLAGS_OF bit */
+ val &= ~M41T62_FLAGS_OF;
+ ret = dm_i2c_write(dev, M41T62_REG_FLAGS, &val, sizeof(val));
+ if (ret)
+ return ret;
+
+ return 0;
+}
+
+static int m41t62_rtc_clear_ht(struct udevice *dev)
+{
+ u8 val;
+ int ret;
/*
* M41T82: Make sure HT (Halt Update) bit is cleared.
* This bit is 0 in M41T62 so its save to clear it always.
*/
- int ret = dm_i2c_read(dev, M41T62_REG_ALARM_HOUR, &val, sizeof(val));
-
+ ret = dm_i2c_read(dev, M41T62_REG_ALARM_HOUR, &val, sizeof(val));
+ if (ret)
+ return ret;
val &= ~M41T80_ALHOUR_HT;
- ret |= dm_i2c_write(dev, M41T62_REG_ALARM_HOUR, &val, sizeof(val));
+ ret = dm_i2c_write(dev, M41T62_REG_ALARM_HOUR, &val, sizeof(val));
+ if (ret)
+ return ret;
+
+ return 0;
+}
+
+static int m41t62_rtc_reset(struct udevice *dev)
+{
+ int ret;
+
+ ret = m41t62_rtc_restart_osc(dev);
+ if (ret)
+ return ret;
+
+ ret = m41t62_rtc_clear_ht(dev);
+ if (ret)
+ return ret;
- return ret;
+ /*
+ * Some boards feed the square wave as clock input into
+ * the SoC. This enables a 32.768kHz square wave, which is
+ * also the hardware default after power-loss.
+ */
+ ret = m41t62_sqw_set_rate(dev, 32768);
+ if (ret)
+ return ret;
+ return m41t62_sqw_enable(dev, true);
}
/*
*/
static int m41t62_rtc_probe(struct udevice *dev)
{
- return m41t62_rtc_reset(dev);
+ return m41t62_rtc_clear_ht(dev);
}
static const struct rtc_ops m41t62_rtc_ops = {
endif
+config POWEROFF_GPIO
+ bool "Enable support for GPIO poweroff driver"
+ select DM_GPIO
+ help
+ Support for system poweroff using a GPIO pin. This can be used
+ for systems having a single GPIO to trigger a system poweroff.
+
config SYSRESET_GPIO
bool "Enable support for GPIO reset driver"
select DM_GPIO
obj-$(CONFIG_ARCH_ROCKCHIP) += sysreset_rockchip.o
obj-$(CONFIG_ARCH_STI) += sysreset_sti.o
obj-$(CONFIG_SANDBOX) += sysreset_sandbox.o
+obj-$(CONFIG_POWEROFF_GPIO) += poweroff_gpio.o
obj-$(CONFIG_SYSRESET_GPIO) += sysreset_gpio.o
obj-$(CONFIG_SYSRESET_MPC83XX) += sysreset_mpc83xx.o
obj-$(CONFIG_SYSRESET_MICROBLAZE) += sysreset_microblaze.o
--- /dev/null
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Toggles a GPIO pin to power down a device
+ *
+ * Created using the Linux driver as reference, which
+ * has been written by:
+ *
+ * Jamie Lentin <jm@lentin.co.uk>
+ * Andrew Lunn <andrew@lunn.ch>
+ *
+ * Copyright (C) 2012 Jamie Lentin
+ */
+
+#include <common.h>
+#include <dm.h>
+#include <errno.h>
+#include <log.h>
+#include <sysreset.h>
+
+#include <asm/gpio.h>
+#include <linux/delay.h>
+
+struct poweroff_gpio_info {
+ struct gpio_desc gpio;
+ u32 active_delay_ms;
+ u32 inactive_delay_ms;
+ u32 timeout_ms;
+};
+
+static int poweroff_gpio_request(struct udevice *dev, enum sysreset_t type)
+{
+ struct poweroff_gpio_info *priv = dev_get_priv(dev);
+ int r;
+
+ if (type != SYSRESET_POWER_OFF)
+ return -ENOSYS;
+
+ debug("GPIO poweroff\n");
+
+ /* drive it active, also inactive->active edge */
+ r = dm_gpio_set_value(&priv->gpio, 1);
+ if (r < 0)
+ return r;
+ mdelay(priv->active_delay_ms);
+
+ /* drive inactive, also active->inactive edge */
+ r = dm_gpio_set_value(&priv->gpio, 0);
+ if (r < 0)
+ return r;
+ mdelay(priv->inactive_delay_ms);
+
+ /* drive it active, also inactive->active edge */
+ r = dm_gpio_set_value(&priv->gpio, 1);
+ if (r < 0)
+ return r;
+
+ /* give it some time */
+ mdelay(priv->timeout_ms);
+
+ return -EINPROGRESS;
+}
+
+static int poweroff_gpio_probe(struct udevice *dev)
+{
+ struct poweroff_gpio_info *priv = dev_get_priv(dev);
+ int flags;
+
+ flags = dev_read_bool(dev, "input") ? GPIOD_IS_IN : GPIOD_IS_OUT;
+ priv->active_delay_ms = dev_read_u32_default(dev, "active-delay-ms", 100);
+ priv->inactive_delay_ms = dev_read_u32_default(dev, "inactive-delay-ms", 100);
+ priv->timeout_ms = dev_read_u32_default(dev, "timeout-ms", 3000);
+
+ return gpio_request_by_name(dev, "gpios", 0, &priv->gpio, flags);
+}
+
+static struct sysreset_ops poweroff_gpio_ops = {
+ .request = poweroff_gpio_request,
+};
+
+static const struct udevice_id poweroff_gpio_ids[] = {
+ { .compatible = "gpio-poweroff", },
+ {},
+};
+
+U_BOOT_DRIVER(poweroff_gpio) = {
+ .name = "poweroff-gpio",
+ .id = UCLASS_SYSRESET,
+ .ops = &poweroff_gpio_ops,
+ .probe = poweroff_gpio_probe,
+ .priv_auto_alloc_size = sizeof(struct poweroff_gpio_info),
+ .of_match = poweroff_gpio_ids,
+};
#include <dm/device.h>
#include <errno.h>
#include <fuse.h>
+#include <linux/delay.h>
#include <malloc.h>
#include <thermal.h>
config HW_WATCHDOG
bool
-config WATCHDOG_RESET_DISABLE
- bool "Disable reset watchdog"
- help
- Disable reset watchdog, which can let WATCHDOG_RESET invalid, so
- that the watchdog will not be fed in u-boot.
-
config IMX_WATCHDOG
bool "Enable Watchdog Timer support for IMX and LSCH2 of NXP"
select HW_WATCHDOG if !WDT
Select this to enable the IMX and LSCH2 of Layerscape watchdog
driver.
+config WATCHDOG_RESET_DISABLE
+ bool "Disable reset watchdog"
+ depends on IMX_WATCHDOG
+ help
+ Disable reset watchdog, which can let WATCHDOG_RESET invalid, so
+ that the watchdog will not be fed in u-boot.
+
config OMAP_WATCHDOG
bool "TI OMAP watchdog driver"
depends on ARCH_OMAP2PLUS
--- /dev/null
+/*
+ * GE B1x5v2
+ *
+ * Copyright 2018-2020 GE Inc.
+ * Copyright 2018-2020 Collabora Ltd.
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#ifndef __GE_B1X5V2_CONFIG_H
+#define __GE_B1X5V2_CONFIG_H
+
+#include "mx6_common.h"
+
+#include "imx6_spl.h"
+#define CONFIG_SPL_TARGET "u-boot-with-spl.imx"
+
+/* Size of malloc() pool */
+#define CONFIG_SYS_MALLOC_LEN (10 * SZ_1M)
+
+/* PWM */
+#define CONFIG_IMX6_PWM_PER_CLK 66000000
+
+/* UART */
+#define CONFIG_MXC_UART_BASE UART3_BASE
+
+#if CONFIG_MXC_UART_BASE == UART2_BASE
+/* UART2 requires CONFIG_DEBUG_UART_BASE=0x21e8000 */
+#define CONSOLE_DEVICE "ttymxc1" /* System on Module debug connector */
+#else
+/* UART3 requires CONFIG_DEBUG_UART_BASE=0x21ec000 */
+#define CONSOLE_DEVICE "ttymxc2" /* Base board debug connector */
+#endif
+
+/* USB */
+#define CONFIG_EHCI_HCD_INIT_AFTER_RESET
+#define CONFIG_MXC_USB_PORTSC (PORT_PTS_UTMI | PORT_PTS_PTW)
+#define CONFIG_MXC_USB_FLAGS 0
+#define CONFIG_USB_MAX_CONTROLLER_COUNT 2 /* Enabled USB controller number */
+#define CONFIG_USBD_HS
+
+/* Video */
+#define CONFIG_HIDE_LOGO_VERSION
+#define CONFIG_IMX_VIDEO_SKIP
+
+/* Memory */
+#define PHYS_SDRAM MMDC0_ARB_BASE_ADDR
+
+#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM
+#define CONFIG_SYS_INIT_RAM_ADDR IRAM_BASE_ADDR
+#define CONFIG_SYS_INIT_RAM_SIZE IRAM_SIZE
+
+#define CONFIG_SYS_INIT_SP_OFFSET \
+ (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
+#define CONFIG_SYS_INIT_SP_ADDR \
+ (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET)
+
+/* Command definition */
+#define CONFIG_EXTRA_ENV_SETTINGS \
+ "image=/boot/fitImage\0" \
+ "fdt_addr_r=0x18000000\0" \
+ "splash_addr_r=0x20000000\0" \
+ "mmcdev=2\0" \
+ "mmcpart=1\0" \
+ "console=console="CONSOLE_DEVICE",115200\0" \
+ "quiet=quiet loglevel=0\0" \
+ "rootdev=/dev/mmcblk1p\0" \
+ "setargs=setenv bootargs ${console} ${quiet} ${fsckforcerepair} " \
+ "bootcause=${bootcause} vt.global_cursor_default=0 vt.cur_default=1 " \
+ "root=${rootdev}${mmcpart} video=HDMI-A-1:${resolution} rootwait ro\0" \
+ "loadimage=load mmc ${mmcdev}:${mmcpart} ${loadaddr} ${image}\0" \
+ "showsplashscreen=load mmc ${mmcdev}:${mmcpart} ${splash_addr_r} /boot/splashscreen-${resolution}.bmp; " \
+ "bmp display ${splash_addr_r};\0" \
+ "setconfidx=" \
+ "if test \"${devicetype}\" = \"B105v2\"; then " \
+ "setenv confidx 1; " \
+ "elif test \"${devicetype}\" = \"B125v2\"; then " \
+ "setenv confidx 2; " \
+ "elif test \"${devicetype}\" = \"B155v2\"; then " \
+ "setenv confidx 3; " \
+ "elif test \"${devicetype}\" = \"B105Pv2\"; then " \
+ "setenv confidx 4; " \
+ "elif test \"${devicetype}\" = \"B125Pv2\"; then " \
+ "setenv confidx 5; " \
+ "fi;\0" \
+ "set_default_type=setenv devicetype B155v2; setenv resolution 1366x768;" \
+ "setenv fdtfile imx6dl-b155v2.dtb; run setconfidx;\0" \
+ "checkconfidx=env exists confidx || run set_default_type;\0" \
+ "checkfsckforcerepair=" \
+ "if test \"${bootcount}\" > \"3\" ; then " \
+ "setenv fsckforcerepair fsck.repair=1; " \
+ "fi;\0" \
+ "helix=run setconfidx; run checkconfidx; run checkfsckforcerepair; run setargs; " \
+ "regulator dev LED_VCC; regulator enable; " \
+ "regulator dev 5V0_AUDIO; regulator enable; " \
+ "bootm ${loadaddr}#conf@${confidx};\0" \
+ "failbootcmd=" \
+ "echo reached failbootcmd;" \
+ "cls; setcurs 5 4; " \
+ "lcdputs \"Monitor failed to start. Try again, or contact GE Service for support.\"; " \
+ "bootcount reset; \0" \
+ "hasfirstboot=" \
+ "load mmc ${mmcdev}:${mmcpart} ${loadaddr} " \
+ "/boot/bootcause/firstboot;\0" \
+ "swappartitions=" \
+ "setexpr mmcpart 3 - ${mmcpart};\0" \
+ "doboot=" \
+ "echo Booting from mmc:${mmcdev}:${mmcpart} ...; " \
+ "run helix;\0" \
+ "altbootcmd=" \
+ "setenv mmcpart 1; run hasfirstboot || setenv mmcpart 2; " \
+ "run hasfirstboot || setenv mmcpart 0; " \
+ "if test ${mmcpart} != 0; then " \
+ "setenv bootcause REVERT; " \
+ "run swappartitions loadimage doboot; " \
+ "fi; " \
+ "run failbootcmd\0" \
+ "tryboot=" \
+ "setenv mmcpart 1; run hasfirstboot || setenv mmcpart 2; " \
+ "run loadimage || run swappartitions && run loadimage || " \
+ "setenv mmcpart 0 && echo MISSING IMAGE;" \
+ "run showsplashscreen; sleep 1; " \
+ "run doboot; run failbootcmd;\0" \
+
+#define CONFIG_BOOTCOMMAND "run tryboot;"
+
+#endif /* __GE_B1X5V2_CONFIG_H */
--- /dev/null
+/* SPDX-License-Identifier: GPL-2.0-or-later
+ *
+ * Copyright (C) 2019-2020 PHYTEC Messtechnik GmbH
+ * Author: Teresa Remmet <t.remmet@phytec.de>
+ */
+
+#ifndef __PHYCORE_IMX8MM_H
+#define __PHYCORE_IMX8MM_H
+
+#include <linux/sizes.h>
+#include <linux/stringify.h>
+#include <asm/arch/imx-regs.h>
+
+#define CONFIG_SYS_BOOTM_LEN SZ_64M
+#define CONFIG_SPL_MAX_SIZE (148 * SZ_1K)
+#define CONFIG_SYS_MONITOR_LEN SZ_512K
+#define CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR
+#define CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR 0x300
+#define CONFIG_SYS_UBOOT_BASE \
+ (QSPI0_AMBA_BASE + CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR * 512)
+
+#ifdef CONFIG_SPL_BUILD
+#define CONFIG_SPL_STACK 0x920000
+#define CONFIG_SPL_BSS_START_ADDR 0x910000
+#define CONFIG_SPL_BSS_MAX_SIZE SZ_8K
+#define CONFIG_SYS_SPL_MALLOC_START 0x42200000
+#define CONFIG_SYS_SPL_MALLOC_SIZE SZ_512K
+
+/* malloc f used before GD_FLG_FULL_MALLOC_INIT set */
+#define CONFIG_MALLOC_F_ADDR 0x930000
+/* For RAW image gives a error info not panic */
+#define CONFIG_SPL_ABORT_ON_RAW_IMAGE
+#endif
+
+#define CONFIG_EXTRA_ENV_SETTINGS \
+ "image=Image\0" \
+ "console=ttymxc2,115200\0" \
+ "fdt_addr=0x48000000\0" \
+ "fdt_file=" CONFIG_DEFAULT_FDT_FILE "\0" \
+ "ipaddr=192.168.3.11\0" \
+ "serverip=192.168.3.10\0" \
+ "netmask=255.225.255.0\0" \
+ "ip_dyn=no\0" \
+ "mmcdev=" __stringify(CONFIG_SYS_MMC_ENV_DEV) "\0" \
+ "mmcpart=" __stringify(CONFIG_SYS_MMC_IMG_LOAD_PART) "\0" \
+ "mmcroot=2\0" \
+ "mmcautodetect=yes\0" \
+ "mmcargs=setenv bootargs console=${console} " \
+ "root=/dev/mmcblk${mmcdev}p${mmcroot} rootwait rw\0" \
+ "loadimage=fatload mmc ${mmcdev}:${mmcpart} ${loadaddr} ${image}\0" \
+ "loadfdt=fatload mmc ${mmcdev}:${mmcpart} ${fdt_addr} ${fdt_file}\0" \
+ "mmcboot=echo Booting from mmc ...; " \
+ "run mmcargs; " \
+ "if run loadfdt; then " \
+ "booti ${loadaddr} - ${fdt_addr}; " \
+ "else " \
+ "echo WARN: Cannot load the DT; " \
+ "fi;\0 " \
+ "nfsroot=/nfs\0" \
+ "netargs=setenv bootargs console=${console} root=/dev/nfs ip=dhcp " \
+ "nfsroot=${serverip}:${nfsroot},v3,tcp\0" \
+ "netboot=echo Booting from net ...; " \
+ "run netargs; " \
+ "if test ${ip_dyn} = yes; then " \
+ "setenv get_cmd dhcp; " \
+ "else " \
+ "setenv get_cmd tftp; " \
+ "fi; " \
+ "${get_cmd} ${loadaddr} ${image}; " \
+ "if ${get_cmd} ${fdt_addr} ${fdt_file}; then " \
+ "booti ${loadaddr} - ${fdt_addr}; " \
+ "else " \
+ "echo WARN: Cannot load the DT; " \
+ "fi;\0" \
+
+#define CONFIG_BOOTCOMMAND \
+ "mmc dev ${mmcdev}; if mmc rescan; then " \
+ "if run loadimage; then " \
+ "run mmcboot; " \
+ "else run netboot; " \
+ "fi; " \
+ "fi;"
+
+/* Link Definitions */
+#define CONFIG_LOADADDR 0x40480000
+#define CONFIG_SYS_LOAD_ADDR CONFIG_LOADADDR
+
+#define CONFIG_SYS_INIT_RAM_ADDR 0x40000000
+#define CONFIG_SYS_INIT_RAM_SIZE SZ_512K
+#define CONFIG_SYS_INIT_SP_OFFSET \
+ (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
+#define CONFIG_SYS_INIT_SP_ADDR \
+ (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET)
+
+#define CONFIG_MMCROOT "/dev/mmcblk2p2" /* USDHC3 */
+
+/* Size of malloc() pool */
+#define CONFIG_SYS_MALLOC_LEN SZ_32M
+#define CONFIG_SYS_SDRAM_BASE 0x40000000
+
+#define PHYS_SDRAM SZ_1G
+#define PHYS_SDRAM_SIZE SZ_2G /* 2GB DDR */
+
+/* UART */
+#define CONFIG_MXC_UART_BASE UART3_BASE_ADDR
+
+/* Monitor Command Prompt */
+#define CONFIG_SYS_PROMPT_HUSH_PS2 "> "
+#define CONFIG_SYS_CBSIZE SZ_2K
+#define CONFIG_SYS_MAXARGS 64
+#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE
+#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + \
+ sizeof(CONFIG_SYS_PROMPT) + 16)
+/* USDHC */
+#define CONFIG_FSL_USDHC
+#define CONFIG_SYS_FSL_USDHC_NUM 2
+#define CONFIG_SYS_FSL_ESDHC_ADDR 0
+#define CONFIG_SYS_MMC_IMG_LOAD_PART 1
+
+/* I2C */
+#define CONFIG_SYS_I2C_SPEED 100000
+
+/* ENET1 */
+#define CONFIG_ETHPRIME "FEC"
+#define CONFIG_FEC_XCV_TYPE RGMII
+#define CONFIG_FEC_MXC_PHYADDR 0
+#define FEC_QUIRK_ENET_MAC
+#define IMX_FEC_BASE 0x30BE0000
+
+#endif /* __PHYCORE_IMX8MM_H */
projects / platform / kernel / u-boot.git / commitdiff