define i32 @aext_sllw_aext_aext(i32 %a, i32 %b) nounwind {
; RV64I-LABEL: aext_sllw_aext_aext:
; RV64I: # %bb.0:
-; RV64I-NEXT: sll a0, a0, a1
+; RV64I-NEXT: sllw a0, a0, a1
; RV64I-NEXT: ret
%1 = shl i32 %a, %b
ret i32 %1
define i32 @aext_sllw_aext_sext(i32 %a, i32 signext %b) nounwind {
; RV64I-LABEL: aext_sllw_aext_sext:
; RV64I: # %bb.0:
-; RV64I-NEXT: sll a0, a0, a1
+; RV64I-NEXT: sllw a0, a0, a1
; RV64I-NEXT: ret
%1 = shl i32 %a, %b
ret i32 %1
define i32 @aext_sllw_aext_zext(i32 %a, i32 zeroext %b) nounwind {
; RV64I-LABEL: aext_sllw_aext_zext:
; RV64I: # %bb.0:
-; RV64I-NEXT: sll a0, a0, a1
+; RV64I-NEXT: sllw a0, a0, a1
; RV64I-NEXT: ret
%1 = shl i32 %a, %b
ret i32 %1
define i32 @aext_sllw_sext_aext(i32 signext %a, i32 %b) nounwind {
; RV64I-LABEL: aext_sllw_sext_aext:
; RV64I: # %bb.0:
-; RV64I-NEXT: sll a0, a0, a1
+; RV64I-NEXT: sllw a0, a0, a1
; RV64I-NEXT: ret
%1 = shl i32 %a, %b
ret i32 %1
define i32 @aext_sllw_sext_sext(i32 signext %a, i32 signext %b) nounwind {
; RV64I-LABEL: aext_sllw_sext_sext:
; RV64I: # %bb.0:
-; RV64I-NEXT: sll a0, a0, a1
+; RV64I-NEXT: sllw a0, a0, a1
; RV64I-NEXT: ret
%1 = shl i32 %a, %b
ret i32 %1
define i32 @aext_sllw_sext_zext(i32 signext %a, i32 zeroext %b) nounwind {
; RV64I-LABEL: aext_sllw_sext_zext:
; RV64I: # %bb.0:
-; RV64I-NEXT: sll a0, a0, a1
+; RV64I-NEXT: sllw a0, a0, a1
; RV64I-NEXT: ret
%1 = shl i32 %a, %b
ret i32 %1
define i32 @aext_sllw_zext_aext(i32 zeroext %a, i32 %b) nounwind {
; RV64I-LABEL: aext_sllw_zext_aext:
; RV64I: # %bb.0:
-; RV64I-NEXT: sll a0, a0, a1
+; RV64I-NEXT: sllw a0, a0, a1
; RV64I-NEXT: ret
%1 = shl i32 %a, %b
ret i32 %1
define i32 @aext_sllw_zext_sext(i32 zeroext %a, i32 signext %b) nounwind {
; RV64I-LABEL: aext_sllw_zext_sext:
; RV64I: # %bb.0:
-; RV64I-NEXT: sll a0, a0, a1
+; RV64I-NEXT: sllw a0, a0, a1
; RV64I-NEXT: ret
%1 = shl i32 %a, %b
ret i32 %1
define i32 @aext_sllw_zext_zext(i32 zeroext %a, i32 zeroext %b) nounwind {
; RV64I-LABEL: aext_sllw_zext_zext:
; RV64I: # %bb.0:
-; RV64I-NEXT: sll a0, a0, a1
+; RV64I-NEXT: sllw a0, a0, a1
; RV64I-NEXT: ret
%1 = shl i32 %a, %b
ret i32 %1
}
-; TODO: Select sllw for all cases witha signext result.
-
define signext i32 @sext_sllw_aext_aext(i32 %a, i32 %b) nounwind {
; RV64I-LABEL: sext_sllw_aext_aext:
; RV64I: # %bb.0:
-; RV64I-NEXT: sll a0, a0, a1
-; RV64I-NEXT: sext.w a0, a0
+; RV64I-NEXT: sllw a0, a0, a1
; RV64I-NEXT: ret
%1 = shl i32 %a, %b
ret i32 %1
define signext i32 @sext_sllw_aext_sext(i32 %a, i32 signext %b) nounwind {
; RV64I-LABEL: sext_sllw_aext_sext:
; RV64I: # %bb.0:
-; RV64I-NEXT: sll a0, a0, a1
-; RV64I-NEXT: sext.w a0, a0
+; RV64I-NEXT: sllw a0, a0, a1
; RV64I-NEXT: ret
%1 = shl i32 %a, %b
ret i32 %1
define signext i32 @sext_sllw_aext_zext(i32 %a, i32 zeroext %b) nounwind {
; RV64I-LABEL: sext_sllw_aext_zext:
; RV64I: # %bb.0:
-; RV64I-NEXT: sll a0, a0, a1
-; RV64I-NEXT: sext.w a0, a0
+; RV64I-NEXT: sllw a0, a0, a1
; RV64I-NEXT: ret
%1 = shl i32 %a, %b
ret i32 %1
define signext i32 @sext_sllw_sext_aext(i32 signext %a, i32 %b) nounwind {
; RV64I-LABEL: sext_sllw_sext_aext:
; RV64I: # %bb.0:
-; RV64I-NEXT: sll a0, a0, a1
-; RV64I-NEXT: sext.w a0, a0
+; RV64I-NEXT: sllw a0, a0, a1
; RV64I-NEXT: ret
%1 = shl i32 %a, %b
ret i32 %1
define signext i32 @sext_sllw_sext_sext(i32 signext %a, i32 signext %b) nounwind {
; RV64I-LABEL: sext_sllw_sext_sext:
; RV64I: # %bb.0:
-; RV64I-NEXT: sll a0, a0, a1
-; RV64I-NEXT: sext.w a0, a0
+; RV64I-NEXT: sllw a0, a0, a1
; RV64I-NEXT: ret
%1 = shl i32 %a, %b
ret i32 %1
define signext i32 @sext_sllw_sext_zext(i32 signext %a, i32 zeroext %b) nounwind {
; RV64I-LABEL: sext_sllw_sext_zext:
; RV64I: # %bb.0:
-; RV64I-NEXT: sll a0, a0, a1
-; RV64I-NEXT: sext.w a0, a0
+; RV64I-NEXT: sllw a0, a0, a1
; RV64I-NEXT: ret
%1 = shl i32 %a, %b
ret i32 %1
define signext i32 @sext_sllw_zext_aext(i32 zeroext %a, i32 %b) nounwind {
; RV64I-LABEL: sext_sllw_zext_aext:
; RV64I: # %bb.0:
-; RV64I-NEXT: sll a0, a0, a1
-; RV64I-NEXT: sext.w a0, a0
+; RV64I-NEXT: sllw a0, a0, a1
; RV64I-NEXT: ret
%1 = shl i32 %a, %b
ret i32 %1
define signext i32 @sext_sllw_zext_sext(i32 zeroext %a, i32 signext %b) nounwind {
; RV64I-LABEL: sext_sllw_zext_sext:
; RV64I: # %bb.0:
-; RV64I-NEXT: sll a0, a0, a1
-; RV64I-NEXT: sext.w a0, a0
+; RV64I-NEXT: sllw a0, a0, a1
; RV64I-NEXT: ret
%1 = shl i32 %a, %b
ret i32 %1
define signext i32 @sext_sllw_zext_zext(i32 zeroext %a, i32 zeroext %b) nounwind {
; RV64I-LABEL: sext_sllw_zext_zext:
; RV64I: # %bb.0:
-; RV64I-NEXT: sll a0, a0, a1
-; RV64I-NEXT: sext.w a0, a0
+; RV64I-NEXT: sllw a0, a0, a1
; RV64I-NEXT: ret
%1 = shl i32 %a, %b
ret i32 %1
define zeroext i32 @zext_sllw_aext_aext(i32 %a, i32 %b) nounwind {
; RV64I-LABEL: zext_sllw_aext_aext:
; RV64I: # %bb.0:
-; RV64I-NEXT: sll a0, a0, a1
+; RV64I-NEXT: sllw a0, a0, a1
; RV64I-NEXT: slli a0, a0, 32
; RV64I-NEXT: srli a0, a0, 32
; RV64I-NEXT: ret
define zeroext i32 @zext_sllw_aext_sext(i32 %a, i32 signext %b) nounwind {
; RV64I-LABEL: zext_sllw_aext_sext:
; RV64I: # %bb.0:
-; RV64I-NEXT: sll a0, a0, a1
+; RV64I-NEXT: sllw a0, a0, a1
; RV64I-NEXT: slli a0, a0, 32
; RV64I-NEXT: srli a0, a0, 32
; RV64I-NEXT: ret
define zeroext i32 @zext_sllw_aext_zext(i32 %a, i32 zeroext %b) nounwind {
; RV64I-LABEL: zext_sllw_aext_zext:
; RV64I: # %bb.0:
-; RV64I-NEXT: sll a0, a0, a1
+; RV64I-NEXT: sllw a0, a0, a1
; RV64I-NEXT: slli a0, a0, 32
; RV64I-NEXT: srli a0, a0, 32
; RV64I-NEXT: ret
define zeroext i32 @zext_sllw_sext_aext(i32 signext %a, i32 %b) nounwind {
; RV64I-LABEL: zext_sllw_sext_aext:
; RV64I: # %bb.0:
-; RV64I-NEXT: sll a0, a0, a1
+; RV64I-NEXT: sllw a0, a0, a1
; RV64I-NEXT: slli a0, a0, 32
; RV64I-NEXT: srli a0, a0, 32
; RV64I-NEXT: ret
define zeroext i32 @zext_sllw_sext_sext(i32 signext %a, i32 signext %b) nounwind {
; RV64I-LABEL: zext_sllw_sext_sext:
; RV64I: # %bb.0:
-; RV64I-NEXT: sll a0, a0, a1
+; RV64I-NEXT: sllw a0, a0, a1
; RV64I-NEXT: slli a0, a0, 32
; RV64I-NEXT: srli a0, a0, 32
; RV64I-NEXT: ret
define zeroext i32 @zext_sllw_sext_zext(i32 signext %a, i32 zeroext %b) nounwind {
; RV64I-LABEL: zext_sllw_sext_zext:
; RV64I: # %bb.0:
-; RV64I-NEXT: sll a0, a0, a1
+; RV64I-NEXT: sllw a0, a0, a1
; RV64I-NEXT: slli a0, a0, 32
; RV64I-NEXT: srli a0, a0, 32
; RV64I-NEXT: ret
define zeroext i32 @zext_sllw_zext_aext(i32 zeroext %a, i32 %b) nounwind {
; RV64I-LABEL: zext_sllw_zext_aext:
; RV64I: # %bb.0:
-; RV64I-NEXT: sll a0, a0, a1
+; RV64I-NEXT: sllw a0, a0, a1
; RV64I-NEXT: slli a0, a0, 32
; RV64I-NEXT: srli a0, a0, 32
; RV64I-NEXT: ret
define zeroext i32 @zext_sllw_zext_sext(i32 zeroext %a, i32 signext %b) nounwind {
; RV64I-LABEL: zext_sllw_zext_sext:
; RV64I: # %bb.0:
-; RV64I-NEXT: sll a0, a0, a1
+; RV64I-NEXT: sllw a0, a0, a1
; RV64I-NEXT: slli a0, a0, 32
; RV64I-NEXT: srli a0, a0, 32
; RV64I-NEXT: ret
define zeroext i32 @zext_sllw_zext_zext(i32 zeroext %a, i32 zeroext %b) nounwind {
; RV64I-LABEL: zext_sllw_zext_zext:
; RV64I: # %bb.0:
-; RV64I-NEXT: sll a0, a0, a1
+; RV64I-NEXT: sllw a0, a0, a1
; RV64I-NEXT: slli a0, a0, 32
; RV64I-NEXT: srli a0, a0, 32
; RV64I-NEXT: ret
ret i32 %1
}
-; TODO: srlw should be selected for 32-bit lshr with variable arguments.
-
define i32 @aext_srlw_aext_aext(i32 %a, i32 %b) nounwind {
; RV64I-LABEL: aext_srlw_aext_aext:
; RV64I: # %bb.0:
-; RV64I-NEXT: slli a0, a0, 32
-; RV64I-NEXT: srli a0, a0, 32
-; RV64I-NEXT: srl a0, a0, a1
+; RV64I-NEXT: srlw a0, a0, a1
; RV64I-NEXT: ret
%1 = lshr i32 %a, %b
ret i32 %1
define i32 @aext_srlw_aext_sext(i32 %a, i32 signext %b) nounwind {
; RV64I-LABEL: aext_srlw_aext_sext:
; RV64I: # %bb.0:
-; RV64I-NEXT: slli a0, a0, 32
-; RV64I-NEXT: srli a0, a0, 32
-; RV64I-NEXT: srl a0, a0, a1
+; RV64I-NEXT: srlw a0, a0, a1
; RV64I-NEXT: ret
%1 = lshr i32 %a, %b
ret i32 %1
define i32 @aext_srlw_aext_zext(i32 %a, i32 zeroext %b) nounwind {
; RV64I-LABEL: aext_srlw_aext_zext:
; RV64I: # %bb.0:
-; RV64I-NEXT: slli a0, a0, 32
-; RV64I-NEXT: srli a0, a0, 32
-; RV64I-NEXT: srl a0, a0, a1
+; RV64I-NEXT: srlw a0, a0, a1
; RV64I-NEXT: ret
%1 = lshr i32 %a, %b
ret i32 %1
define i32 @aext_srlw_sext_aext(i32 signext %a, i32 %b) nounwind {
; RV64I-LABEL: aext_srlw_sext_aext:
; RV64I: # %bb.0:
-; RV64I-NEXT: slli a0, a0, 32
-; RV64I-NEXT: srli a0, a0, 32
-; RV64I-NEXT: srl a0, a0, a1
+; RV64I-NEXT: srlw a0, a0, a1
; RV64I-NEXT: ret
%1 = lshr i32 %a, %b
ret i32 %1
define i32 @aext_srlw_sext_sext(i32 signext %a, i32 signext %b) nounwind {
; RV64I-LABEL: aext_srlw_sext_sext:
; RV64I: # %bb.0:
-; RV64I-NEXT: slli a0, a0, 32
-; RV64I-NEXT: srli a0, a0, 32
-; RV64I-NEXT: srl a0, a0, a1
+; RV64I-NEXT: srlw a0, a0, a1
; RV64I-NEXT: ret
%1 = lshr i32 %a, %b
ret i32 %1
define i32 @aext_srlw_sext_zext(i32 signext %a, i32 zeroext %b) nounwind {
; RV64I-LABEL: aext_srlw_sext_zext:
; RV64I: # %bb.0:
-; RV64I-NEXT: slli a0, a0, 32
-; RV64I-NEXT: srli a0, a0, 32
-; RV64I-NEXT: srl a0, a0, a1
+; RV64I-NEXT: srlw a0, a0, a1
; RV64I-NEXT: ret
%1 = lshr i32 %a, %b
ret i32 %1
define i32 @aext_srlw_zext_aext(i32 zeroext %a, i32 %b) nounwind {
; RV64I-LABEL: aext_srlw_zext_aext:
; RV64I: # %bb.0:
-; RV64I-NEXT: srl a0, a0, a1
+; RV64I-NEXT: srlw a0, a0, a1
; RV64I-NEXT: ret
%1 = lshr i32 %a, %b
ret i32 %1
define i32 @aext_srlw_zext_sext(i32 zeroext %a, i32 signext %b) nounwind {
; RV64I-LABEL: aext_srlw_zext_sext:
; RV64I: # %bb.0:
-; RV64I-NEXT: srl a0, a0, a1
+; RV64I-NEXT: srlw a0, a0, a1
; RV64I-NEXT: ret
%1 = lshr i32 %a, %b
ret i32 %1
define i32 @aext_srlw_zext_zext(i32 zeroext %a, i32 zeroext %b) nounwind {
; RV64I-LABEL: aext_srlw_zext_zext:
; RV64I: # %bb.0:
-; RV64I-NEXT: srl a0, a0, a1
+; RV64I-NEXT: srlw a0, a0, a1
; RV64I-NEXT: ret
%1 = lshr i32 %a, %b
ret i32 %1
define signext i32 @sext_srlw_aext_aext(i32 %a, i32 %b) nounwind {
; RV64I-LABEL: sext_srlw_aext_aext:
; RV64I: # %bb.0:
-; RV64I-NEXT: slli a0, a0, 32
-; RV64I-NEXT: srli a0, a0, 32
-; RV64I-NEXT: srl a0, a0, a1
-; RV64I-NEXT: sext.w a0, a0
+; RV64I-NEXT: srlw a0, a0, a1
; RV64I-NEXT: ret
%1 = lshr i32 %a, %b
ret i32 %1
define signext i32 @sext_srlw_aext_sext(i32 %a, i32 signext %b) nounwind {
; RV64I-LABEL: sext_srlw_aext_sext:
; RV64I: # %bb.0:
-; RV64I-NEXT: slli a0, a0, 32
-; RV64I-NEXT: srli a0, a0, 32
-; RV64I-NEXT: srl a0, a0, a1
-; RV64I-NEXT: sext.w a0, a0
+; RV64I-NEXT: srlw a0, a0, a1
; RV64I-NEXT: ret
%1 = lshr i32 %a, %b
ret i32 %1
define signext i32 @sext_srlw_aext_zext(i32 %a, i32 zeroext %b) nounwind {
; RV64I-LABEL: sext_srlw_aext_zext:
; RV64I: # %bb.0:
-; RV64I-NEXT: slli a0, a0, 32
-; RV64I-NEXT: srli a0, a0, 32
-; RV64I-NEXT: srl a0, a0, a1
-; RV64I-NEXT: sext.w a0, a0
+; RV64I-NEXT: srlw a0, a0, a1
; RV64I-NEXT: ret
%1 = lshr i32 %a, %b
ret i32 %1
define signext i32 @sext_srlw_sext_aext(i32 signext %a, i32 %b) nounwind {
; RV64I-LABEL: sext_srlw_sext_aext:
; RV64I: # %bb.0:
-; RV64I-NEXT: slli a0, a0, 32
-; RV64I-NEXT: srli a0, a0, 32
-; RV64I-NEXT: srl a0, a0, a1
-; RV64I-NEXT: sext.w a0, a0
+; RV64I-NEXT: srlw a0, a0, a1
; RV64I-NEXT: ret
%1 = lshr i32 %a, %b
ret i32 %1
define signext i32 @sext_srlw_sext_sext(i32 signext %a, i32 signext %b) nounwind {
; RV64I-LABEL: sext_srlw_sext_sext:
; RV64I: # %bb.0:
-; RV64I-NEXT: slli a0, a0, 32
-; RV64I-NEXT: srli a0, a0, 32
-; RV64I-NEXT: srl a0, a0, a1
-; RV64I-NEXT: sext.w a0, a0
+; RV64I-NEXT: srlw a0, a0, a1
; RV64I-NEXT: ret
%1 = lshr i32 %a, %b
ret i32 %1
define signext i32 @sext_srlw_sext_zext(i32 signext %a, i32 zeroext %b) nounwind {
; RV64I-LABEL: sext_srlw_sext_zext:
; RV64I: # %bb.0:
-; RV64I-NEXT: slli a0, a0, 32
-; RV64I-NEXT: srli a0, a0, 32
-; RV64I-NEXT: srl a0, a0, a1
-; RV64I-NEXT: sext.w a0, a0
+; RV64I-NEXT: srlw a0, a0, a1
; RV64I-NEXT: ret
%1 = lshr i32 %a, %b
ret i32 %1
define signext i32 @sext_srlw_zext_aext(i32 zeroext %a, i32 %b) nounwind {
; RV64I-LABEL: sext_srlw_zext_aext:
; RV64I: # %bb.0:
-; RV64I-NEXT: srl a0, a0, a1
-; RV64I-NEXT: sext.w a0, a0
+; RV64I-NEXT: srlw a0, a0, a1
; RV64I-NEXT: ret
%1 = lshr i32 %a, %b
ret i32 %1
define signext i32 @sext_srlw_zext_sext(i32 zeroext %a, i32 signext %b) nounwind {
; RV64I-LABEL: sext_srlw_zext_sext:
; RV64I: # %bb.0:
-; RV64I-NEXT: srl a0, a0, a1
-; RV64I-NEXT: sext.w a0, a0
+; RV64I-NEXT: srlw a0, a0, a1
; RV64I-NEXT: ret
%1 = lshr i32 %a, %b
ret i32 %1
define signext i32 @sext_srlw_zext_zext(i32 zeroext %a, i32 zeroext %b) nounwind {
; RV64I-LABEL: sext_srlw_zext_zext:
; RV64I: # %bb.0:
-; RV64I-NEXT: srl a0, a0, a1
-; RV64I-NEXT: sext.w a0, a0
+; RV64I-NEXT: srlw a0, a0, a1
; RV64I-NEXT: ret
%1 = lshr i32 %a, %b
ret i32 %1
define zeroext i32 @zext_srlw_aext_aext(i32 %a, i32 %b) nounwind {
; RV64I-LABEL: zext_srlw_aext_aext:
; RV64I: # %bb.0:
-; RV64I-NEXT: slli a0, a0, 32
-; RV64I-NEXT: srli a0, a0, 32
-; RV64I-NEXT: srl a0, a0, a1
+; RV64I-NEXT: srlw a0, a0, a1
; RV64I-NEXT: slli a0, a0, 32
; RV64I-NEXT: srli a0, a0, 32
; RV64I-NEXT: ret
define zeroext i32 @zext_srlw_aext_sext(i32 %a, i32 signext %b) nounwind {
; RV64I-LABEL: zext_srlw_aext_sext:
; RV64I: # %bb.0:
-; RV64I-NEXT: slli a0, a0, 32
-; RV64I-NEXT: srli a0, a0, 32
-; RV64I-NEXT: srl a0, a0, a1
+; RV64I-NEXT: srlw a0, a0, a1
; RV64I-NEXT: slli a0, a0, 32
; RV64I-NEXT: srli a0, a0, 32
; RV64I-NEXT: ret
define zeroext i32 @zext_srlw_aext_zext(i32 %a, i32 zeroext %b) nounwind {
; RV64I-LABEL: zext_srlw_aext_zext:
; RV64I: # %bb.0:
-; RV64I-NEXT: slli a0, a0, 32
-; RV64I-NEXT: srli a0, a0, 32
-; RV64I-NEXT: srl a0, a0, a1
+; RV64I-NEXT: srlw a0, a0, a1
; RV64I-NEXT: slli a0, a0, 32
; RV64I-NEXT: srli a0, a0, 32
; RV64I-NEXT: ret
define zeroext i32 @zext_srlw_sext_aext(i32 signext %a, i32 %b) nounwind {
; RV64I-LABEL: zext_srlw_sext_aext:
; RV64I: # %bb.0:
-; RV64I-NEXT: slli a0, a0, 32
-; RV64I-NEXT: srli a0, a0, 32
-; RV64I-NEXT: srl a0, a0, a1
+; RV64I-NEXT: srlw a0, a0, a1
; RV64I-NEXT: slli a0, a0, 32
; RV64I-NEXT: srli a0, a0, 32
; RV64I-NEXT: ret
define zeroext i32 @zext_srlw_sext_sext(i32 signext %a, i32 signext %b) nounwind {
; RV64I-LABEL: zext_srlw_sext_sext:
; RV64I: # %bb.0:
-; RV64I-NEXT: slli a0, a0, 32
-; RV64I-NEXT: srli a0, a0, 32
-; RV64I-NEXT: srl a0, a0, a1
+; RV64I-NEXT: srlw a0, a0, a1
; RV64I-NEXT: slli a0, a0, 32
; RV64I-NEXT: srli a0, a0, 32
; RV64I-NEXT: ret
define zeroext i32 @zext_srlw_sext_zext(i32 signext %a, i32 zeroext %b) nounwind {
; RV64I-LABEL: zext_srlw_sext_zext:
; RV64I: # %bb.0:
-; RV64I-NEXT: slli a0, a0, 32
-; RV64I-NEXT: srli a0, a0, 32
-; RV64I-NEXT: srl a0, a0, a1
+; RV64I-NEXT: srlw a0, a0, a1
; RV64I-NEXT: slli a0, a0, 32
; RV64I-NEXT: srli a0, a0, 32
; RV64I-NEXT: ret
define zeroext i32 @zext_srlw_zext_aext(i32 zeroext %a, i32 %b) nounwind {
; RV64I-LABEL: zext_srlw_zext_aext:
; RV64I: # %bb.0:
-; RV64I-NEXT: srl a0, a0, a1
+; RV64I-NEXT: srlw a0, a0, a1
; RV64I-NEXT: slli a0, a0, 32
; RV64I-NEXT: srli a0, a0, 32
; RV64I-NEXT: ret
define zeroext i32 @zext_srlw_zext_sext(i32 zeroext %a, i32 signext %b) nounwind {
; RV64I-LABEL: zext_srlw_zext_sext:
; RV64I: # %bb.0:
-; RV64I-NEXT: srl a0, a0, a1
+; RV64I-NEXT: srlw a0, a0, a1
; RV64I-NEXT: slli a0, a0, 32
; RV64I-NEXT: srli a0, a0, 32
; RV64I-NEXT: ret
define zeroext i32 @zext_srlw_zext_zext(i32 zeroext %a, i32 zeroext %b) nounwind {
; RV64I-LABEL: zext_srlw_zext_zext:
; RV64I: # %bb.0:
-; RV64I-NEXT: srl a0, a0, a1
+; RV64I-NEXT: srlw a0, a0, a1
; RV64I-NEXT: slli a0, a0, 32
; RV64I-NEXT: srli a0, a0, 32
; RV64I-NEXT: ret
ret i32 %1
}
-; TODO: sraw should be selected if the first operand is not sign-extended. If the
-; first operand is sign-extended, sra is equivalent for the test cases below.
-
define i32 @aext_sraw_aext_aext(i32 %a, i32 %b) nounwind {
; RV64I-LABEL: aext_sraw_aext_aext:
; RV64I: # %bb.0:
-; RV64I-NEXT: sext.w a0, a0
-; RV64I-NEXT: sra a0, a0, a1
+; RV64I-NEXT: sraw a0, a0, a1
; RV64I-NEXT: ret
%1 = ashr i32 %a, %b
ret i32 %1
define i32 @aext_sraw_aext_sext(i32 %a, i32 signext %b) nounwind {
; RV64I-LABEL: aext_sraw_aext_sext:
; RV64I: # %bb.0:
-; RV64I-NEXT: sext.w a0, a0
-; RV64I-NEXT: sra a0, a0, a1
+; RV64I-NEXT: sraw a0, a0, a1
; RV64I-NEXT: ret
%1 = ashr i32 %a, %b
ret i32 %1
define i32 @aext_sraw_aext_zext(i32 %a, i32 zeroext %b) nounwind {
; RV64I-LABEL: aext_sraw_aext_zext:
; RV64I: # %bb.0:
-; RV64I-NEXT: sext.w a0, a0
-; RV64I-NEXT: sra a0, a0, a1
+; RV64I-NEXT: sraw a0, a0, a1
; RV64I-NEXT: ret
%1 = ashr i32 %a, %b
ret i32 %1
define i32 @aext_sraw_sext_aext(i32 signext %a, i32 %b) nounwind {
; RV64I-LABEL: aext_sraw_sext_aext:
; RV64I: # %bb.0:
-; RV64I-NEXT: sra a0, a0, a1
+; RV64I-NEXT: sraw a0, a0, a1
; RV64I-NEXT: ret
%1 = ashr i32 %a, %b
ret i32 %1
define i32 @aext_sraw_sext_sext(i32 signext %a, i32 signext %b) nounwind {
; RV64I-LABEL: aext_sraw_sext_sext:
; RV64I: # %bb.0:
-; RV64I-NEXT: sra a0, a0, a1
+; RV64I-NEXT: sraw a0, a0, a1
; RV64I-NEXT: ret
%1 = ashr i32 %a, %b
ret i32 %1
define i32 @aext_sraw_sext_zext(i32 signext %a, i32 zeroext %b) nounwind {
; RV64I-LABEL: aext_sraw_sext_zext:
; RV64I: # %bb.0:
-; RV64I-NEXT: sra a0, a0, a1
+; RV64I-NEXT: sraw a0, a0, a1
; RV64I-NEXT: ret
%1 = ashr i32 %a, %b
ret i32 %1
define i32 @aext_sraw_zext_aext(i32 zeroext %a, i32 %b) nounwind {
; RV64I-LABEL: aext_sraw_zext_aext:
; RV64I: # %bb.0:
-; RV64I-NEXT: sext.w a0, a0
-; RV64I-NEXT: sra a0, a0, a1
+; RV64I-NEXT: sraw a0, a0, a1
; RV64I-NEXT: ret
%1 = ashr i32 %a, %b
ret i32 %1
define i32 @aext_sraw_zext_sext(i32 zeroext %a, i32 signext %b) nounwind {
; RV64I-LABEL: aext_sraw_zext_sext:
; RV64I: # %bb.0:
-; RV64I-NEXT: sext.w a0, a0
-; RV64I-NEXT: sra a0, a0, a1
+; RV64I-NEXT: sraw a0, a0, a1
; RV64I-NEXT: ret
%1 = ashr i32 %a, %b
ret i32 %1
define i32 @aext_sraw_zext_zext(i32 zeroext %a, i32 zeroext %b) nounwind {
; RV64I-LABEL: aext_sraw_zext_zext:
; RV64I: # %bb.0:
-; RV64I-NEXT: sext.w a0, a0
-; RV64I-NEXT: sra a0, a0, a1
+; RV64I-NEXT: sraw a0, a0, a1
; RV64I-NEXT: ret
%1 = ashr i32 %a, %b
ret i32 %1
define signext i32 @sext_sraw_aext_aext(i32 %a, i32 %b) nounwind {
; RV64I-LABEL: sext_sraw_aext_aext:
; RV64I: # %bb.0:
-; RV64I-NEXT: sext.w a0, a0
-; RV64I-NEXT: sra a0, a0, a1
+; RV64I-NEXT: sraw a0, a0, a1
; RV64I-NEXT: ret
%1 = ashr i32 %a, %b
ret i32 %1
define signext i32 @sext_sraw_aext_sext(i32 %a, i32 signext %b) nounwind {
; RV64I-LABEL: sext_sraw_aext_sext:
; RV64I: # %bb.0:
-; RV64I-NEXT: sext.w a0, a0
-; RV64I-NEXT: sra a0, a0, a1
+; RV64I-NEXT: sraw a0, a0, a1
; RV64I-NEXT: ret
%1 = ashr i32 %a, %b
ret i32 %1
define signext i32 @sext_sraw_aext_zext(i32 %a, i32 zeroext %b) nounwind {
; RV64I-LABEL: sext_sraw_aext_zext:
; RV64I: # %bb.0:
-; RV64I-NEXT: sext.w a0, a0
-; RV64I-NEXT: sra a0, a0, a1
+; RV64I-NEXT: sraw a0, a0, a1
; RV64I-NEXT: ret
%1 = ashr i32 %a, %b
ret i32 %1
define signext i32 @sext_sraw_sext_aext(i32 signext %a, i32 %b) nounwind {
; RV64I-LABEL: sext_sraw_sext_aext:
; RV64I: # %bb.0:
-; RV64I-NEXT: sra a0, a0, a1
+; RV64I-NEXT: sraw a0, a0, a1
; RV64I-NEXT: ret
%1 = ashr i32 %a, %b
ret i32 %1
define signext i32 @sext_sraw_sext_sext(i32 signext %a, i32 signext %b) nounwind {
; RV64I-LABEL: sext_sraw_sext_sext:
; RV64I: # %bb.0:
-; RV64I-NEXT: sra a0, a0, a1
+; RV64I-NEXT: sraw a0, a0, a1
; RV64I-NEXT: ret
%1 = ashr i32 %a, %b
ret i32 %1
define signext i32 @sext_sraw_sext_zext(i32 signext %a, i32 zeroext %b) nounwind {
; RV64I-LABEL: sext_sraw_sext_zext:
; RV64I: # %bb.0:
-; RV64I-NEXT: sra a0, a0, a1
+; RV64I-NEXT: sraw a0, a0, a1
; RV64I-NEXT: ret
%1 = ashr i32 %a, %b
ret i32 %1
define signext i32 @sext_sraw_zext_aext(i32 zeroext %a, i32 %b) nounwind {
; RV64I-LABEL: sext_sraw_zext_aext:
; RV64I: # %bb.0:
-; RV64I-NEXT: sext.w a0, a0
-; RV64I-NEXT: sra a0, a0, a1
+; RV64I-NEXT: sraw a0, a0, a1
; RV64I-NEXT: ret
%1 = ashr i32 %a, %b
ret i32 %1
define signext i32 @sext_sraw_zext_sext(i32 zeroext %a, i32 signext %b) nounwind {
; RV64I-LABEL: sext_sraw_zext_sext:
; RV64I: # %bb.0:
-; RV64I-NEXT: sext.w a0, a0
-; RV64I-NEXT: sra a0, a0, a1
+; RV64I-NEXT: sraw a0, a0, a1
; RV64I-NEXT: ret
%1 = ashr i32 %a, %b
ret i32 %1
define signext i32 @sext_sraw_zext_zext(i32 zeroext %a, i32 zeroext %b) nounwind {
; RV64I-LABEL: sext_sraw_zext_zext:
; RV64I: # %bb.0:
-; RV64I-NEXT: sext.w a0, a0
-; RV64I-NEXT: sra a0, a0, a1
+; RV64I-NEXT: sraw a0, a0, a1
; RV64I-NEXT: ret
%1 = ashr i32 %a, %b
ret i32 %1
define zeroext i32 @zext_sraw_aext_aext(i32 %a, i32 %b) nounwind {
; RV64I-LABEL: zext_sraw_aext_aext:
; RV64I: # %bb.0:
-; RV64I-NEXT: sext.w a0, a0
-; RV64I-NEXT: sra a0, a0, a1
+; RV64I-NEXT: sraw a0, a0, a1
; RV64I-NEXT: slli a0, a0, 32
; RV64I-NEXT: srli a0, a0, 32
; RV64I-NEXT: ret
define zeroext i32 @zext_sraw_aext_sext(i32 %a, i32 signext %b) nounwind {
; RV64I-LABEL: zext_sraw_aext_sext:
; RV64I: # %bb.0:
-; RV64I-NEXT: sext.w a0, a0
-; RV64I-NEXT: sra a0, a0, a1
+; RV64I-NEXT: sraw a0, a0, a1
; RV64I-NEXT: slli a0, a0, 32
; RV64I-NEXT: srli a0, a0, 32
; RV64I-NEXT: ret
define zeroext i32 @zext_sraw_aext_zext(i32 %a, i32 zeroext %b) nounwind {
; RV64I-LABEL: zext_sraw_aext_zext:
; RV64I: # %bb.0:
-; RV64I-NEXT: sext.w a0, a0
-; RV64I-NEXT: sra a0, a0, a1
+; RV64I-NEXT: sraw a0, a0, a1
; RV64I-NEXT: slli a0, a0, 32
; RV64I-NEXT: srli a0, a0, 32
; RV64I-NEXT: ret
define zeroext i32 @zext_sraw_sext_aext(i32 signext %a, i32 %b) nounwind {
; RV64I-LABEL: zext_sraw_sext_aext:
; RV64I: # %bb.0:
-; RV64I-NEXT: sra a0, a0, a1
+; RV64I-NEXT: sraw a0, a0, a1
; RV64I-NEXT: slli a0, a0, 32
; RV64I-NEXT: srli a0, a0, 32
; RV64I-NEXT: ret
define zeroext i32 @zext_sraw_sext_sext(i32 signext %a, i32 signext %b) nounwind {
; RV64I-LABEL: zext_sraw_sext_sext:
; RV64I: # %bb.0:
-; RV64I-NEXT: sra a0, a0, a1
+; RV64I-NEXT: sraw a0, a0, a1
; RV64I-NEXT: slli a0, a0, 32
; RV64I-NEXT: srli a0, a0, 32
; RV64I-NEXT: ret
define zeroext i32 @zext_sraw_sext_zext(i32 signext %a, i32 zeroext %b) nounwind {
; RV64I-LABEL: zext_sraw_sext_zext:
; RV64I: # %bb.0:
-; RV64I-NEXT: sra a0, a0, a1
+; RV64I-NEXT: sraw a0, a0, a1
; RV64I-NEXT: slli a0, a0, 32
; RV64I-NEXT: srli a0, a0, 32
; RV64I-NEXT: ret
define zeroext i32 @zext_sraw_zext_aext(i32 zeroext %a, i32 %b) nounwind {
; RV64I-LABEL: zext_sraw_zext_aext:
; RV64I: # %bb.0:
-; RV64I-NEXT: sext.w a0, a0
-; RV64I-NEXT: sra a0, a0, a1
+; RV64I-NEXT: sraw a0, a0, a1
; RV64I-NEXT: slli a0, a0, 32
; RV64I-NEXT: srli a0, a0, 32
; RV64I-NEXT: ret
define zeroext i32 @zext_sraw_zext_sext(i32 zeroext %a, i32 signext %b) nounwind {
; RV64I-LABEL: zext_sraw_zext_sext:
; RV64I: # %bb.0:
-; RV64I-NEXT: sext.w a0, a0
-; RV64I-NEXT: sra a0, a0, a1
+; RV64I-NEXT: sraw a0, a0, a1
; RV64I-NEXT: slli a0, a0, 32
; RV64I-NEXT: srli a0, a0, 32
; RV64I-NEXT: ret
define zeroext i32 @zext_sraw_zext_zext(i32 zeroext %a, i32 zeroext %b) nounwind {
; RV64I-LABEL: zext_sraw_zext_zext:
; RV64I: # %bb.0:
-; RV64I-NEXT: sext.w a0, a0
-; RV64I-NEXT: sra a0, a0, a1
+; RV64I-NEXT: sraw a0, a0, a1
; RV64I-NEXT: slli a0, a0, 32
; RV64I-NEXT: srli a0, a0, 32
; RV64I-NEXT: ret