* bfd/archures.c (bfd_arch_mt): Renamed.
(bfd_mt_arch): Renamed.
(bfd_archures_list): Adjusted.
* bfd/bfd-in2.h: Rebuilt.
* bfd/config.bfd (mt): Remove special case targ_archs.
(mt-*-elf): Rename bfd_elf32_mt_vec.
* bfd/configure: Rebuilt.
* bfd/configure.in (bfd_elf32_mt_vec): Renamed.
(selarchs) Remove mt special case.
* bfd/cpu-mt.c (arch_info_struct): Adjust.
(bfd_mt_arch): Renamed, adjust.
* bfd/elf32-mt.c (mt_reloc_type_lookup, mt_info_to_howto_rela,
mt_elf_relocate_hi16, mt_final_link_relocate, mt_relocate_section,
mt_elf_howto_table): Renamed, adjusted.
(mt_elf_gc_mark_hook, mt_elf_gc_sweep_hook, mt_elf_check_relocs,
elf32_mt_machine, mt_elf_object_p, mt_elf_set_private_flags,
mt_elf_copy_private_bfd_data, mt_elf_merge_private_bfd_data,
mt_elf_print_private_bfd_data): Renamed, adjusted.
(TARGET_BIG_SYM, TARGET_BIG_NAME, ELF_ARCH, ELF_MACHINE_CODE,
ELF_MAXPAGESIZE, elf_info_to_howto, elf_backend_relocate_section,
bfd_elf32_bfd_reloc_type_lookup, elf_backend_gc_mark_hook,
elf_backend_gc_sweep_hook, elf_backend_check_relocs,
eld_backend_object_p, bfd_elf32_bfd_set_private_flags,
bfd_elf32_bfd_copy_private_bfd_data,
bfd_elf32_bfd_merge_private_bfd_data,
bfd_elf32_bfd_print_private_bfd_data): Adjusted.
* bfd/libbfd.h: Regenerated.
* bfd/reloc.c (BFD_RELOC_MT_PC16, BFD_RELOC_MT_HI16,
BFD_RELOC_MT_LO16, BFD_RELOC_MT_GNU_VTINHERIT,
BFD_RELOC_MT_GNU_VTENTRY, BFD_RELOC_MT_PCINSN8): Renamed.
* bfd/targets.c (bfd_elf32_mt_vec): Renamed.
(_bfd_target_vector): Adjusted.
* binutils/readelf.c (guess_is_rela): Use EM_MT.
(dump_relocations, get_machine_name): Adjust.
* cpu/mt.cpu (define-arch, define-isa): Set name to mt.
(define-mach): Adjust.
* cpu/mt.opc (CGEN_ASM_HASH): Update.
(mt_asm_hash, mt_cgen_insn_supported): Renamed.
(parse_loopsize, parse_imm16): Adjust.
* gas/configure: Rebuilt.
* gas/configure.in (mt): Remove special case.
* gas/config/tc-mt.c (opcodes/mt-desc.h, opcodes/mt-opc.h): Change
#includes.
(mt_insn, mt_mach, mt_mach_bitmask, mt_flags, mt_architectures):
Rename, adjust.
(md_parse_option, md_show_usage, md_begin, md_assemble,
md_cgen_lookup_reloc, md_atof): Adjust.
(mt_force_relocation, mt_apply_fix, mt_fix_adjustable): Rename, adjust.
* gas/config/tc-mt.h (TC_MT): Rename.
(LISTING_HEADER, TARGET_ARCH, TARGET_FORMAT): Adjust.
(md_apply_fix): Adjust.
(mt_apply_fix, mt_fix_adjustable, mt_force_relocation): Rename.
(TC_FORCE_RELOCATION, tc_fix_adjustable): Adjust.
* gdb/mt-tdep.c (mt_arch_constants, mt_gdb_regnums): Rename, adjust.
(mt_register_name, mt_register_type, mt_register_reggroup_p,
mt_return_value, mt_skip_prologue, mt_breapoint_from_pc,
mt_pseudo_register_read, mt_pseudo_register_write, mt_frame_align,
mt_registers_info, mt_push_dummy_call, mt_unwind_cache,
mt_frame_unwind_cache, mt_unwind_pc, mt_unwind_dummy_id,
mt_frame_this_id, mt_frame_prev_register, mt_frame_base_address,
mt_frame_unwind, mt_frame_sniffer, mt_frame_base, mt_gdbarch_init,
_initialize_mt_tdep): Rename & adjust.
* include/dis-asm.h (print_insn_mt): Renamed.
* include/elf/common.h (EM_MT): Renamed.
* include/elf/mt.h: Rename relocs, cpu & other defines.
* ld/emulparams/elf32mt.sh (ARCH, OUTPUT_FORMAT): Adjust.
* opcodes/Makefile.am (HFILES, CFILES, ALL_MACHINES): Adjust.
(stamp-mt): Adjust rule.
(mt-asm.lo, mt-desc.lo, mt-dis.lo, mt-ibld.lo, mt-opc.lo): Rename &
adjust.
* opcodes/Makefile.in: Rebuilt.
* opcodes/configure: Rebuilt.
* opcodes/configure.in (bfd_mt_arch): Rename & adjust.
* opcodes/disassemble.c (ARCH_mt): Renamed.
(disassembler): Adjust.
* opcodes/mt-asm.c: Renamed, rebuilt.
* opcodes/mt-desc.c: Renamed, rebuilt.
* opcodes/mt-desc.h: Renamed, rebuilt.
* opcodes/mt-dis.c: Renamed, rebuilt.
* opcodes/mt-ibld.c: Renamed, rebuilt.
* opcodes/mt-opc.c: Renamed, rebuilt.
* opcodes/mt-opc.h: Renamed, rebuilt.
* sid/Makefile.in: Rebuilt.
* sid/aclocal.m4: Rebuilt.
* sid/configure: Rebuilt.
* sid/sid.spec: Adjust.
* sid/bsp/Makefile.am: Adjust.
* sid/bsp/Makefile.in: Rebuilt.
* sid/bsp/aclocal.m4: Rebuilt.
* sid/bsp/configrun-sid.in: Adjust.
* sid/bsp/pregen/Makefile.in: Rebuilt.
* sid/bsp/pregen/mt-gdb.conf: Renamed & rebuilt.
* sid/bsp/pregen/mt-gloss.conf: Renamed & rebuilt.
* sid/bsp/pregen/pregen-configs.in: Adjust.
* sid/component/aclocal.m4: Rebuilt.
* sid/component/configure: Rebuilt.
* sid/component/tconfig.in: Adjust.
* sid/component/bochs/aclocal.m4: Rebuilt.
* sid/component/cache/Makefile.in: Rebuilt.
* sid/component/cgen-cpu/Makefile.in: Rebuilt.
* sid/component/cgen-cpu/aclocal.m4: Rebuilt.
* sid/component/cgen-cpu/compCGEN.cxx: Adjust.
* sid/component/cgen-cpu/configure: Rebuilt.
* sid/component/cgen-cpu/configure.in: Rebult.
* sid/component/cgen-cpu/mt/Makefile.am: Adjust.
* sid/component/cgen-cpu/mt/Makefile.in: Rebuilt.
* sid/component/cgen-cpu/mt/hw-cpu-mt.txt: Adjust.
* sid/component/cgen-cpu/mt/mt-cpu.h: Rebuilt.
* sid/component/cgen-cpu/mt/mt-decode.cxx: Rebuilt.
* sid/component/cgen-cpu/mt/mt-decode.h: Rebuilt.
* sid/component/cgen-cpu/mt/mt-defs.h: Rebuilt.
* sid/component/cgen-cpu/mt/mt-desc.h: Rebuilt.
* sid/component/cgen-cpu/mt/mt-sem.cxx: Rebuilt.
* sid/component/cgen-cpu/mt/mt-write.cxx: Rebuilt.
* sid/component/cgen-cpu/mt/mt.cxx: Adjust.
* sid/component/cgen-cpu/mt/mt.h: Adjust.
* sid/component/consoles/Makefile.in: Rebuilt.
* sid/component/families/aclocal.m4: Rebuilt.
* sid/component/families/configure: Rebuilt.
* sid/component/gdb/Makefile.in: Rebuilt.
* sid/component/gloss/Makefile.in: Rebuilt.
* sid/component/glue/Makefile.in: Rebuilt.
* sid/component/ide/Makefile.in: Rebuilt.
* sid/component/interrupt/Makefile.in: Rebuilt.
* sid/component/lcd/Makefile.in: Rebuilt.
* sid/component/lcd/testsuite/Makefile.in: Rebuilt.
* sid/component/loader/Makefile.am: Rebuilt.
* sid/component/loader/Makefile.in: Rebuilt.
* sid/component/mapper/Makefile.in: Rebuilt.
* sid/component/mapper/testsuite/Makefile.in: Rebuilt.
* sid/component/memory/Makefile.in: Rebuilt.
* sid/component/mmu/Makefile.in: Rebuilt.
* sid/component/parport/Makefile.in: Rebuilt.
* sid/component/profiling/Makefile.in: Rebuilt.
* sid/component/rtc/Makefile.in: Rebuilt.
* sid/component/sched/Makefile.in: Rebuilt.
* sid/component/testsuite/Makefile.in: Rebuilt.
* sid/component/timers/aclocal.m4: Rebuilt.
* sid/component/timers/configure: Rebuilt.
* sid/component/uart/Makefile.in: Rebuilt.
* sid/component/uart/testsuite/Makefile.in: Rebuilt.
* sid/config/config.sub: Adjust.
* sid/config/info.tcl.in: Adjust.
* sid/config/sidtargets.m4: Adjust.
* sid/doc/Makefile.in: Rebuilt.
* sid/main/dynamic/Makefile.am: Rebuilt.
* sid/main/dynamic/Makefile.in: Rebuilt.
* sid/main/dynamic/aclocal.m4: Rebuilt.
* sid/main/dynamic/configure: Rebuilt.
+2005-12-16 Nathan Sidwell <nathan@codesourcery.com>
+
+ Second part of ms1 to mt renaming.
+ * archures.c (bfd_arch_mt): Renamed.
+ (bfd_mt_arch): Renamed.
+ (bfd_archures_list): Adjusted.
+ * bfd-in2.h: Rebuilt.
+ * config.bfd (mt): Remove special case targ_archs.
+ (mt-*-elf): Rename bfd_elf32_mt_vec.
+ * configure: Rebuilt.
+ * configure.in (bfd_elf32_mt_vec): Renamed.
+ (selarchs) Remove mt special case.
+ * cpu-mt.c (arch_info_struct): Adjust.
+ (bfd_mt_arch): Renamed, adjust.
+ * elf32-mt.c (mt_reloc_type_lookup, mt_info_to_howto_rela,
+ mt_elf_relocate_hi16, mt_final_link_relocate, mt_relocate_section,
+ mt_elf_howto_table): Renamed, adjusted.
+ (mt_elf_gc_mark_hook, mt_elf_gc_sweep_hook, mt_elf_check_relocs,
+ elf32_mt_machine, mt_elf_object_p, mt_elf_set_private_flags,
+ mt_elf_copy_private_bfd_data, mt_elf_merge_private_bfd_data,
+ mt_elf_print_private_bfd_data): Renamed, adjusted.
+ (TARGET_BIG_SYM, TARGET_BIG_NAME, ELF_ARCH, ELF_MACHINE_CODE,
+ ELF_MAXPAGESIZE, elf_info_to_howto, elf_backend_relocate_section,
+ bfd_elf32_bfd_reloc_type_lookup, elf_backend_gc_mark_hook,
+ elf_backend_gc_sweep_hook, elf_backend_check_relocs,
+ eld_backend_object_p, bfd_elf32_bfd_set_private_flags,
+ bfd_elf32_bfd_copy_private_bfd_data,
+ bfd_elf32_bfd_merge_private_bfd_data,
+ bfd_elf32_bfd_print_private_bfd_data): Adjusted.
+ * libbfd.h: Regenerated.
+ * reloc.c (BFD_RELOC_MT_PC16, BFD_RELOC_MT_HI16,
+ BFD_RELOC_MT_LO16, BFD_RELOC_MT_GNU_VTINHERIT,
+ BFD_RELOC_MT_GNU_VTENTRY, BFD_RELOC_MT_PCINSN8): Renamed.
+ * targets.c (bfd_elf32_mt_vec): Renamed.
+ (_bfd_target_vector): Adjusted.
+
2005-12-13 H.J. Lu <hongjiu.lu@intel.com>
PR ld/2008
. bfd_arch_iq2000, {* Vitesse IQ2000. *}
.#define bfd_mach_iq2000 1
.#define bfd_mach_iq10 2
-. bfd_arch_ms1,
+. bfd_arch_mt,
.#define bfd_mach_ms1 1
.#define bfd_mach_mrisc2 2
.#define bfd_mach_ms2 3
extern const bfd_arch_info_type bfd_mn10200_arch;
extern const bfd_arch_info_type bfd_mn10300_arch;
extern const bfd_arch_info_type bfd_msp430_arch;
-extern const bfd_arch_info_type bfd_ms1_arch;
+extern const bfd_arch_info_type bfd_mt_arch;
extern const bfd_arch_info_type bfd_ns32k_arch;
extern const bfd_arch_info_type bfd_openrisc_arch;
extern const bfd_arch_info_type bfd_or32_arch;
&bfd_mmix_arch,
&bfd_mn10200_arch,
&bfd_mn10300_arch,
- &bfd_ms1_arch,
+ &bfd_mt_arch,
&bfd_msp430_arch,
&bfd_ns32k_arch,
&bfd_openrisc_arch,
bfd_arch_iq2000, /* Vitesse IQ2000. */
#define bfd_mach_iq2000 1
#define bfd_mach_iq10 2
- bfd_arch_ms1,
+ bfd_arch_mt,
#define bfd_mach_ms1 1
#define bfd_mach_mrisc2 2
#define bfd_mach_ms2 3
BFD_RELOC_VAX_JMP_SLOT,
BFD_RELOC_VAX_RELATIVE,
-/* Morpho MS1 - 16 bit immediate relocation. */
- BFD_RELOC_MS1_PC16,
+/* Morpho MT - 16 bit immediate relocation. */
+ BFD_RELOC_MT_PC16,
-/* Morpho MS1 - Hi 16 bits of an address. */
- BFD_RELOC_MS1_HI16,
+/* Morpho MT - Hi 16 bits of an address. */
+ BFD_RELOC_MT_HI16,
-/* Morpho MS1 - Low 16 bits of an address. */
- BFD_RELOC_MS1_LO16,
+/* Morpho MT - Low 16 bits of an address. */
+ BFD_RELOC_MT_LO16,
-/* Morpho MS1 - Used to tell the linker which vtable entries are used. */
- BFD_RELOC_MS1_GNU_VTINHERIT,
+/* Morpho MT - Used to tell the linker which vtable entries are used. */
+ BFD_RELOC_MT_GNU_VTINHERIT,
-/* Morpho MS1 - Used to tell the linker which vtable entries are used. */
- BFD_RELOC_MS1_GNU_VTENTRY,
+/* Morpho MT - Used to tell the linker which vtable entries are used. */
+ BFD_RELOC_MT_GNU_VTENTRY,
-/* Morpho MS1 - 8 bit immediate relocation. */
- BFD_RELOC_MS1_PCINSN8,
+/* Morpho MT - 8 bit immediate relocation. */
+ BFD_RELOC_MT_PCINSN8,
/* msp430 specific relocation codes */
BFD_RELOC_MSP430_10_PCREL,
m88*) targ_archs=bfd_m88k_arch ;;
maxq*) targ_archs=bfd_maxq_arch ;;
mips*) targ_archs=bfd_mips_arch ;;
-mt) targ_archs=bfd_ms1_arch ;;
or32*) targ_archs=bfd_or32_arch ;;
pdp11*) targ_archs=bfd_pdp11_arch ;;
pj*) targ_archs="bfd_pj_arch bfd_i386_arch";;
;;
mt-*-elf)
- targ_defvec=bfd_elf32_ms1_vec
+ targ_defvec=bfd_elf32_mt_vec
;;
msp430-*-*)
bfd_elf32_mcore_little_vec) tb="$tb elf32-mcore.lo elf32.lo $elf" ;;
bfd_elf32_mn10200_vec) tb="$tb elf-m10200.lo elf32.lo $elf" ;;
bfd_elf32_mn10300_vec) tb="$tb elf-m10300.lo elf32.lo $elf" ;;
- bfd_elf32_ms1_vec) tb="$tb elf32-mt.lo elf32.lo $elf" ;;
+ bfd_elf32_mt_vec) tb="$tb elf32-mt.lo elf32.lo $elf" ;;
bfd_elf32_msp430_vec) tb="$tb elf32-msp430.lo elf32.lo $elf" ;;
bfd_elf32_nbigmips_vec) tb="$tb elfn32-mips.lo elfxx-mips.lo elf32.lo $elf ecofflink.lo"; target_size=64 ;;
bfd_elf32_nlittlemips_vec) tb="$tb elfn32-mips.lo elfxx-mips.lo elf32.lo $elf ecofflink.lo"; target_size=64 ;;
# Target architecture .o files.
# A couple of CPUs use shorter file names to avoid problems on DOS
# filesystems.
-ta=`echo $selarchs | sed -e s/_ms1_/_mt_/ -e s/bfd_/cpu-/g -e s/_arch/.lo/g -e s/mn10200/m10200/ -e s/mn10300/m10300/`
+ta=`echo $selarchs | sed -e s/bfd_/cpu-/g -e s/_arch/.lo/g -e s/mn10200/m10200/ -e s/mn10300/m10300/`
# Weed out duplicate .o files.
f=""
bfd_elf32_mcore_little_vec) tb="$tb elf32-mcore.lo elf32.lo $elf" ;;
bfd_elf32_mn10200_vec) tb="$tb elf-m10200.lo elf32.lo $elf" ;;
bfd_elf32_mn10300_vec) tb="$tb elf-m10300.lo elf32.lo $elf" ;;
- bfd_elf32_ms1_vec) tb="$tb elf32-mt.lo elf32.lo $elf" ;;
+ bfd_elf32_mt_vec) tb="$tb elf32-mt.lo elf32.lo $elf" ;;
bfd_elf32_msp430_vec) tb="$tb elf32-msp430.lo elf32.lo $elf" ;;
bfd_elf32_nbigmips_vec) tb="$tb elfn32-mips.lo elfxx-mips.lo elf32.lo $elf ecofflink.lo"; target_size=64 ;;
bfd_elf32_nlittlemips_vec) tb="$tb elfn32-mips.lo elfxx-mips.lo elf32.lo $elf ecofflink.lo"; target_size=64 ;;
# Target architecture .o files.
# A couple of CPUs use shorter file names to avoid problems on DOS
# filesystems.
-ta=`echo $selarchs | sed -e s/_ms1_/_mt_/ -e s/bfd_/cpu-/g -e s/_arch/.lo/g -e s/mn10200/m10200/ -e s/mn10300/m10300/`
+ta=`echo $selarchs | sed -e s/bfd_/cpu-/g -e s/_arch/.lo/g -e s/mn10200/m10200/ -e s/mn10300/m10300/`
# Weed out duplicate .o files.
f=""
-/* BFD support for the Morpho Technologies MS1 processor.
+/* BFD support for the Morpho Technologies MT processor.
Copyright (C) 2001, 2002, 2005 Free Software Foundation, Inc.
This file is part of BFD, the Binary File Descriptor library.
32, /* Bits per word - not really true. */
32, /* Bits per address. */
8, /* Bits per byte. */
- bfd_arch_ms1, /* Architecture. */
+ bfd_arch_mt, /* Architecture. */
bfd_mach_mrisc2, /* Machine. */
- "ms1", /* Architecture name. */
+ "mt", /* Architecture name. */
"ms1-003", /* Printable name. */
1, /* Section align power. */
FALSE, /* The default ? */
32, /* Bits per word - not really true. */
32, /* Bits per address. */
8, /* Bits per byte. */
- bfd_arch_ms1, /* Architecture. */
+ bfd_arch_mt, /* Architecture. */
bfd_mach_ms2, /* Machine. */
- "ms1", /* Architecture name. */
+ "mt", /* Architecture name. */
"ms2", /* Printable name. */
1, /* Section align power. */
FALSE, /* The default ? */
},
};
-const bfd_arch_info_type bfd_ms1_arch =
+const bfd_arch_info_type bfd_mt_arch =
{
32, /* Bits per word - not really true. */
32, /* Bits per address. */
8, /* Bits per byte. */
- bfd_arch_ms1, /* Architecture. */
+ bfd_arch_mt, /* Architecture. */
bfd_mach_ms1, /* Machine. */
- "ms1", /* Architecture name. */
+ "mt", /* Architecture name. */
"ms1", /* Printable name. */
1, /* Section align power. */
TRUE, /* The default ? */
-/* Morpho Technologies MS1 specific support for 32-bit ELF
+/* Morpho Technologies MT specific support for 32-bit ELF
Copyright 2001, 2002, 2003, 2004, 2005
Free Software Foundation, Inc.
#include "elf/mt.h"
/* Prototypes. */
-static reloc_howto_type * ms1_reloc_type_lookup
+static reloc_howto_type * mt_reloc_type_lookup
(bfd *, bfd_reloc_code_real_type);
-static void ms1_info_to_howto_rela
+static void mt_info_to_howto_rela
(bfd *, arelent *, Elf_Internal_Rela *);
-static bfd_reloc_status_type ms1_elf_relocate_hi16
+static bfd_reloc_status_type mt_elf_relocate_hi16
(bfd *, Elf_Internal_Rela *, bfd_byte *, bfd_vma);
-static bfd_reloc_status_type ms1_final_link_relocate
+static bfd_reloc_status_type mt_final_link_relocate
(reloc_howto_type *, bfd *, asection *, bfd_byte *,
Elf_Internal_Rela *, bfd_vma);
-static bfd_boolean ms1_elf_relocate_section
+static bfd_boolean mt_elf_relocate_section
(bfd *, struct bfd_link_info *, bfd *, asection *, bfd_byte *,
Elf_Internal_Rela *, Elf_Internal_Sym *, asection **);
/* Relocation tables. */
-static reloc_howto_type ms1_elf_howto_table [] =
+static reloc_howto_type mt_elf_howto_table [] =
{
/* This reloc does nothing. */
- HOWTO (R_MS1_NONE, /* type */
+ HOWTO (R_MT_NONE, /* type */
0, /* rightshift */
2, /* size (0 = byte, 1 = short, 2 = long) */
32, /* bitsize */
0, /* bitpos */
complain_overflow_dont, /* complain_on_overflow */
bfd_elf_generic_reloc, /* special_function */
- "R_MS1_NONE", /* name */
+ "R_MT_NONE", /* name */
FALSE, /* partial_inplace */
0 , /* src_mask */
0, /* dst_mask */
FALSE), /* pcrel_offset */
/* A 16 bit absolute relocation. */
- HOWTO (R_MS1_16, /* type */
+ HOWTO (R_MT_16, /* type */
0, /* rightshift */
2, /* size (0 = byte, 1 = short, 2 = long) */
16, /* bitsize */
0, /* bitpos */
complain_overflow_dont, /* complain_on_overflow */
bfd_elf_generic_reloc, /* special_function */
- "R_MS1_16", /* name */
+ "R_MT_16", /* name */
FALSE, /* partial_inplace */
0 , /* src_mask */
0xffff, /* dst_mask */
FALSE), /* pcrel_offset */
/* A 32 bit absolute relocation. */
- HOWTO (R_MS1_32, /* type */
+ HOWTO (R_MT_32, /* type */
0, /* rightshift */
2, /* size (0 = byte, 1 = short, 2 = long) */
32, /* bitsize */
0, /* bitpos */
complain_overflow_dont, /* complain_on_overflow */
bfd_elf_generic_reloc, /* special_function */
- "R_MS1_32", /* name */
+ "R_MT_32", /* name */
FALSE, /* partial_inplace */
0 , /* src_mask */
0xffffffff, /* dst_mask */
FALSE), /* pcrel_offset */
/* A 32 bit pc-relative relocation. */
- HOWTO (R_MS1_32_PCREL, /* type */
+ HOWTO (R_MT_32_PCREL, /* type */
0, /* rightshift */
2, /* size (0 = byte, 1 = short, 2 = long) */
32, /* bitsize */
0, /* bitpos */
complain_overflow_dont, /* complain_on_overflow */
bfd_elf_generic_reloc, /* special_function */
- "R_MS1_32_PCREL", /* name */
+ "R_MT_32_PCREL", /* name */
FALSE, /* partial_inplace */
0 , /* src_mask */
0xffffffff, /* dst_mask */
TRUE), /* pcrel_offset */
/* A 16 bit pc-relative relocation. */
- HOWTO (R_MS1_PC16, /* type */
+ HOWTO (R_MT_PC16, /* type */
0, /* rightshift */
2, /* size (0 = byte, 1 = short, 2 = long) */
16, /* bitsize */
0, /* bitpos */
complain_overflow_signed, /* complain_on_overflow */
bfd_elf_generic_reloc, /* special_function */
- "R_MS1_PC16", /* name */
+ "R_MT_PC16", /* name */
FALSE, /* partial_inplace */
0, /* src_mask */
0xffff, /* dst_mask */
TRUE), /* pcrel_offset */
/* high 16 bits of symbol value. */
- HOWTO (R_MS1_HI16, /* type */
+ HOWTO (R_MT_HI16, /* type */
0, /* rightshift */
2, /* size (0 = byte, 1 = short, 2 = long) */
16, /* bitsize */
0, /* bitpos */
complain_overflow_dont, /* complain_on_overflow */
bfd_elf_generic_reloc, /* special_function */
- "R_MS1_HI16", /* name */
+ "R_MT_HI16", /* name */
FALSE, /* partial_inplace */
0xffff0000, /* src_mask */
0xffff0000, /* dst_mask */
FALSE), /* pcrel_offset */
/* Low 16 bits of symbol value. */
- HOWTO (R_MS1_LO16, /* type */
+ HOWTO (R_MT_LO16, /* type */
0, /* rightshift */
2, /* size (0 = byte, 1 = short, 2 = long) */
16, /* bitsize */
0, /* bitpos */
complain_overflow_dont, /* complain_on_overflow */
bfd_elf_generic_reloc, /* special_function */
- "R_MS1_LO16", /* name */
+ "R_MT_LO16", /* name */
FALSE, /* partial_inplace */
0xffff, /* src_mask */
0xffff, /* dst_mask */
FALSE), /* pcrel_offset */
};
-/* Map BFD reloc types to MS1 ELF reloc types. */
+/* Map BFD reloc types to MT ELF reloc types. */
static reloc_howto_type *
-ms1_reloc_type_lookup
+mt_reloc_type_lookup
(bfd * abfd ATTRIBUTE_UNUSED,
bfd_reloc_code_real_type code)
{
- /* Note that the ms1_elf_howto_table is indxed by the R_
+ /* Note that the mt_elf_howto_table is indxed by the R_
constants. Thus, the order that the howto records appear in the
table *must* match the order of the relocation types defined in
- include/elf/ms1.h. */
+ include/elf/mt.h. */
switch (code)
{
case BFD_RELOC_NONE:
- return &ms1_elf_howto_table[ (int) R_MS1_NONE];
+ return &mt_elf_howto_table[ (int) R_MT_NONE];
case BFD_RELOC_16:
- return &ms1_elf_howto_table[ (int) R_MS1_16];
+ return &mt_elf_howto_table[ (int) R_MT_16];
case BFD_RELOC_32:
- return &ms1_elf_howto_table[ (int) R_MS1_32];
+ return &mt_elf_howto_table[ (int) R_MT_32];
case BFD_RELOC_32_PCREL:
- return &ms1_elf_howto_table[ (int) R_MS1_32_PCREL];
+ return &mt_elf_howto_table[ (int) R_MT_32_PCREL];
case BFD_RELOC_16_PCREL:
- return &ms1_elf_howto_table[ (int) R_MS1_PC16];
+ return &mt_elf_howto_table[ (int) R_MT_PC16];
case BFD_RELOC_HI16:
- return &ms1_elf_howto_table[ (int) R_MS1_HI16];
+ return &mt_elf_howto_table[ (int) R_MT_HI16];
case BFD_RELOC_LO16:
- return &ms1_elf_howto_table[ (int) R_MS1_LO16];
+ return &mt_elf_howto_table[ (int) R_MT_LO16];
default:
/* Pacify gcc -Wall. */
}
bfd_reloc_status_type
-ms1_elf_relocate_hi16
+mt_elf_relocate_hi16
(bfd * input_bfd,
Elf_Internal_Rela * relhi,
bfd_byte * contents,
/* XXX: The following code is the result of a cut&paste. This unfortunate
practice is very widespread in the various target back-end files. */
-/* Set the howto pointer for a MS1 ELF reloc. */
+/* Set the howto pointer for a MT ELF reloc. */
static void
-ms1_info_to_howto_rela
+mt_info_to_howto_rela
(bfd * abfd ATTRIBUTE_UNUSED,
arelent * cache_ptr,
Elf_Internal_Rela * dst)
unsigned int r_type;
r_type = ELF32_R_TYPE (dst->r_info);
- cache_ptr->howto = & ms1_elf_howto_table [r_type];
+ cache_ptr->howto = & mt_elf_howto_table [r_type];
}
/* Perform a single relocation. By default we use the standard BFD
routines. */
static bfd_reloc_status_type
-ms1_final_link_relocate
+mt_final_link_relocate
(reloc_howto_type * howto,
bfd * input_bfd,
asection * input_section,
relocation, rel->r_addend);
}
-/* Relocate a MS1 ELF section.
+/* Relocate a MT ELF section.
There is some attempt to make this function usable for many architectures,
both USE_REL and USE_RELA ['twould be nice if such a critter existed],
if only to serve as a learning tool.
accordingly. */
static bfd_boolean
-ms1_elf_relocate_section
+mt_elf_relocate_section
(bfd * output_bfd ATTRIBUTE_UNUSED,
struct bfd_link_info * info,
bfd * input_bfd,
r_symndx = ELF32_R_SYM (rel->r_info);
/* This is a final link. */
- howto = ms1_elf_howto_table + ELF32_R_TYPE (rel->r_info);
+ howto = mt_elf_howto_table + ELF32_R_TYPE (rel->r_info);
h = NULL;
sym = NULL;
sec = NULL;
}
- /* Finally, the sole MS1-specific part. */
+ /* Finally, the sole MT-specific part. */
switch (r_type)
{
- case R_MS1_HI16:
- r = ms1_elf_relocate_hi16 (input_bfd, rel, contents, relocation);
+ case R_MT_HI16:
+ r = mt_elf_relocate_hi16 (input_bfd, rel, contents, relocation);
break;
default:
- r = ms1_final_link_relocate (howto, input_bfd, input_section,
+ r = mt_final_link_relocate (howto, input_bfd, input_section,
contents, rel, relocation);
break;
}
relocation. */
static asection *
-ms1_elf_gc_mark_hook
+mt_elf_gc_mark_hook
(asection * sec,
struct bfd_link_info * info ATTRIBUTE_UNUSED,
Elf_Internal_Rela * rel ATTRIBUTE_UNUSED,
removed. */
static bfd_boolean
-ms1_elf_gc_sweep_hook
+mt_elf_gc_sweep_hook
(bfd * abfd ATTRIBUTE_UNUSED,
struct bfd_link_info * info ATTRIBUTE_UNUSED,
asection * sec ATTRIBUTE_UNUSED,
virtual table relocs for gc. */
static bfd_boolean
-ms1_elf_check_relocs
+mt_elf_check_relocs
(bfd * abfd,
struct bfd_link_info * info,
asection * sec,
/* Return the MACH for an e_flags value. */
static int
-elf32_ms1_machine (bfd *abfd)
+elf32_mt_machine (bfd *abfd)
{
- switch (elf_elfheader (abfd)->e_flags & EF_MS1_CPU_MASK)
+ switch (elf_elfheader (abfd)->e_flags & EF_MT_CPU_MASK)
{
- case EF_MS1_CPU_MRISC: return bfd_mach_ms1;
- case EF_MS1_CPU_MRISC2: return bfd_mach_mrisc2;
- case EF_MS1_CPU_MS2: return bfd_mach_ms2;
+ case EF_MT_CPU_MRISC: return bfd_mach_ms1;
+ case EF_MT_CPU_MRISC2: return bfd_mach_mrisc2;
+ case EF_MT_CPU_MS2: return bfd_mach_ms2;
}
return bfd_mach_ms1;
}
static bfd_boolean
-ms1_elf_object_p (bfd * abfd)
+mt_elf_object_p (bfd * abfd)
{
- bfd_default_set_arch_mach (abfd, bfd_arch_ms1, elf32_ms1_machine (abfd));
+ bfd_default_set_arch_mach (abfd, bfd_arch_mt, elf32_mt_machine (abfd));
return TRUE;
}
/* Function to set the ELF flag bits. */
static bfd_boolean
-ms1_elf_set_private_flags (bfd * abfd,
+mt_elf_set_private_flags (bfd * abfd,
flagword flags)
{
elf_elfheader (abfd)->e_flags = flags;
}
static bfd_boolean
-ms1_elf_copy_private_bfd_data (bfd * ibfd, bfd * obfd)
+mt_elf_copy_private_bfd_data (bfd * ibfd, bfd * obfd)
{
if (bfd_get_flavour (ibfd) != bfd_target_elf_flavour
|| bfd_get_flavour (obfd) != bfd_target_elf_flavour)
object file when linking. */
static bfd_boolean
-ms1_elf_merge_private_bfd_data (bfd * ibfd, bfd * obfd)
+mt_elf_merge_private_bfd_data (bfd * ibfd, bfd * obfd)
{
flagword old_flags, new_flags;
bfd_boolean error = FALSE;
if (_bfd_generic_verify_endian_match (ibfd, obfd) == FALSE)
return FALSE;
- /* If they're not both ms1, then merging is meaningless, so just
+ /* If they're not both mt, then merging is meaningless, so just
don't do it. */
- if (strcmp (ibfd->arch_info->arch_name, "ms1") != 0)
+ if (strcmp (ibfd->arch_info->arch_name, "mt") != 0)
return TRUE;
- if (strcmp (obfd->arch_info->arch_name, "ms1") != 0)
+ if (strcmp (obfd->arch_info->arch_name, "mt") != 0)
return TRUE;
new_flags = elf_elfheader (ibfd)->e_flags;
old_flags = new_flags;
elf_flags_init (obfd) = TRUE;
}
- else if ((new_flags & EF_MS1_CPU_MASK) != (old_flags & EF_MS1_CPU_MASK))
+ else if ((new_flags & EF_MT_CPU_MASK) != (old_flags & EF_MT_CPU_MASK))
{
/* CPU has changed. This is invalid, because MRISC, MRISC2 and
MS2 are not subsets of each other. */
mixing breaks the build. So we allow merging and use the
greater CPU value. This is of course unsafe. */
error = 0;
- if ((new_flags & EF_MS1_CPU_MASK) > (old_flags & EF_MS1_CPU_MASK))
- old_flags = ((old_flags & ~EF_MS1_CPU_MASK)
- | (new_flags & EF_MS1_CPU_MASK));
+ if ((new_flags & EF_MT_CPU_MASK) > (old_flags & EF_MT_CPU_MASK))
+ old_flags = ((old_flags & ~EF_MT_CPU_MASK)
+ | (new_flags & EF_MT_CPU_MASK));
}
if (!error)
{
}
static bfd_boolean
-ms1_elf_print_private_bfd_data (bfd * abfd, void * ptr)
+mt_elf_print_private_bfd_data (bfd * abfd, void * ptr)
{
FILE * file = (FILE *) ptr;
flagword flags;
flags = elf_elfheader (abfd)->e_flags;
fprintf (file, _("private flags = 0x%lx:"), (long)flags);
- switch (flags & EF_MS1_CPU_MASK)
+ switch (flags & EF_MT_CPU_MASK)
{
default:
- case EF_MS1_CPU_MRISC: fprintf (file, " ms1-16-002"); break;
- case EF_MS1_CPU_MRISC2: fprintf (file, " ms1-16-003"); break;
- case EF_MS1_CPU_MS2: fprintf (file, " ms2"); break;
+ case EF_MT_CPU_MRISC: fprintf (file, " ms1-16-002"); break;
+ case EF_MT_CPU_MRISC2: fprintf (file, " ms1-16-003"); break;
+ case EF_MT_CPU_MS2: fprintf (file, " ms2"); break;
}
fputc ('\n', file);
}
\f
-#define TARGET_BIG_SYM bfd_elf32_ms1_vec
-#define TARGET_BIG_NAME "elf32-ms1"
+#define TARGET_BIG_SYM bfd_elf32_mt_vec
+#define TARGET_BIG_NAME "elf32-mt"
-#define ELF_ARCH bfd_arch_ms1
-#define ELF_MACHINE_CODE EM_MS1
-#define ELF_MAXPAGESIZE 1 /* No pages on the MS1. */
+#define ELF_ARCH bfd_arch_mt
+#define ELF_MACHINE_CODE EM_MT
+#define ELF_MAXPAGESIZE 1 /* No pages on the MT. */
#define elf_info_to_howto_rel NULL
-#define elf_info_to_howto ms1_info_to_howto_rela
+#define elf_info_to_howto mt_info_to_howto_rela
-#define elf_backend_relocate_section ms1_elf_relocate_section
+#define elf_backend_relocate_section mt_elf_relocate_section
-#define bfd_elf32_bfd_reloc_type_lookup ms1_reloc_type_lookup
+#define bfd_elf32_bfd_reloc_type_lookup mt_reloc_type_lookup
-#define elf_backend_gc_mark_hook ms1_elf_gc_mark_hook
-#define elf_backend_gc_sweep_hook ms1_elf_gc_sweep_hook
-#define elf_backend_check_relocs ms1_elf_check_relocs
-#define elf_backend_object_p ms1_elf_object_p
+#define elf_backend_gc_mark_hook mt_elf_gc_mark_hook
+#define elf_backend_gc_sweep_hook mt_elf_gc_sweep_hook
+#define elf_backend_check_relocs mt_elf_check_relocs
+#define elf_backend_object_p mt_elf_object_p
#define elf_backend_rela_normal 1
#define elf_backend_can_gc_sections 1
-#define bfd_elf32_bfd_set_private_flags ms1_elf_set_private_flags
-#define bfd_elf32_bfd_copy_private_bfd_data ms1_elf_copy_private_bfd_data
-#define bfd_elf32_bfd_merge_private_bfd_data ms1_elf_merge_private_bfd_data
-#define bfd_elf32_bfd_print_private_bfd_data ms1_elf_print_private_bfd_data
+#define bfd_elf32_bfd_set_private_flags mt_elf_set_private_flags
+#define bfd_elf32_bfd_copy_private_bfd_data mt_elf_copy_private_bfd_data
+#define bfd_elf32_bfd_merge_private_bfd_data mt_elf_merge_private_bfd_data
+#define bfd_elf32_bfd_print_private_bfd_data mt_elf_print_private_bfd_data
#include "elf32-target.h"
"BFD_RELOC_VAX_GLOB_DAT",
"BFD_RELOC_VAX_JMP_SLOT",
"BFD_RELOC_VAX_RELATIVE",
- "BFD_RELOC_MS1_PC16",
- "BFD_RELOC_MS1_HI16",
- "BFD_RELOC_MS1_LO16",
- "BFD_RELOC_MS1_GNU_VTINHERIT",
- "BFD_RELOC_MS1_GNU_VTENTRY",
- "BFD_RELOC_MS1_PCINSN8",
+ "BFD_RELOC_MT_PC16",
+ "BFD_RELOC_MT_HI16",
+ "BFD_RELOC_MT_LO16",
+ "BFD_RELOC_MT_GNU_VTINHERIT",
+ "BFD_RELOC_MT_GNU_VTENTRY",
+ "BFD_RELOC_MT_PCINSN8",
"BFD_RELOC_MSP430_10_PCREL",
"BFD_RELOC_MSP430_16_PCREL",
"BFD_RELOC_MSP430_16",
Relocations used by VAX ELF.
ENUM
- BFD_RELOC_MS1_PC16
+ BFD_RELOC_MT_PC16
ENUMDOC
- Morpho MS1 - 16 bit immediate relocation.
+ Morpho MT - 16 bit immediate relocation.
ENUM
- BFD_RELOC_MS1_HI16
+ BFD_RELOC_MT_HI16
ENUMDOC
- Morpho MS1 - Hi 16 bits of an address.
+ Morpho MT - Hi 16 bits of an address.
ENUM
- BFD_RELOC_MS1_LO16
+ BFD_RELOC_MT_LO16
ENUMDOC
- Morpho MS1 - Low 16 bits of an address.
+ Morpho MT - Low 16 bits of an address.
ENUM
- BFD_RELOC_MS1_GNU_VTINHERIT
+ BFD_RELOC_MT_GNU_VTINHERIT
ENUMDOC
- Morpho MS1 - Used to tell the linker which vtable entries are used.
+ Morpho MT - Used to tell the linker which vtable entries are used.
ENUM
- BFD_RELOC_MS1_GNU_VTENTRY
+ BFD_RELOC_MT_GNU_VTENTRY
ENUMDOC
- Morpho MS1 - Used to tell the linker which vtable entries are used.
+ Morpho MT - Used to tell the linker which vtable entries are used.
ENUM
- BFD_RELOC_MS1_PCINSN8
+ BFD_RELOC_MT_PCINSN8
ENUMDOC
- Morpho MS1 - 8 bit immediate relocation.
+ Morpho MT - 8 bit immediate relocation.
ENUM
BFD_RELOC_MSP430_10_PCREL
extern const bfd_target bfd_elf32_mcore_little_vec;
extern const bfd_target bfd_elf32_mn10200_vec;
extern const bfd_target bfd_elf32_mn10300_vec;
-extern const bfd_target bfd_elf32_ms1_vec;
+extern const bfd_target bfd_elf32_mt_vec;
extern const bfd_target bfd_elf32_msp430_vec;
extern const bfd_target bfd_elf32_nbigmips_vec;
extern const bfd_target bfd_elf32_nlittlemips_vec;
&bfd_elf32_mcore_little_vec,
&bfd_elf32_mn10200_vec,
&bfd_elf32_mn10300_vec,
- &bfd_elf32_ms1_vec,
+ &bfd_elf32_mt_vec,
&bfd_elf32_msp430_vec,
#ifdef BFD64
&bfd_elf32_nbigmips_vec,
+2005-12-16 Nathan Sidwell <nathan@codesourcery.com>
+
+ Second part of ms1 to mt renaming.
+ * readelf.c (guess_is_rela): Use EM_MT.
+ (dump_relocations, get_machine_name): Adjust.
+
2005-12-12 Nathan Sidwell <nathan@codesourcery.com>
* Makefile.am: Replace ms1 files with mt files.
case EM_XTENSA_OLD:
case EM_M32R:
case EM_M32C:
- case EM_MS1:
+ case EM_MT:
case EM_BLACKFIN:
return TRUE;
rtype = elf_m32c_reloc_type (type);
break;
- case EM_MS1:
- rtype = elf_ms1_reloc_type (type);
+ case EM_MT:
+ rtype = elf_mt_reloc_type (type);
break;
case EM_BLACKFIN:
case EM_XTENSA_OLD:
case EM_XTENSA: return "Tensilica Xtensa Processor";
case EM_M32C: return "Renesas M32c";
- case EM_MS1: return "Morpho Techologies MS1 processor";
+ case EM_MT: return "Morpho Techologies MT processor";
default:
snprintf (buff, sizeof (buff), _("<unknown>: %x"), e_machine);
return buff;
+2005-12-16 Nathan Sidwell <nathan@codesourcery.com>
+
+ Second part of ms1 to mt renaming.
+ * mt.cpu (define-arch, define-isa): Set name to mt.
+ (define-mach): Adjust.
+ * mt.opc (CGEN_ASM_HASH): Update.
+ (mt_asm_hash, mt_cgen_insn_supported): Renamed.
+ (parse_loopsize, parse_imm16): Adjust.
+
2005-12-13 DJ Delorie <dj@redhat.com>
* m32c.cpu (jsri): Fix order so register names aren't treated as
-; Morpho Technologies mRISC CPU description. -*- Scheme -*-
+; Morpho Technologies MT Arch description. -*- Scheme -*-
; Copyright 2001 Free Software Foundation, Inc.
;
; Contributed by Red Hat Inc; developed under contract from
; define-arch must appear first
(define-arch
- (name ms1) ; name of cpu family
+ (name mt) ; name of cpu family
(comment "Morpho Technologies mRISC family")
(default-alignment aligned)
(insn-lsb0? #t)
(machs ms1 ms1-003 ms2)
- (isas ms1)
+ (isas mt)
)
; Instruction set parameters.
(define-isa
- (name ms1)
- (comment "Morpho Technologies mrisc ISA")
+ (name mt)
+ (comment "Morpho Technologies MT ISA")
(default-insn-word-bitsize 32)
(default-insn-bitsize 32)
(base-insn-bitsize 32)
(name ms1)
(comment "Morpho Technologies mrisc")
(cpu ms1bf)
- (isas ms1)
+ (isas mt)
)
(define-mach
(name ms1-003)
(comment "Morpho Technologies mrisc")
(cpu ms1-003bf)
- (isas ms1)
+ (isas mt)
)
(define-mach
(name ms2)
(comment "Morpho Technologies ms2")
(cpu ms2bf)
- (isas ms1)
+ (isas mt)
)
\f
#define CGEN_DIS_HASH(buf, value) (((* (unsigned char *) (buf)) >> 5) % CGEN_DIS_HASH_SIZE)
#define CGEN_ASM_HASH_SIZE 127
-#define CGEN_ASM_HASH(insn) ms1_asm_hash (insn)
+#define CGEN_ASM_HASH(insn) mt_asm_hash (insn)
-extern unsigned int ms1_asm_hash (const char *);
+extern unsigned int mt_asm_hash (const char *);
-extern int ms1_cgen_insn_supported (CGEN_CPU_DESC, const CGEN_INSN *);
+extern int mt_cgen_insn_supported (CGEN_CPU_DESC, const CGEN_INSN *);
\f
/* -- opc.c */
/* Special check to ensure that instruction exists for given machine. */
int
-ms1_cgen_insn_supported (CGEN_CPU_DESC cd,
- const CGEN_INSN *insn)
+mt_cgen_insn_supported (CGEN_CPU_DESC cd, const CGEN_INSN *insn)
{
int machs = CGEN_INSN_ATTR_VALUE (insn, CGEN_INSN_MACH);
/* A better hash function for instruction mnemonics. */
unsigned int
-ms1_asm_hash (const char* insn)
+mt_asm_hash (const char* insn)
{
unsigned int hash;
const char* m = insn;
bfd_vma value;
/* Is it a control transfer instructions? */
- if (opindex == (CGEN_OPERAND_TYPE) MS1_OPERAND_LOOPSIZE)
+ if (opindex == (CGEN_OPERAND_TYPE) MT_OPERAND_LOOPSIZE)
{
- code = BFD_RELOC_MS1_PCINSN8;
+ code = BFD_RELOC_MT_PCINSN8;
errmsg = cgen_parse_address (cd, strp, opindex, code,
& result_type, & value);
*valuep = value;
bfd_vma value;
/* Is it a control transfer instructions? */
- if (opindex == (CGEN_OPERAND_TYPE) MS1_OPERAND_IMM16O)
+ if (opindex == (CGEN_OPERAND_TYPE) MT_OPERAND_IMM16O)
{
code = BFD_RELOC_16_PCREL;
errmsg = cgen_parse_address (cd, strp, opindex, code,
/* If it's not a control transfer instruction, then
we have to check for %OP relocating operators. */
- if (opindex == (CGEN_OPERAND_TYPE) MS1_OPERAND_IMM16L)
+ if (opindex == (CGEN_OPERAND_TYPE) MT_OPERAND_IMM16L)
;
else if (strncmp (*strp, "%hi16", 5) == 0)
{
{
/* Parse hex values like 0xffff as unsigned, and sign extend
them manually. */
- int parse_signed = (opindex == (CGEN_OPERAND_TYPE)MS1_OPERAND_IMM16);
+ int parse_signed = (opindex == (CGEN_OPERAND_TYPE)MT_OPERAND_IMM16);
if ((*strp)[0] == '0'
&& ((*strp)[1] == 'x' || (*strp)[1] == 'X'))
}
else
{
- /* MS1_OPERAND_IMM16Z. Parse as an unsigned integer. */
+ /* MT_OPERAND_IMM16Z. Parse as an unsigned integer. */
errmsg = cgen_parse_unsigned_integer (cd, strp, opindex, (unsigned long *) valuep);
- if (opindex == (CGEN_OPERAND_TYPE) MS1_OPERAND_IMM16
+ if (opindex == (CGEN_OPERAND_TYPE) MT_OPERAND_IMM16
&& *valuep >= 0x8000
&& *valuep <= 0xffff)
*valuep -= 0x10000;
+2005-12-16 Nathan Sidwell <nathan@codesourcery.com>
+
+ Second part of ms1 to mt renaming.
+ * configure: Rebuilt.
+ * configure.in (mt): Remove special case.
+ * config/tc-mt.c (opcodes/mt-desc.h, opcodes/mt-opc.h): Change
+ #includes.
+ (mt_insn, mt_mach, mt_mach_bitmask, mt_flags, mt_architectures):
+ Rename, adjust.
+ (md_parse_option, md_show_usage, md_begin, md_assemble,
+ md_cgen_lookup_reloc, md_atof): Adjust.
+ (mt_force_relocation, mt_apply_fix, mt_fix_adjustable): Rename, adjust.
+ * config/tc-mt.h (TC_MT): Rename.
+ (LISTING_HEADER, TARGET_ARCH, TARGET_FORMAT): Adjust.
+ (md_apply_fix): Adjust.
+ (mt_apply_fix, mt_fix_adjustable, mt_force_relocation): Rename.
+ (TC_FORCE_RELOCATION, tc_fix_adjustable): Adjust.
+
2005-12-14 Jan Beulich <jbeulich@novell.com>
* config/tc-i386.c (add_prefix): More fine-grained handling of
-/* tc-ms1.c -- Assembler for the Morpho Technologies ms-I.
+/* tc-mt.c -- Assembler for the Morpho Technologies mt .
Copyright (C) 2005 Free Software Foundation.
This file is part of GAS, the GNU Assembler.
#include "dwarf2dbg.h"
#include "subsegs.h"
#include "symcat.h"
-#include "opcodes/ms1-desc.h"
-#include "opcodes/ms1-opc.h"
+#include "opcodes/mt-desc.h"
+#include "opcodes/mt-opc.h"
#include "cgen.h"
#include "elf/common.h"
#include "elf/mt.h"
fixS * fixups [GAS_CGEN_MAX_FIXUPS];
int indices [MAX_OPERAND_INSTANCES];
}
-ms1_insn;
+mt_insn;
const char comment_chars[] = ";";
const char * md_shortopts = "";
/* Mach selected from command line. */
-static int ms1_mach = bfd_mach_ms1;
-static unsigned ms1_mach_bitmask = 1 << MACH_MS1;
+static int mt_mach = bfd_mach_ms1;
+static unsigned mt_mach_bitmask = 1 << MACH_MS1;
/* Flags to set in the elf header */
-static flagword ms1_flags = EF_MS1_CPU_MRISC;
+static flagword mt_flags = EF_MT_CPU_MRISC;
/* The architecture to use. */
-enum ms1_architectures
+enum mt_architectures
{
ms1_64_001,
ms1_16_002,
ms2
};
-/* MS1 architecture we are using for this output file. */
-static enum ms1_architectures ms1_arch = ms1_64_001;
+/* MT architecture we are using for this output file. */
+static enum mt_architectures mt_arch = ms1_64_001;
int
md_parse_option (int c ATTRIBUTE_UNUSED, char * arg)
case OPTION_MARCH:
if (strcasecmp (arg, "MS1-64-001") == 0)
{
- ms1_flags = (ms1_flags & ~EF_MS1_CPU_MASK) | EF_MS1_CPU_MRISC;
- ms1_mach = bfd_mach_ms1;
- ms1_mach_bitmask = 1 << MACH_MS1;
- ms1_arch = ms1_64_001;
+ mt_flags = (mt_flags & ~EF_MT_CPU_MASK) | EF_MT_CPU_MRISC;
+ mt_mach = bfd_mach_ms1;
+ mt_mach_bitmask = 1 << MACH_MS1;
+ mt_arch = ms1_64_001;
}
else if (strcasecmp (arg, "MS1-16-002") == 0)
{
- ms1_flags = (ms1_flags & ~EF_MS1_CPU_MASK) | EF_MS1_CPU_MRISC;
- ms1_mach = bfd_mach_ms1;
- ms1_mach_bitmask = 1 << MACH_MS1;
- ms1_arch = ms1_16_002;
+ mt_flags = (mt_flags & ~EF_MT_CPU_MASK) | EF_MT_CPU_MRISC;
+ mt_mach = bfd_mach_ms1;
+ mt_mach_bitmask = 1 << MACH_MS1;
+ mt_arch = ms1_16_002;
}
else if (strcasecmp (arg, "MS1-16-003") == 0)
{
- ms1_flags = (ms1_flags & ~EF_MS1_CPU_MASK) | EF_MS1_CPU_MRISC2;
- ms1_mach = bfd_mach_mrisc2;
- ms1_mach_bitmask = 1 << MACH_MS1_003;
- ms1_arch = ms1_16_003;
+ mt_flags = (mt_flags & ~EF_MT_CPU_MASK) | EF_MT_CPU_MRISC2;
+ mt_mach = bfd_mach_mrisc2;
+ mt_mach_bitmask = 1 << MACH_MS1_003;
+ mt_arch = ms1_16_003;
}
else if (strcasecmp (arg, "MS2") == 0)
{
- ms1_flags = (ms1_flags & ~EF_MS1_CPU_MASK) | EF_MS1_CPU_MS2;
- ms1_mach = bfd_mach_mrisc2;
- ms1_mach_bitmask = 1 << MACH_MS2;
- ms1_arch = ms2;
+ mt_flags = (mt_flags & ~EF_MT_CPU_MASK) | EF_MT_CPU_MS2;
+ mt_mach = bfd_mach_mrisc2;
+ mt_mach_bitmask = 1 << MACH_MS2;
+ mt_arch = ms2;
}
case OPTION_NO_SCHED_REST:
no_scheduling_restrictions = 1;
void
md_show_usage (FILE * stream)
{
- fprintf (stream, _("MS1 specific command line options:\n"));
+ fprintf (stream, _("MT specific command line options:\n"));
fprintf (stream, _(" -march=ms1-64-001 allow ms1-64-001 instructions (default) \n"));
fprintf (stream, _(" -march=ms1-16-002 allow ms1-16-002 instructions \n"));
fprintf (stream, _(" -march=ms1-16-003 allow ms1-16-003 instructions \n"));
/* Initialize the `cgen' interface. */
/* Set the machine number and endian. */
- gas_cgen_cpu_desc = ms1_cgen_cpu_open (CGEN_CPU_OPEN_MACHS, ms1_mach_bitmask,
- CGEN_CPU_OPEN_ENDIAN,
- CGEN_ENDIAN_BIG,
- CGEN_CPU_OPEN_END);
- ms1_cgen_init_asm (gas_cgen_cpu_desc);
+ gas_cgen_cpu_desc = mt_cgen_cpu_open (CGEN_CPU_OPEN_MACHS, mt_mach_bitmask,
+ CGEN_CPU_OPEN_ENDIAN,
+ CGEN_ENDIAN_BIG,
+ CGEN_CPU_OPEN_END);
+ mt_cgen_init_asm (gas_cgen_cpu_desc);
/* This is a callback from cgen to gas to parse operands. */
cgen_set_parse_operand_fn (gas_cgen_cpu_desc, gas_cgen_parse_operand);
/* Set the ELF flags if desired. */
- if (ms1_flags)
- bfd_set_private_flags (stdoutput, ms1_flags);
+ if (mt_flags)
+ bfd_set_private_flags (stdoutput, mt_flags);
/* Set the machine type. */
- bfd_default_set_arch_mach (stdoutput, bfd_arch_ms1, ms1_mach);
+ bfd_default_set_arch_mach (stdoutput, bfd_arch_mt, mt_mach);
}
void
static int last_insn_was_branch_insn = 0;
static int last_insn_was_conditional_branch_insn = 0;
- ms1_insn insn;
+ mt_insn insn;
char * errmsg;
/* Initialize GAS's cgen interface for a new instruction. */
gas_cgen_init_parse ();
- insn.insn = ms1_cgen_assemble_insn
+ insn.insn = mt_cgen_assemble_insn
(gas_cgen_cpu_desc, str, & insn.fields, insn.buffer, & errmsg);
if (!insn.insn)
/* Detect consecutive Memory Accesses. */
if (last_insn_was_memory_access
&& CGEN_INSN_ATTR_VALUE (insn.insn, CGEN_INSN_MEMORY_ACCESS)
- && ms1_mach == ms1_64_001)
+ && mt_mach == ms1_64_001)
as_warn (_("instruction %s may not follow another memory access instruction."),
CGEN_INSN_NAME (insn.insn));
}
/* Detect JAL/RETI hazard */
- if (ms1_mach == ms2
+ if (mt_mach == ms2
&& CGEN_INSN_ATTR_VALUE (insn.insn, CGEN_INSN_JAL_HAZARD))
{
if ((CGEN_INSN_ATTR_VALUE (insn.insn, CGEN_INSN_USES_FRSR1)
&& !last_insn_in_noncond_delay_slot
&& (delayed_load_register != 0)
&& CGEN_INSN_ATTR_VALUE (insn.insn, CGEN_INSN_BR_INSN)
- && ms1_arch == ms1_64_001)
+ && mt_arch == ms1_64_001)
{
if (CGEN_INSN_ATTR_VALUE (insn.insn, CGEN_INSN_USES_FRSR1)
&& insn.fields.f_sr1 == delayed_load_register)
switch (operand->type)
{
- case MS1_OPERAND_IMM16O:
+ case MT_OPERAND_IMM16O:
result = BFD_RELOC_16_PCREL;
fixP->fx_pcrel = 1;
/* fixP->fx_no_overflow = 1; */
break;
- case MS1_OPERAND_IMM16:
- case MS1_OPERAND_IMM16Z:
+ case MT_OPERAND_IMM16:
+ case MT_OPERAND_IMM16Z:
/* These may have been processed at parse time. */
if (fixP->fx_cgen.opinfo != 0)
result = fixP->fx_cgen.opinfo;
fixP->fx_no_overflow = 1;
break;
- case MS1_OPERAND_LOOPSIZE:
- result = BFD_RELOC_MS1_PCINSN8;
+ case MT_OPERAND_LOOPSIZE:
+ result = BFD_RELOC_MT_PCINSN8;
fixP->fx_pcrel = 1;
/* Adjust for the delay slot, which is not part of the loop */
fixP->fx_offset -= 8;
* sizeP = prec * sizeof (LITTLENUM_TYPE);
/* This loops outputs the LITTLENUMs in REVERSE order;
- in accord with the ms1 endianness. */
+ in accord with the mt endianness. */
for (wordP = words; prec--;)
{
md_number_to_chars (litP, (valueT) (*wordP++), sizeof (LITTLENUM_TYPE));
/* See whether we need to force a relocation into the output file. */
int
-ms1_force_relocation (fixS * fixp ATTRIBUTE_UNUSED)
+mt_force_relocation (fixS * fixp ATTRIBUTE_UNUSED)
{
return 0;
}
void
-ms1_apply_fix (fixS *fixP, valueT *valueP, segT seg)
+mt_apply_fix (fixS *fixP, valueT *valueP, segT seg)
{
if ((fixP->fx_pcrel != 0) && (fixP->fx_r_type == BFD_RELOC_32))
fixP->fx_r_type = BFD_RELOC_32_PCREL;
}
bfd_boolean
-ms1_fix_adjustable (fixS * fixP)
+mt_fix_adjustable (fixS * fixP)
{
bfd_reloc_code_real_type reloc_type;
-/* tc-ms1.h -- Header file for tc-ms1.c.
+/* tc-mt.h -- Header file for tc-mt.c.
Copyright (C) 2005 Free Software Foundation, Inc.
This file is part of GAS, the GNU Assembler.
the Free Software Foundation, 59 Temple Place - Suite 330,
Boston, MA 02111-1307, USA. */
-#define TC_MS1
+#define TC_MT
-#define LISTING_HEADER "MS1 GAS "
+#define LISTING_HEADER "MT GAS "
/* The target BFD architecture. */
-#define TARGET_ARCH bfd_arch_ms1
+#define TARGET_ARCH bfd_arch_mt
-#define TARGET_FORMAT "elf32-ms1"
+#define TARGET_FORMAT "elf32-mt"
#define TARGET_BYTES_BIG_ENDIAN 1
/* We don't need to handle .word strangely. */
#define WORKING_DOT_WORD
-/* All ms1 instructions are multiples of 32 bits. */
+/* All mt instructions are multiples of 32 bits. */
#define DWARF2_LINE_MIN_INSN_LENGTH 4
#define LITERAL_PREFIXDOLLAR_HEX
#define LITERAL_PREFIXPERCENT_BIN
-#define md_apply_fix ms1_apply_fix
-extern void ms1_apply_fix (struct fix *, valueT *, segT);
+#define md_apply_fix mt_apply_fix
+extern void mt_apply_fix (struct fix *, valueT *, segT);
/* Call md_pcrel_from_section(), not md_pcrel_from(). */
#define MD_PCREL_FROM_SECTION(FIXP, SEC) md_pcrel_from_section (FIXP, SEC)
extern long md_pcrel_from_section (struct fix *, segT);
#define obj_fix_adjustable(fixP) iq2000_fix_adjustable (fixP)
-extern bfd_boolean ms1_fix_adjustable (struct fix *);
+extern bfd_boolean mt_fix_adjustable (struct fix *);
/* Values passed to md_apply_fix don't include the symbol value. */
#define MD_APPLY_SYM_VALUE(FIX) 0
#define md_operand(x) gas_cgen_md_operand (x)
extern void gas_cgen_md_operand (expressionS *);
-#define TC_FORCE_RELOCATION(fixp) ms1_force_relocation (fixp)
-extern int ms1_force_relocation (struct fix *);
+#define TC_FORCE_RELOCATION(fixp) mt_force_relocation (fixp)
+extern int mt_force_relocation (struct fix *);
-#define tc_fix_adjustable(fixP) ms1_fix_adjustable (fixP)
-extern bfd_boolean ms1_fix_adjustable (struct fix *);
+#define tc_fix_adjustable(fixP) mt_fix_adjustable (fixP)
+extern bfd_boolean mt_fix_adjustable (struct fix *);
cgen_cpu_prefix=""
if test $using_cgen = yes ; then
case ${target_cpu} in
- mt) cgen_cpu_prefix=ms1 ;;
*) cgen_cpu_prefix=${target_cpu} ;;
esac
cgen_cpu_prefix=""
if test $using_cgen = yes ; then
case ${target_cpu} in
- mt) cgen_cpu_prefix=ms1 ;;
*) cgen_cpu_prefix=${target_cpu} ;;
esac
AC_SUBST(cgen_cpu_prefix)
+2005-12-16 Nathan Sidwell <nathan@codesourcery.com>
+
+ Second part of ms1 to mt renaming.
+ * mt-tdep.c (mt_arch_constants, mt_gdb_regnums): Rename, adjust.
+ (mt_register_name, mt_register_type, mt_register_reggroup_p,
+ mt_return_value, mt_skip_prologue, mt_breapoint_from_pc,
+ mt_pseudo_register_read, mt_pseudo_register_write, mt_frame_align,
+ mt_registers_info, mt_push_dummy_call, mt_unwind_cache,
+ mt_frame_unwind_cache, mt_unwind_pc, mt_unwind_dummy_id,
+ mt_frame_this_id, mt_frame_prev_register, mt_frame_base_address,
+ mt_frame_unwind, mt_frame_sniffer, mt_frame_base, mt_gdbarch_init,
+ _initialize_mt_tdep): Rename & adjust.
+
2005-12-13 Mark Kettenis <kettenis@gnu.org>
* hppa-hpux-tdep.c (hppa_hpux_sigtramp_unwind_sniffer): Detect
-/* Target-dependent code for Morpho ms1 processor, for GDB.
+/* Target-dependent code for Morpho mt processor, for GDB.
Copyright 2005 Free Software Foundation, Inc.
#include "infcall.h"
#include "gdb_assert.h"
-enum ms1_arch_constants
+enum mt_arch_constants
{
- MS1_MAX_STRUCT_SIZE = 16
+ MT_MAX_STRUCT_SIZE = 16
};
-enum ms1_gdb_regnums
+enum mt_gdb_regnums
{
- MS1_R0_REGNUM, /* 32 bit regs. */
- MS1_R1_REGNUM,
- MS1_1ST_ARGREG = MS1_R1_REGNUM,
- MS1_R2_REGNUM,
- MS1_R3_REGNUM,
- MS1_R4_REGNUM,
- MS1_LAST_ARGREG = MS1_R4_REGNUM,
- MS1_R5_REGNUM,
- MS1_R6_REGNUM,
- MS1_R7_REGNUM,
- MS1_R8_REGNUM,
- MS1_R9_REGNUM,
- MS1_R10_REGNUM,
- MS1_R11_REGNUM,
- MS1_R12_REGNUM,
- MS1_FP_REGNUM = MS1_R12_REGNUM,
- MS1_R13_REGNUM,
- MS1_SP_REGNUM = MS1_R13_REGNUM,
- MS1_R14_REGNUM,
- MS1_RA_REGNUM = MS1_R14_REGNUM,
- MS1_R15_REGNUM,
- MS1_IRA_REGNUM = MS1_R15_REGNUM,
- MS1_PC_REGNUM,
+ MT_R0_REGNUM, /* 32 bit regs. */
+ MT_R1_REGNUM,
+ MT_1ST_ARGREG = MT_R1_REGNUM,
+ MT_R2_REGNUM,
+ MT_R3_REGNUM,
+ MT_R4_REGNUM,
+ MT_LAST_ARGREG = MT_R4_REGNUM,
+ MT_R5_REGNUM,
+ MT_R6_REGNUM,
+ MT_R7_REGNUM,
+ MT_R8_REGNUM,
+ MT_R9_REGNUM,
+ MT_R10_REGNUM,
+ MT_R11_REGNUM,
+ MT_R12_REGNUM,
+ MT_FP_REGNUM = MT_R12_REGNUM,
+ MT_R13_REGNUM,
+ MT_SP_REGNUM = MT_R13_REGNUM,
+ MT_R14_REGNUM,
+ MT_RA_REGNUM = MT_R14_REGNUM,
+ MT_R15_REGNUM,
+ MT_IRA_REGNUM = MT_R15_REGNUM,
+ MT_PC_REGNUM,
/* Interrupt Enable pseudo-register, exported by SID. */
- MS1_INT_ENABLE_REGNUM,
+ MT_INT_ENABLE_REGNUM,
/* End of CPU regs. */
- MS1_NUM_CPU_REGS,
+ MT_NUM_CPU_REGS,
/* Co-processor registers. */
- MS1_COPRO_REGNUM = MS1_NUM_CPU_REGS, /* 16 bit regs. */
- MS1_CPR0_REGNUM,
- MS1_CPR1_REGNUM,
- MS1_CPR2_REGNUM,
- MS1_CPR3_REGNUM,
- MS1_CPR4_REGNUM,
- MS1_CPR5_REGNUM,
- MS1_CPR6_REGNUM,
- MS1_CPR7_REGNUM,
- MS1_CPR8_REGNUM,
- MS1_CPR9_REGNUM,
- MS1_CPR10_REGNUM,
- MS1_CPR11_REGNUM,
- MS1_CPR12_REGNUM,
- MS1_CPR13_REGNUM,
- MS1_CPR14_REGNUM,
- MS1_CPR15_REGNUM,
- MS1_BYPA_REGNUM, /* 32 bit regs. */
- MS1_BYPB_REGNUM,
- MS1_BYPC_REGNUM,
- MS1_FLAG_REGNUM,
- MS1_CONTEXT_REGNUM, /* 38 bits (treat as array of
+ MT_COPRO_REGNUM = MT_NUM_CPU_REGS, /* 16 bit regs. */
+ MT_CPR0_REGNUM,
+ MT_CPR1_REGNUM,
+ MT_CPR2_REGNUM,
+ MT_CPR3_REGNUM,
+ MT_CPR4_REGNUM,
+ MT_CPR5_REGNUM,
+ MT_CPR6_REGNUM,
+ MT_CPR7_REGNUM,
+ MT_CPR8_REGNUM,
+ MT_CPR9_REGNUM,
+ MT_CPR10_REGNUM,
+ MT_CPR11_REGNUM,
+ MT_CPR12_REGNUM,
+ MT_CPR13_REGNUM,
+ MT_CPR14_REGNUM,
+ MT_CPR15_REGNUM,
+ MT_BYPA_REGNUM, /* 32 bit regs. */
+ MT_BYPB_REGNUM,
+ MT_BYPC_REGNUM,
+ MT_FLAG_REGNUM,
+ MT_CONTEXT_REGNUM, /* 38 bits (treat as array of
six bytes). */
- MS1_MAC_REGNUM, /* 32 bits. */
- MS1_Z1_REGNUM, /* 16 bits. */
- MS1_Z2_REGNUM, /* 16 bits. */
- MS1_ICHANNEL_REGNUM, /* 32 bits. */
- MS1_ISCRAMB_REGNUM, /* 32 bits. */
- MS1_QSCRAMB_REGNUM, /* 32 bits. */
- MS1_OUT_REGNUM, /* 16 bits. */
- MS1_EXMAC_REGNUM, /* 32 bits (8 used). */
- MS1_QCHANNEL_REGNUM, /* 32 bits. */
+ MT_MAC_REGNUM, /* 32 bits. */
+ MT_Z1_REGNUM, /* 16 bits. */
+ MT_Z2_REGNUM, /* 16 bits. */
+ MT_ICHANNEL_REGNUM, /* 32 bits. */
+ MT_ISCRAMB_REGNUM, /* 32 bits. */
+ MT_QSCRAMB_REGNUM, /* 32 bits. */
+ MT_OUT_REGNUM, /* 16 bits. */
+ MT_EXMAC_REGNUM, /* 32 bits (8 used). */
+ MT_QCHANNEL_REGNUM, /* 32 bits. */
/* Number of real registers. */
- MS1_NUM_REGS,
+ MT_NUM_REGS,
/* Pseudo-registers. */
- MS1_COPRO_PSEUDOREG_REGNUM = MS1_NUM_REGS,
- MS1_MAC_PSEUDOREG_REGNUM,
+ MT_COPRO_PSEUDOREG_REGNUM = MT_NUM_REGS,
+ MT_MAC_PSEUDOREG_REGNUM,
/* Two pseudo-regs ('coprocessor' and 'mac'). */
- MS1_NUM_PSEUDO_REGS = 2
+ MT_NUM_PSEUDO_REGS = 2
};
/* Return name of register number specified by REGNUM. */
static const char *
-ms1_register_name (int regnum)
+mt_register_name (int regnum)
{
static const char *const register_names[] = {
/* CPU regs. */
type of that register. */
static struct type *
-ms1_register_type (struct gdbarch *arch, int regnum)
+mt_register_type (struct gdbarch *arch, int regnum)
{
static struct type *void_func_ptr = NULL;
static struct type *void_ptr = NULL;
static struct type *copro_type;
- if (regnum >= 0 && regnum < MS1_NUM_REGS + MS1_NUM_PSEUDO_REGS)
+ if (regnum >= 0 && regnum < MT_NUM_REGS + MT_NUM_PSEUDO_REGS)
{
if (void_func_ptr == NULL)
{
}
switch (regnum)
{
- case MS1_PC_REGNUM:
- case MS1_RA_REGNUM:
- case MS1_IRA_REGNUM:
+ case MT_PC_REGNUM:
+ case MT_RA_REGNUM:
+ case MT_IRA_REGNUM:
return void_func_ptr;
- case MS1_SP_REGNUM:
- case MS1_FP_REGNUM:
+ case MT_SP_REGNUM:
+ case MT_FP_REGNUM:
return void_ptr;
- case MS1_INT_ENABLE_REGNUM:
- case MS1_ICHANNEL_REGNUM:
- case MS1_QCHANNEL_REGNUM:
- case MS1_ISCRAMB_REGNUM:
- case MS1_QSCRAMB_REGNUM:
+ case MT_INT_ENABLE_REGNUM:
+ case MT_ICHANNEL_REGNUM:
+ case MT_QCHANNEL_REGNUM:
+ case MT_ISCRAMB_REGNUM:
+ case MT_QSCRAMB_REGNUM:
return builtin_type_int32;
- case MS1_EXMAC_REGNUM:
- case MS1_MAC_REGNUM:
+ case MT_EXMAC_REGNUM:
+ case MT_MAC_REGNUM:
return builtin_type_uint32;
- case MS1_BYPA_REGNUM:
- case MS1_BYPB_REGNUM:
- case MS1_BYPC_REGNUM:
- case MS1_Z1_REGNUM:
- case MS1_Z2_REGNUM:
- case MS1_OUT_REGNUM:
+ case MT_BYPA_REGNUM:
+ case MT_BYPB_REGNUM:
+ case MT_BYPC_REGNUM:
+ case MT_Z1_REGNUM:
+ case MT_Z2_REGNUM:
+ case MT_OUT_REGNUM:
return builtin_type_int16;
- case MS1_CONTEXT_REGNUM:
+ case MT_CONTEXT_REGNUM:
return builtin_type_long_long;
- case MS1_COPRO_REGNUM:
- case MS1_COPRO_PSEUDOREG_REGNUM:
+ case MT_COPRO_REGNUM:
+ case MT_COPRO_PSEUDOREG_REGNUM:
return copro_type;
- case MS1_MAC_PSEUDOREG_REGNUM:
+ case MT_MAC_PSEUDOREG_REGNUM:
if (gdbarch_bfd_arch_info (arch)->mach == bfd_mach_mrisc2
|| gdbarch_bfd_arch_info (arch)->mach == bfd_mach_ms2)
return builtin_type_uint64;
else
return builtin_type_uint32;
- case MS1_FLAG_REGNUM:
+ case MT_FLAG_REGNUM:
return builtin_type_unsigned_char;
default:
- if (regnum >= MS1_R0_REGNUM && regnum <= MS1_R15_REGNUM)
+ if (regnum >= MT_R0_REGNUM && regnum <= MT_R15_REGNUM)
return builtin_type_int32;
- else if (regnum >= MS1_CPR0_REGNUM && regnum <= MS1_CPR15_REGNUM)
+ else if (regnum >= MT_CPR0_REGNUM && regnum <= MT_CPR15_REGNUM)
return builtin_type_int16;
}
}
internal_error (__FILE__, __LINE__,
- _("ms1_register_type: illegal register number %d"), regnum);
+ _("mt_register_type: illegal register number %d"), regnum);
}
/* Return true if register REGNUM is a member of the register group
specified by GROUP. */
static int
-ms1_register_reggroup_p (struct gdbarch *gdbarch, int regnum,
+mt_register_reggroup_p (struct gdbarch *gdbarch, int regnum,
struct reggroup *group)
{
/* Groups of registers that can be displayed via "info reg". */
if (group == all_reggroup)
return (regnum >= 0
- && regnum < MS1_NUM_REGS + MS1_NUM_PSEUDO_REGS
- && ms1_register_name (regnum)[0] != '\0');
+ && regnum < MT_NUM_REGS + MT_NUM_PSEUDO_REGS
+ && mt_register_name (regnum)[0] != '\0');
if (group == general_reggroup)
- return (regnum >= MS1_R0_REGNUM && regnum <= MS1_R15_REGNUM);
+ return (regnum >= MT_R0_REGNUM && regnum <= MT_R15_REGNUM);
if (group == float_reggroup)
return 0; /* No float regs. */
values. */
static enum return_value_convention
-ms1_return_value (struct gdbarch *gdbarch, struct type *type,
+mt_return_value (struct gdbarch *gdbarch, struct type *type,
struct regcache *regcache, gdb_byte *readbuf,
const gdb_byte *writebuf)
{
{
ULONGEST addr;
- regcache_cooked_read_unsigned (regcache, MS1_R11_REGNUM, &addr);
+ regcache_cooked_read_unsigned (regcache, MT_R11_REGNUM, &addr);
read_memory (addr, readbuf, TYPE_LENGTH (type));
}
{
ULONGEST addr;
- regcache_cooked_read_unsigned (regcache, MS1_R11_REGNUM, &addr);
+ regcache_cooked_read_unsigned (regcache, MT_R11_REGNUM, &addr);
write_memory (addr, writebuf, TYPE_LENGTH (type));
}
ULONGEST temp;
/* Return values of <= 4 bytes are returned in R11. */
- regcache_cooked_read_unsigned (regcache, MS1_R11_REGNUM, &temp);
+ regcache_cooked_read_unsigned (regcache, MT_R11_REGNUM, &temp);
store_unsigned_integer (readbuf, TYPE_LENGTH (type), temp);
}
memset (buf, 0, sizeof (buf));
memcpy (buf + sizeof (buf) - TYPE_LENGTH (type),
writebuf, TYPE_LENGTH (type));
- regcache_cooked_write (regcache, MS1_R11_REGNUM, buf);
+ regcache_cooked_write (regcache, MT_R11_REGNUM, buf);
}
else /* (TYPE_LENGTH (type) == 4 */
- regcache_cooked_write (regcache, MS1_R11_REGNUM, writebuf);
+ regcache_cooked_write (regcache, MT_R11_REGNUM, writebuf);
}
return RETURN_VALUE_REGISTER_CONVENTION;
call. */
static CORE_ADDR
-ms1_skip_prologue (CORE_ADDR pc)
+mt_skip_prologue (CORE_ADDR pc)
{
CORE_ADDR func_addr = 0, func_end = 0;
char *func_name;
The BP for ms2 is defined as 0x69000000 (illegal) */
static const gdb_byte *
-ms1_breakpoint_from_pc (CORE_ADDR *bp_addr, int *bp_size)
+mt_breakpoint_from_pc (CORE_ADDR *bp_addr, int *bp_size)
{
static gdb_byte ms1_breakpoint[] = { 0x68, 0, 0, 0 };
static gdb_byte ms2_breakpoint[] = { 0x69, 0, 0, 0 };
8-bit extended-MAC register). */
static void
-ms1_pseudo_register_read (struct gdbarch *gdbarch,
+mt_pseudo_register_read (struct gdbarch *gdbarch,
struct regcache *regcache, int regno, gdb_byte *buf)
{
switch (regno)
{
- case MS1_COPRO_REGNUM:
- case MS1_COPRO_PSEUDOREG_REGNUM:
- regcache_raw_read (regcache, MS1_COPRO_REGNUM, buf);
+ case MT_COPRO_REGNUM:
+ case MT_COPRO_PSEUDOREG_REGNUM:
+ regcache_raw_read (regcache, MT_COPRO_REGNUM, buf);
break;
- case MS1_MAC_REGNUM:
- case MS1_MAC_PSEUDOREG_REGNUM:
+ case MT_MAC_REGNUM:
+ case MT_MAC_PSEUDOREG_REGNUM:
if (gdbarch_bfd_arch_info (gdbarch)->mach == bfd_mach_mrisc2
|| gdbarch_bfd_arch_info (gdbarch)->mach == bfd_mach_ms2)
{
ULONGEST oldmac = 0, ext_mac = 0;
ULONGEST newmac;
- regcache_cooked_read_unsigned (regcache, MS1_MAC_REGNUM, &oldmac);
- regcache_cooked_read_unsigned (regcache, MS1_EXMAC_REGNUM, &ext_mac);
+ regcache_cooked_read_unsigned (regcache, MT_MAC_REGNUM, &oldmac);
+ regcache_cooked_read_unsigned (regcache, MT_EXMAC_REGNUM, &ext_mac);
newmac =
(oldmac & 0xffffffff) | ((long long) (ext_mac & 0xff) << 32);
store_signed_integer (buf, 8, newmac);
}
else
- regcache_raw_read (regcache, MS1_MAC_REGNUM, buf);
+ regcache_raw_read (regcache, MT_MAC_REGNUM, buf);
break;
default:
internal_error (__FILE__, __LINE__,
- _("ms1_pseudo_register_read: bad reg # (%d)"), regno);
+ _("mt_pseudo_register_read: bad reg # (%d)"), regno);
break;
}
}
/* Write the pseudo registers:
- Ms1 pseudo-registers are stored directly to the target. The
+ Mt pseudo-registers are stored directly to the target. The
'coprocessor' register is special, because when it is modified, all
the other coprocessor regs must be flushed from the reg cache. */
static void
-ms1_pseudo_register_write (struct gdbarch *gdbarch,
+mt_pseudo_register_write (struct gdbarch *gdbarch,
struct regcache *regcache,
int regno, const gdb_byte *buf)
{
switch (regno)
{
- case MS1_COPRO_REGNUM:
- case MS1_COPRO_PSEUDOREG_REGNUM:
- regcache_raw_write (regcache, MS1_COPRO_REGNUM, buf);
- for (i = MS1_NUM_CPU_REGS; i < MS1_NUM_REGS; i++)
+ case MT_COPRO_REGNUM:
+ case MT_COPRO_PSEUDOREG_REGNUM:
+ regcache_raw_write (regcache, MT_COPRO_REGNUM, buf);
+ for (i = MT_NUM_CPU_REGS; i < MT_NUM_REGS; i++)
set_register_cached (i, 0);
break;
- case MS1_MAC_REGNUM:
- case MS1_MAC_PSEUDOREG_REGNUM:
+ case MT_MAC_REGNUM:
+ case MT_MAC_PSEUDOREG_REGNUM:
if (gdbarch_bfd_arch_info (gdbarch)->mach == bfd_mach_mrisc2
|| gdbarch_bfd_arch_info (gdbarch)->mach == bfd_mach_ms2)
{
newmac = extract_unsigned_integer (buf, 8);
oldmac = newmac & 0xffffffff;
ext_mac = (newmac >> 32) & 0xff;
- regcache_cooked_write_unsigned (regcache, MS1_MAC_REGNUM, oldmac);
- regcache_cooked_write_unsigned (regcache, MS1_EXMAC_REGNUM, ext_mac);
+ regcache_cooked_write_unsigned (regcache, MT_MAC_REGNUM, oldmac);
+ regcache_cooked_write_unsigned (regcache, MT_EXMAC_REGNUM, ext_mac);
}
else
- regcache_raw_write (regcache, MS1_MAC_REGNUM, buf);
+ regcache_raw_write (regcache, MT_MAC_REGNUM, buf);
break;
default:
internal_error (__FILE__, __LINE__,
- _("ms1_pseudo_register_write: bad reg # (%d)"), regno);
+ _("mt_pseudo_register_write: bad reg # (%d)"), regno);
break;
}
}
static CORE_ADDR
-ms1_frame_align (struct gdbarch *gdbarch, CORE_ADDR sp)
+mt_frame_align (struct gdbarch *gdbarch, CORE_ADDR sp)
{
/* Register size is 4 bytes. */
return align_down (sp, 4);
of the registers. */
static void
-ms1_registers_info (struct gdbarch *gdbarch,
+mt_registers_info (struct gdbarch *gdbarch,
struct ui_file *file,
struct frame_info *frame, int regnum, int all)
{
{
int lim;
- lim = all ? MS1_NUM_REGS : MS1_NUM_CPU_REGS;
+ lim = all ? MT_NUM_REGS : MT_NUM_CPU_REGS;
for (regnum = 0; regnum < lim; regnum++)
{
/* Don't display the Qchannel register since it will be displayed
along with Ichannel. (See below.) */
- if (regnum == MS1_QCHANNEL_REGNUM)
+ if (regnum == MT_QCHANNEL_REGNUM)
continue;
- ms1_registers_info (gdbarch, file, frame, regnum, all);
+ mt_registers_info (gdbarch, file, frame, regnum, all);
/* Display the Qchannel register immediately after Ichannel. */
- if (regnum == MS1_ICHANNEL_REGNUM)
- ms1_registers_info (gdbarch, file, frame, MS1_QCHANNEL_REGNUM, all);
+ if (regnum == MT_ICHANNEL_REGNUM)
+ mt_registers_info (gdbarch, file, frame, MT_QCHANNEL_REGNUM, all);
}
}
else
{
- if (regnum == MS1_EXMAC_REGNUM)
+ if (regnum == MT_EXMAC_REGNUM)
return;
- else if (regnum == MS1_CONTEXT_REGNUM)
+ else if (regnum == MT_CONTEXT_REGNUM)
{
/* Special output handling for 38-bit context register. */
unsigned char *buff;
extract_unsigned_integer (buff, regsize));
fputs_filtered ("\n", file);
}
- else if (regnum == MS1_COPRO_REGNUM
- || regnum == MS1_COPRO_PSEUDOREG_REGNUM)
+ else if (regnum == MT_COPRO_REGNUM
+ || regnum == MT_COPRO_PSEUDOREG_REGNUM)
{
/* Special output handling for the 'coprocessor' register. */
gdb_byte *buf;
- buf = alloca (register_size (gdbarch, MS1_COPRO_REGNUM));
- frame_register_read (frame, MS1_COPRO_REGNUM, buf);
+ buf = alloca (register_size (gdbarch, MT_COPRO_REGNUM));
+ frame_register_read (frame, MT_COPRO_REGNUM, buf);
/* And print. */
- regnum = MS1_COPRO_PSEUDOREG_REGNUM;
+ regnum = MT_COPRO_PSEUDOREG_REGNUM;
fputs_filtered (REGISTER_NAME (regnum), file);
print_spaces_filtered (15 - strlen (REGISTER_NAME (regnum)), file);
val_print (register_type (gdbarch, regnum), buf,
0, 0, file, 0, 1, 0, Val_no_prettyprint);
fputs_filtered ("\n", file);
}
- else if (regnum == MS1_MAC_REGNUM || regnum == MS1_MAC_PSEUDOREG_REGNUM)
+ else if (regnum == MT_MAC_REGNUM || regnum == MT_MAC_PSEUDOREG_REGNUM)
{
ULONGEST oldmac, ext_mac, newmac;
gdb_byte buf[3 * sizeof (LONGEST)];
/* Get the two "real" mac registers. */
- frame_register_read (frame, MS1_MAC_REGNUM, buf);
+ frame_register_read (frame, MT_MAC_REGNUM, buf);
oldmac = extract_unsigned_integer
- (buf, register_size (gdbarch, MS1_MAC_REGNUM));
+ (buf, register_size (gdbarch, MT_MAC_REGNUM));
if (gdbarch_bfd_arch_info (gdbarch)->mach == bfd_mach_mrisc2
|| gdbarch_bfd_arch_info (gdbarch)->mach == bfd_mach_ms2)
{
- frame_register_read (frame, MS1_EXMAC_REGNUM, buf);
+ frame_register_read (frame, MT_EXMAC_REGNUM, buf);
ext_mac = extract_unsigned_integer
- (buf, register_size (gdbarch, MS1_EXMAC_REGNUM));
+ (buf, register_size (gdbarch, MT_EXMAC_REGNUM));
}
else
ext_mac = 0;
newmac = (oldmac & 0xffffffff) + ((ext_mac & 0xff) << 32);
/* And print. */
- regnum = MS1_MAC_PSEUDOREG_REGNUM;
+ regnum = MT_MAC_PSEUDOREG_REGNUM;
fputs_filtered (REGISTER_NAME (regnum), file);
print_spaces_filtered (15 - strlen (REGISTER_NAME (regnum)), file);
fputs_filtered ("0x", file);
Returns the updated (and aligned) stack pointer. */
static CORE_ADDR
-ms1_push_dummy_call (struct gdbarch *gdbarch, struct value *function,
+mt_push_dummy_call (struct gdbarch *gdbarch, struct value *function,
struct regcache *regcache, CORE_ADDR bp_addr,
int nargs, struct value **args, CORE_ADDR sp,
int struct_return, CORE_ADDR struct_addr)
{
#define wordsize 4
- gdb_byte buf[MS1_MAX_STRUCT_SIZE];
- int argreg = MS1_1ST_ARGREG;
+ gdb_byte buf[MT_MAX_STRUCT_SIZE];
+ int argreg = MT_1ST_ARGREG;
int split_param_len = 0;
int stack_dest = sp;
int slacklen;
int typelen;
int i, j;
- /* First handle however many args we can fit into MS1_1ST_ARGREG thru
- MS1_LAST_ARGREG. */
- for (i = 0; i < nargs && argreg <= MS1_LAST_ARGREG; i++)
+ /* First handle however many args we can fit into MT_1ST_ARGREG thru
+ MT_LAST_ARGREG. */
+ for (i = 0; i < nargs && argreg <= MT_LAST_ARGREG; i++)
{
const gdb_byte *val;
typelen = TYPE_LENGTH (value_type (args[i]));
val = value_contents (args[i]);
while (typelen > 0)
{
- if (argreg <= MS1_LAST_ARGREG)
+ if (argreg <= MT_LAST_ARGREG)
{
/* This word of the argument is passed in a register. */
regcache_cooked_write_unsigned (regcache, argreg++,
}
/* Set up return address (provided to us as bp_addr). */
- regcache_cooked_write_unsigned (regcache, MS1_RA_REGNUM, bp_addr);
+ regcache_cooked_write_unsigned (regcache, MT_RA_REGNUM, bp_addr);
/* Store struct return address, if given. */
if (struct_return && struct_addr != 0)
- regcache_cooked_write_unsigned (regcache, MS1_R11_REGNUM, struct_addr);
+ regcache_cooked_write_unsigned (regcache, MT_R11_REGNUM, struct_addr);
/* Set aside 16 bytes for the callee to save regs 1-4. */
stack_dest -= 16;
/* Update the stack pointer. */
- regcache_cooked_write_unsigned (regcache, MS1_SP_REGNUM, stack_dest);
+ regcache_cooked_write_unsigned (regcache, MT_SP_REGNUM, stack_dest);
/* And that should do it. Return the new stack pointer. */
return stack_dest;
/* The 'unwind_cache' data structure. */
-struct ms1_unwind_cache
+struct mt_unwind_cache
{
/* The previous frame's inner most stack address.
Used as this frame ID's stack_addr. */
/* Initialize an unwind_cache. Build up the saved_regs table etc. for
the frame. */
-static struct ms1_unwind_cache *
-ms1_frame_unwind_cache (struct frame_info *next_frame,
+static struct mt_unwind_cache *
+mt_frame_unwind_cache (struct frame_info *next_frame,
void **this_prologue_cache)
{
struct gdbarch *gdbarch;
- struct ms1_unwind_cache *info;
+ struct mt_unwind_cache *info;
CORE_ADDR next_addr, start_addr, end_addr, prologue_end_addr;
unsigned long instr, upper_half, delayed_store = 0;
int regnum, offset;
return (*this_prologue_cache);
gdbarch = get_frame_arch (next_frame);
- info = FRAME_OBSTACK_ZALLOC (struct ms1_unwind_cache);
+ info = FRAME_OBSTACK_ZALLOC (struct mt_unwind_cache);
(*this_prologue_cache) = info;
info->prev_sp = 0;
/* Grab the frame-relative values of SP and FP, needed below.
The frame_saved_register function will find them on the
stack or in the registers as appropriate. */
- frame_unwind_unsigned_register (next_frame, MS1_SP_REGNUM, &sp);
- frame_unwind_unsigned_register (next_frame, MS1_FP_REGNUM, &fp);
+ frame_unwind_unsigned_register (next_frame, MT_SP_REGNUM, &sp);
+ frame_unwind_unsigned_register (next_frame, MT_FP_REGNUM, &fp);
start_addr = frame_func_unwind (next_frame);
info->prev_sp = fp + info->framesize;
}
/* Save prev_sp in saved_regs as a value, not as an address. */
- trad_frame_set_value (info->saved_regs, MS1_SP_REGNUM, info->prev_sp);
+ trad_frame_set_value (info->saved_regs, MT_SP_REGNUM, info->prev_sp);
/* Now convert frame offsets to actual addresses (not offsets). */
- for (regnum = 0; regnum < MS1_NUM_REGS; regnum++)
+ for (regnum = 0; regnum < MT_NUM_REGS; regnum++)
if (trad_frame_addr_p (info->saved_regs, regnum))
info->saved_regs[regnum].addr += info->frame_base - info->framesize;
Since this is an unwind, do the reverse. Copy the location of RA
into PC (the address / regnum) so that a request for PC will be
converted into a request for the RA. */
- info->saved_regs[MS1_PC_REGNUM] = info->saved_regs[MS1_RA_REGNUM];
+ info->saved_regs[MT_PC_REGNUM] = info->saved_regs[MT_RA_REGNUM];
return info;
}
static CORE_ADDR
-ms1_unwind_pc (struct gdbarch *gdbarch, struct frame_info *next_frame)
+mt_unwind_pc (struct gdbarch *gdbarch, struct frame_info *next_frame)
{
ULONGEST pc;
- frame_unwind_unsigned_register (next_frame, MS1_PC_REGNUM, &pc);
+ frame_unwind_unsigned_register (next_frame, MT_PC_REGNUM, &pc);
return pc;
}
static CORE_ADDR
-ms1_unwind_sp (struct gdbarch *gdbarch, struct frame_info *next_frame)
+mt_unwind_sp (struct gdbarch *gdbarch, struct frame_info *next_frame)
{
ULONGEST sp;
- frame_unwind_unsigned_register (next_frame, MS1_SP_REGNUM, &sp);
+ frame_unwind_unsigned_register (next_frame, MT_SP_REGNUM, &sp);
return sp;
}
breakpoint. */
static struct frame_id
-ms1_unwind_dummy_id (struct gdbarch *gdbarch, struct frame_info *next_frame)
+mt_unwind_dummy_id (struct gdbarch *gdbarch, struct frame_info *next_frame)
{
- return frame_id_build (ms1_unwind_sp (gdbarch, next_frame),
+ return frame_id_build (mt_unwind_sp (gdbarch, next_frame),
frame_pc_unwind (next_frame));
}
frame. This will be used to create a new GDB frame struct. */
static void
-ms1_frame_this_id (struct frame_info *next_frame,
+mt_frame_this_id (struct frame_info *next_frame,
void **this_prologue_cache, struct frame_id *this_id)
{
- struct ms1_unwind_cache *info =
- ms1_frame_unwind_cache (next_frame, this_prologue_cache);
+ struct mt_unwind_cache *info =
+ mt_frame_unwind_cache (next_frame, this_prologue_cache);
if (!(info == NULL || info->prev_sp == 0))
{
}
static void
-ms1_frame_prev_register (struct frame_info *next_frame,
+mt_frame_prev_register (struct frame_info *next_frame,
void **this_prologue_cache,
int regnum, int *optimizedp,
enum lval_type *lvalp, CORE_ADDR *addrp,
int *realnump, gdb_byte *bufferp)
{
- struct ms1_unwind_cache *info =
- ms1_frame_unwind_cache (next_frame, this_prologue_cache);
+ struct mt_unwind_cache *info =
+ mt_frame_unwind_cache (next_frame, this_prologue_cache);
trad_frame_get_prev_register (next_frame, info->saved_regs, regnum,
optimizedp, lvalp, addrp, realnump, bufferp);
}
static CORE_ADDR
-ms1_frame_base_address (struct frame_info *next_frame,
+mt_frame_base_address (struct frame_info *next_frame,
void **this_prologue_cache)
{
- struct ms1_unwind_cache *info =
- ms1_frame_unwind_cache (next_frame, this_prologue_cache);
+ struct mt_unwind_cache *info =
+ mt_frame_unwind_cache (next_frame, this_prologue_cache);
return info->frame_base;
}
This exports the 'prev_register' and 'this_id' methods. */
-static const struct frame_unwind ms1_frame_unwind = {
+static const struct frame_unwind mt_frame_unwind = {
NORMAL_FRAME,
- ms1_frame_this_id,
- ms1_frame_prev_register
+ mt_frame_this_id,
+ mt_frame_prev_register
};
/* The sniffer is a registered function that identifies our family of
frame unwind functions (this_id and prev_register). */
static const struct frame_unwind *
-ms1_frame_sniffer (struct frame_info *next_frame)
+mt_frame_sniffer (struct frame_info *next_frame)
{
- return &ms1_frame_unwind;
+ return &mt_frame_unwind;
}
/* Another shared interface: the 'frame_base' object specifies how to
unwind a frame and secure the base addresses for frame objects
(locals, args). */
-static struct frame_base ms1_frame_base = {
- &ms1_frame_unwind,
- ms1_frame_base_address,
- ms1_frame_base_address,
- ms1_frame_base_address
+static struct frame_base mt_frame_base = {
+ &mt_frame_unwind,
+ mt_frame_base_address,
+ mt_frame_base_address,
+ mt_frame_base_address
};
static struct gdbarch *
-ms1_gdbarch_init (struct gdbarch_info info, struct gdbarch_list *arches)
+mt_gdbarch_init (struct gdbarch_info info, struct gdbarch_list *arches)
{
struct gdbarch *gdbarch;
break;
default:
internal_error (__FILE__, __LINE__,
- _("ms1_gdbarch_init: bad byte order for float format"));
+ _("mt_gdbarch_init: bad byte order for float format"));
}
- set_gdbarch_register_name (gdbarch, ms1_register_name);
- set_gdbarch_num_regs (gdbarch, MS1_NUM_REGS);
- set_gdbarch_num_pseudo_regs (gdbarch, MS1_NUM_PSEUDO_REGS);
- set_gdbarch_pc_regnum (gdbarch, MS1_PC_REGNUM);
- set_gdbarch_sp_regnum (gdbarch, MS1_SP_REGNUM);
- set_gdbarch_pseudo_register_read (gdbarch, ms1_pseudo_register_read);
- set_gdbarch_pseudo_register_write (gdbarch, ms1_pseudo_register_write);
- set_gdbarch_skip_prologue (gdbarch, ms1_skip_prologue);
+ set_gdbarch_register_name (gdbarch, mt_register_name);
+ set_gdbarch_num_regs (gdbarch, MT_NUM_REGS);
+ set_gdbarch_num_pseudo_regs (gdbarch, MT_NUM_PSEUDO_REGS);
+ set_gdbarch_pc_regnum (gdbarch, MT_PC_REGNUM);
+ set_gdbarch_sp_regnum (gdbarch, MT_SP_REGNUM);
+ set_gdbarch_pseudo_register_read (gdbarch, mt_pseudo_register_read);
+ set_gdbarch_pseudo_register_write (gdbarch, mt_pseudo_register_write);
+ set_gdbarch_skip_prologue (gdbarch, mt_skip_prologue);
set_gdbarch_inner_than (gdbarch, core_addr_lessthan);
- set_gdbarch_breakpoint_from_pc (gdbarch, ms1_breakpoint_from_pc);
+ set_gdbarch_breakpoint_from_pc (gdbarch, mt_breakpoint_from_pc);
set_gdbarch_decr_pc_after_break (gdbarch, 0);
set_gdbarch_frame_args_skip (gdbarch, 0);
- set_gdbarch_print_insn (gdbarch, print_insn_ms1);
- set_gdbarch_register_type (gdbarch, ms1_register_type);
- set_gdbarch_register_reggroup_p (gdbarch, ms1_register_reggroup_p);
+ set_gdbarch_print_insn (gdbarch, print_insn_mt);
+ set_gdbarch_register_type (gdbarch, mt_register_type);
+ set_gdbarch_register_reggroup_p (gdbarch, mt_register_reggroup_p);
- set_gdbarch_return_value (gdbarch, ms1_return_value);
- set_gdbarch_sp_regnum (gdbarch, MS1_SP_REGNUM);
+ set_gdbarch_return_value (gdbarch, mt_return_value);
+ set_gdbarch_sp_regnum (gdbarch, MT_SP_REGNUM);
- set_gdbarch_frame_align (gdbarch, ms1_frame_align);
+ set_gdbarch_frame_align (gdbarch, mt_frame_align);
- set_gdbarch_print_registers_info (gdbarch, ms1_registers_info);
+ set_gdbarch_print_registers_info (gdbarch, mt_registers_info);
- set_gdbarch_push_dummy_call (gdbarch, ms1_push_dummy_call);
+ set_gdbarch_push_dummy_call (gdbarch, mt_push_dummy_call);
/* Target builtin data types. */
set_gdbarch_short_bit (gdbarch, 16);
/* Register the DWARF 2 sniffer first, and then the traditional prologue
based sniffer. */
frame_unwind_append_sniffer (gdbarch, dwarf2_frame_sniffer);
- frame_unwind_append_sniffer (gdbarch, ms1_frame_sniffer);
- frame_base_set_default (gdbarch, &ms1_frame_base);
+ frame_unwind_append_sniffer (gdbarch, mt_frame_sniffer);
+ frame_base_set_default (gdbarch, &mt_frame_base);
/* Register the 'unwind_pc' method. */
- set_gdbarch_unwind_pc (gdbarch, ms1_unwind_pc);
- set_gdbarch_unwind_sp (gdbarch, ms1_unwind_sp);
+ set_gdbarch_unwind_pc (gdbarch, mt_unwind_pc);
+ set_gdbarch_unwind_sp (gdbarch, mt_unwind_sp);
/* Methods for saving / extracting a dummy frame's ID.
The ID's stack address must match the SP value returned by
PUSH_DUMMY_CALL, and saved by generic_save_dummy_frame_tos. */
- set_gdbarch_unwind_dummy_id (gdbarch, ms1_unwind_dummy_id);
+ set_gdbarch_unwind_dummy_id (gdbarch, mt_unwind_dummy_id);
return gdbarch;
}
void
-_initialize_ms1_tdep (void)
+_initialize_mt_tdep (void)
{
- register_gdbarch_init (bfd_arch_ms1, ms1_gdbarch_init);
+ register_gdbarch_init (bfd_arch_mt, mt_gdbarch_init);
}
+2005-12-16 Nathan Sidwell <nathan@codesourcery.com>
+
+ Second part of ms1 to mt renaming.
+ * dis-asm.h (print_insn_mt): Renamed.
+
2005-12-12 Nathan Sidwell <nathan@codesourcery.com>
* elf/mt.h: Renamed from ms1.h
extern int print_insn_mmix (bfd_vma, disassemble_info *);
extern int print_insn_mn10200 (bfd_vma, disassemble_info *);
extern int print_insn_mn10300 (bfd_vma, disassemble_info *);
-extern int print_insn_ms1 (bfd_vma, disassemble_info *);
+extern int print_insn_mt (bfd_vma, disassemble_info *);
extern int print_insn_msp430 (bfd_vma, disassemble_info *);
extern int print_insn_ns32k (bfd_vma, disassemble_info *);
extern int print_insn_crx (bfd_vma, disassemble_info *);
+2005-12-16 Nathan Sidwell <nathan@codesourcery.com>
+
+ Second part of ms1 to mt renaming.
+ * common.h (EM_MT): Renamed.
+ * mt.h: Rename relocs, cpu & other defines.
+
2005-12-12 Paul Brook <paul@codesourcery.com>
* arm.h (elf32_arm_get_eabi_attr_int): Add prototype.
/* Ubicom IP2xxx; no ABI */
#define EM_IP2K_OLD 0x8217
-#define EM_MS1 0x2530 /* Morpho MS1; no ABI */
+#define EM_MT 0x2530 /* Morpho MT; no ABI */
/* MSP430 magic number
Written in the absense everything. */
along with this program; if not, write to the Free Software Foundation, Inc.,
59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. */
-#ifndef _ELF_MS1_H
-#define _ELF_MS1_H
+#ifndef _ELF_MT_H
+#define _ELF_MT_H
#include "elf/reloc-macros.h"
/* Relocations. */
-START_RELOC_NUMBERS (elf_ms1_reloc_type)
- RELOC_NUMBER (R_MS1_NONE, 0)
- RELOC_NUMBER (R_MS1_16, 1)
- RELOC_NUMBER (R_MS1_32, 2)
- RELOC_NUMBER (R_MS1_32_PCREL, 3)
- RELOC_NUMBER (R_MS1_PC16, 4)
- RELOC_NUMBER (R_MS1_HI16, 5)
- RELOC_NUMBER (R_MS1_LO16, 6)
-END_RELOC_NUMBERS(R_MS1_max)
-
-#define EF_MS1_CPU_MRISC 0x00000001 /* default */
-#define EF_MS1_CPU_MRISC2 0x00000002 /* MRISC2 */
-#define EF_MS1_CPU_MS2 0x00000003 /* MS2 */
-#define EF_MS1_CPU_MASK 0x00000003 /* specific cpu bits */
-#define EF_MS1_ALL_FLAGS (EF_MS1_CPU_MASK)
+START_RELOC_NUMBERS (elf_mt_reloc_type)
+ RELOC_NUMBER (R_MT_NONE, 0)
+ RELOC_NUMBER (R_MT_16, 1)
+ RELOC_NUMBER (R_MT_32, 2)
+ RELOC_NUMBER (R_MT_32_PCREL, 3)
+ RELOC_NUMBER (R_MT_PC16, 4)
+ RELOC_NUMBER (R_MT_HI16, 5)
+ RELOC_NUMBER (R_MT_LO16, 6)
+END_RELOC_NUMBERS(R_MT_max)
+
+#define EF_MT_CPU_MRISC 0x00000001 /* default */
+#define EF_MT_CPU_MRISC2 0x00000002 /* MRISC2 */
+#define EF_MT_CPU_MS2 0x00000003 /* MS2 */
+#define EF_MT_CPU_MASK 0x00000003 /* specific cpu bits */
+#define EF_MT_ALL_FLAGS (EF_MT_CPU_MASK)
/* The location of the memory mapped hardware stack. */
-#define MS1_STACK_VALUE 0x0f000000
-#define MS1_STACK_SIZE 0x20
+#define MT_STACK_VALUE 0x0f000000
+#define MT_STACK_SIZE 0x20
-#endif /* _ELF_MS1_H */
+#endif /* _ELF_MT_H */
+2005-12-16 Nathan Sidwell <nathan@codesourcery.com>
+
+ Second part of ms1 to mt renaming.
+ * emulparams/elf32mt.sh (ARCH, OUTPUT_FORMAT): Adjust.
+
2005-12-14 Jakub Jelinek <jakub@redhat.com>
* scripttempl/elf.sc: Put .gnu.linkonce.d.rel.ro.* sections into
MACHINE=
SCRIPT_NAME=elf
-OUTPUT_FORMAT="elf32-ms1"
+OUTPUT_FORMAT="elf32-mt"
# See also `include/elf/mt.h'
TEXT_START_ADDR=0x2000
-ARCH=ms1
+ARCH=mt
ENTRY=_start
EMBEDDED=yes
ELFSIZE=32
+2005-12-16 Nathan Sidwell <nathan@codesourcery.com>
+
+ Second part of ms1 to mt renaming.
+ * Makefile.am (HFILES, CFILES, ALL_MACHINES): Adjust.
+ (stamp-mt): Adjust rule.
+ (mt-asm.lo, mt-desc.lo, mt-dis.lo, mt-ibld.lo, mt-opc.lo): Rename &
+ adjust.
+ * Makefile.in: Rebuilt.
+ * configure: Rebuilt.
+ * configure.in (bfd_mt_arch): Rename & adjust.
+ * disassemble.c (ARCH_mt): Renamed.
+ (disassembler): Adjust.
+ * mt-asm.c: Renamed, rebuilt.
+ * mt-desc.c: Renamed, rebuilt.
+ * mt-desc.h: Renamed, rebuilt.
+ * mt-dis.c: Renamed, rebuilt.
+ * mt-ibld.c: Renamed, rebuilt.
+ * mt-opc.c: Renamed, rebuilt.
+ * mt-opc.h: Renamed, rebuilt.
+
2005-12-13 DJ Delorie <dj@redhat.com>
* m32c-desc.c: Regenerate.
m32c-desc.h m32c-opc.h \
m32r-desc.h m32r-opc.h \
mcore-opc.h \
- ms1-desc.h ms1-opc.h \
+ mt-desc.h mt-opc.h \
openrisc-desc.h openrisc-opc.h \
sh-opc.h \
sh64-opc.h \
m10300-opc.c \
mmix-dis.c \
mmix-opc.c \
- ms1-asm.c \
- ms1-desc.c \
- ms1-dis.c \
- ms1-ibld.c \
- ms1-opc.c \
+ mt-asm.c \
+ mt-desc.c \
+ mt-dis.c \
+ mt-ibld.c \
+ mt-opc.c \
ns32k-dis.c \
openrisc-asm.c \
openrisc-desc.c \
mips16-opc.lo \
mmix-dis.lo \
mmix-opc.lo \
- ms1-asm.lo \
- ms1-desc.lo \
- ms1-dis.lo \
- ms1-ibld.lo \
- ms1-opc.lo \
msp430-dis.lo \
+ mt-asm.lo \
+ mt-desc.lo \
+ mt-dis.lo \
+ mt-ibld.lo \
+ mt-opc.lo \
ns32k-dis.lo \
openrisc-asm.lo \
openrisc-desc.lo \
$(MAKE) run-cgen arch=frv prefix=frv options= \
archfile=$(srcdir)/../cpu/frv.cpu opcfile=$(srcdir)/../cpu/frv.opc extrafiles=
-$(srcdir)/ms1-desc.h $(srcdir)/ms1-desc.c $(srcdir)/ms1-opc.h $(srcdir)/ms1-opc.c $(srcdir)/ms1-ibld.c $(srcdir)/ms1-asm.c $(srcdir)/ms1-dis.c: $(MT_DEPS)
+$(srcdir)/mt-desc.h $(srcdir)/mt-desc.c $(srcdir)/mt-opc.h $(srcdir)/mt-opc.c $(srcdir)/mt-ibld.c $(srcdir)/mt-asm.c $(srcdir)/mt-dis.c: $(MT_DEPS)
@true
stamp-mt: $(CGENDEPS) $(srcdir)/../cpu/mt.cpu $(srcdir)/../cpu/mt.opc
- $(MAKE) run-cgen arch=ms1 prefix=ms1 options= \
+ $(MAKE) run-cgen arch=mt prefix=mt options= \
archfile=$(srcdir)/../cpu/mt.cpu \
opcfile=$(srcdir)/../cpu/mt.opc extrafiles=
$(BFD_H) $(INCDIR)/ansidecl.h $(INCDIR)/symcat.h $(INCDIR)/libiberty.h \
$(INCDIR)/ansidecl.h $(BFD_H) opintl.h
mmix-opc.lo: mmix-opc.c $(INCDIR)/opcode/mmix.h $(INCDIR)/symcat.h
-ms1-asm.lo: ms1-asm.c sysdep.h config.h $(INCDIR)/ansidecl.h \
+mt-asm.lo: mt-asm.c sysdep.h config.h $(INCDIR)/ansidecl.h \
$(BFD_H) $(INCDIR)/ansidecl.h $(INCDIR)/symcat.h $(INCDIR)/symcat.h \
- ms1-desc.h $(INCDIR)/opcode/cgen-bitset.h $(INCDIR)/opcode/cgen.h \
- $(INCDIR)/symcat.h $(INCDIR)/opcode/cgen-bitset.h ms1-opc.h \
+ mt-desc.h $(INCDIR)/opcode/cgen-bitset.h $(INCDIR)/opcode/cgen.h \
+ $(INCDIR)/symcat.h $(INCDIR)/opcode/cgen-bitset.h mt-opc.h \
opintl.h $(INCDIR)/xregex.h $(INCDIR)/xregex2.h $(INCDIR)/libiberty.h \
$(INCDIR)/ansidecl.h $(INCDIR)/safe-ctype.h
-ms1-desc.lo: ms1-desc.c sysdep.h config.h $(INCDIR)/ansidecl.h \
+mt-desc.lo: mt-desc.c sysdep.h config.h $(INCDIR)/ansidecl.h \
$(BFD_H) $(INCDIR)/ansidecl.h $(INCDIR)/symcat.h $(INCDIR)/symcat.h \
- ms1-desc.h $(INCDIR)/opcode/cgen-bitset.h $(INCDIR)/opcode/cgen.h \
- $(INCDIR)/symcat.h $(INCDIR)/opcode/cgen-bitset.h ms1-opc.h \
+ mt-desc.h $(INCDIR)/opcode/cgen-bitset.h $(INCDIR)/opcode/cgen.h \
+ $(INCDIR)/symcat.h $(INCDIR)/opcode/cgen-bitset.h mt-opc.h \
opintl.h $(INCDIR)/libiberty.h $(INCDIR)/ansidecl.h \
$(INCDIR)/xregex.h $(INCDIR)/xregex2.h
-ms1-dis.lo: ms1-dis.c sysdep.h config.h $(INCDIR)/ansidecl.h \
+mt-dis.lo: mt-dis.c sysdep.h config.h $(INCDIR)/ansidecl.h \
$(INCDIR)/dis-asm.h $(BFD_H) $(INCDIR)/ansidecl.h $(INCDIR)/symcat.h \
$(BFD_H) $(INCDIR)/symcat.h $(INCDIR)/libiberty.h $(INCDIR)/ansidecl.h \
- ms1-desc.h $(INCDIR)/opcode/cgen-bitset.h $(INCDIR)/opcode/cgen.h \
- $(INCDIR)/symcat.h $(INCDIR)/opcode/cgen-bitset.h ms1-opc.h \
+ mt-desc.h $(INCDIR)/opcode/cgen-bitset.h $(INCDIR)/opcode/cgen.h \
+ $(INCDIR)/symcat.h $(INCDIR)/opcode/cgen-bitset.h mt-opc.h \
opintl.h
-ms1-ibld.lo: ms1-ibld.c sysdep.h config.h $(INCDIR)/ansidecl.h \
+mt-ibld.lo: mt-ibld.c sysdep.h config.h $(INCDIR)/ansidecl.h \
$(INCDIR)/dis-asm.h $(BFD_H) $(INCDIR)/ansidecl.h $(INCDIR)/symcat.h \
- $(BFD_H) $(INCDIR)/symcat.h ms1-desc.h $(INCDIR)/opcode/cgen-bitset.h \
+ $(BFD_H) $(INCDIR)/symcat.h mt-desc.h $(INCDIR)/opcode/cgen-bitset.h \
$(INCDIR)/opcode/cgen.h $(INCDIR)/symcat.h $(INCDIR)/opcode/cgen-bitset.h \
- ms1-opc.h opintl.h $(INCDIR)/safe-ctype.h
-ms1-opc.lo: ms1-opc.c sysdep.h config.h $(INCDIR)/ansidecl.h \
+ mt-opc.h opintl.h $(INCDIR)/safe-ctype.h
+mt-opc.lo: mt-opc.c sysdep.h config.h $(INCDIR)/ansidecl.h \
$(BFD_H) $(INCDIR)/ansidecl.h $(INCDIR)/symcat.h $(INCDIR)/symcat.h \
- ms1-desc.h $(INCDIR)/opcode/cgen-bitset.h $(INCDIR)/opcode/cgen.h \
- $(INCDIR)/symcat.h $(INCDIR)/opcode/cgen-bitset.h ms1-opc.h \
+ mt-desc.h $(INCDIR)/opcode/cgen-bitset.h $(INCDIR)/opcode/cgen.h \
+ $(INCDIR)/symcat.h $(INCDIR)/opcode/cgen-bitset.h mt-opc.h \
$(INCDIR)/libiberty.h $(INCDIR)/ansidecl.h $(INCDIR)/safe-ctype.h
ns32k-dis.lo: ns32k-dis.c $(BFD_H) $(INCDIR)/ansidecl.h \
$(INCDIR)/symcat.h sysdep.h config.h $(INCDIR)/ansidecl.h \
m32c-desc.h m32c-opc.h \
m32r-desc.h m32r-opc.h \
mcore-opc.h \
- ms1-desc.h ms1-opc.h \
+ mt-desc.h mt-opc.h \
openrisc-desc.h openrisc-opc.h \
sh-opc.h \
sh64-opc.h \
m10300-opc.c \
mmix-dis.c \
mmix-opc.c \
- ms1-asm.c \
- ms1-desc.c \
- ms1-dis.c \
- ms1-ibld.c \
- ms1-opc.c \
+ mt-asm.c \
+ mt-desc.c \
+ mt-dis.c \
+ mt-ibld.c \
+ mt-opc.c \
ns32k-dis.c \
openrisc-asm.c \
openrisc-desc.c \
mips16-opc.lo \
mmix-dis.lo \
mmix-opc.lo \
- ms1-asm.lo \
- ms1-desc.lo \
- ms1-dis.lo \
- ms1-ibld.lo \
- ms1-opc.lo \
msp430-dis.lo \
+ mt-asm.lo \
+ mt-desc.lo \
+ mt-dis.lo \
+ mt-ibld.lo \
+ mt-opc.lo \
ns32k-dis.lo \
openrisc-asm.lo \
openrisc-desc.lo \
$(MAKE) run-cgen arch=frv prefix=frv options= \
archfile=$(srcdir)/../cpu/frv.cpu opcfile=$(srcdir)/../cpu/frv.opc extrafiles=
-$(srcdir)/ms1-desc.h $(srcdir)/ms1-desc.c $(srcdir)/ms1-opc.h $(srcdir)/ms1-opc.c $(srcdir)/ms1-ibld.c $(srcdir)/ms1-asm.c $(srcdir)/ms1-dis.c: $(MT_DEPS)
+$(srcdir)/mt-desc.h $(srcdir)/mt-desc.c $(srcdir)/mt-opc.h $(srcdir)/mt-opc.c $(srcdir)/mt-ibld.c $(srcdir)/mt-asm.c $(srcdir)/mt-dis.c: $(MT_DEPS)
@true
stamp-mt: $(CGENDEPS) $(srcdir)/../cpu/mt.cpu $(srcdir)/../cpu/mt.opc
- $(MAKE) run-cgen arch=ms1 prefix=ms1 options= \
+ $(MAKE) run-cgen arch=mt prefix=mt options= \
archfile=$(srcdir)/../cpu/mt.cpu \
opcfile=$(srcdir)/../cpu/mt.opc extrafiles=
$(BFD_H) $(INCDIR)/ansidecl.h $(INCDIR)/symcat.h $(INCDIR)/libiberty.h \
$(INCDIR)/ansidecl.h $(BFD_H) opintl.h
mmix-opc.lo: mmix-opc.c $(INCDIR)/opcode/mmix.h $(INCDIR)/symcat.h
-ms1-asm.lo: ms1-asm.c sysdep.h config.h $(INCDIR)/ansidecl.h \
+mt-asm.lo: mt-asm.c sysdep.h config.h $(INCDIR)/ansidecl.h \
$(BFD_H) $(INCDIR)/ansidecl.h $(INCDIR)/symcat.h $(INCDIR)/symcat.h \
- ms1-desc.h $(INCDIR)/opcode/cgen-bitset.h $(INCDIR)/opcode/cgen.h \
- $(INCDIR)/symcat.h $(INCDIR)/opcode/cgen-bitset.h ms1-opc.h \
+ mt-desc.h $(INCDIR)/opcode/cgen-bitset.h $(INCDIR)/opcode/cgen.h \
+ $(INCDIR)/symcat.h $(INCDIR)/opcode/cgen-bitset.h mt-opc.h \
opintl.h $(INCDIR)/xregex.h $(INCDIR)/xregex2.h $(INCDIR)/libiberty.h \
$(INCDIR)/ansidecl.h $(INCDIR)/safe-ctype.h
-ms1-desc.lo: ms1-desc.c sysdep.h config.h $(INCDIR)/ansidecl.h \
+mt-desc.lo: mt-desc.c sysdep.h config.h $(INCDIR)/ansidecl.h \
$(BFD_H) $(INCDIR)/ansidecl.h $(INCDIR)/symcat.h $(INCDIR)/symcat.h \
- ms1-desc.h $(INCDIR)/opcode/cgen-bitset.h $(INCDIR)/opcode/cgen.h \
- $(INCDIR)/symcat.h $(INCDIR)/opcode/cgen-bitset.h ms1-opc.h \
+ mt-desc.h $(INCDIR)/opcode/cgen-bitset.h $(INCDIR)/opcode/cgen.h \
+ $(INCDIR)/symcat.h $(INCDIR)/opcode/cgen-bitset.h mt-opc.h \
opintl.h $(INCDIR)/libiberty.h $(INCDIR)/ansidecl.h \
$(INCDIR)/xregex.h $(INCDIR)/xregex2.h
-ms1-dis.lo: ms1-dis.c sysdep.h config.h $(INCDIR)/ansidecl.h \
+mt-dis.lo: mt-dis.c sysdep.h config.h $(INCDIR)/ansidecl.h \
$(INCDIR)/dis-asm.h $(BFD_H) $(INCDIR)/ansidecl.h $(INCDIR)/symcat.h \
$(BFD_H) $(INCDIR)/symcat.h $(INCDIR)/libiberty.h $(INCDIR)/ansidecl.h \
- ms1-desc.h $(INCDIR)/opcode/cgen-bitset.h $(INCDIR)/opcode/cgen.h \
- $(INCDIR)/symcat.h $(INCDIR)/opcode/cgen-bitset.h ms1-opc.h \
+ mt-desc.h $(INCDIR)/opcode/cgen-bitset.h $(INCDIR)/opcode/cgen.h \
+ $(INCDIR)/symcat.h $(INCDIR)/opcode/cgen-bitset.h mt-opc.h \
opintl.h
-ms1-ibld.lo: ms1-ibld.c sysdep.h config.h $(INCDIR)/ansidecl.h \
+mt-ibld.lo: mt-ibld.c sysdep.h config.h $(INCDIR)/ansidecl.h \
$(INCDIR)/dis-asm.h $(BFD_H) $(INCDIR)/ansidecl.h $(INCDIR)/symcat.h \
- $(BFD_H) $(INCDIR)/symcat.h ms1-desc.h $(INCDIR)/opcode/cgen-bitset.h \
+ $(BFD_H) $(INCDIR)/symcat.h mt-desc.h $(INCDIR)/opcode/cgen-bitset.h \
$(INCDIR)/opcode/cgen.h $(INCDIR)/symcat.h $(INCDIR)/opcode/cgen-bitset.h \
- ms1-opc.h opintl.h $(INCDIR)/safe-ctype.h
-ms1-opc.lo: ms1-opc.c sysdep.h config.h $(INCDIR)/ansidecl.h \
+ mt-opc.h opintl.h $(INCDIR)/safe-ctype.h
+mt-opc.lo: mt-opc.c sysdep.h config.h $(INCDIR)/ansidecl.h \
$(BFD_H) $(INCDIR)/ansidecl.h $(INCDIR)/symcat.h $(INCDIR)/symcat.h \
- ms1-desc.h $(INCDIR)/opcode/cgen-bitset.h $(INCDIR)/opcode/cgen.h \
- $(INCDIR)/symcat.h $(INCDIR)/opcode/cgen-bitset.h ms1-opc.h \
+ mt-desc.h $(INCDIR)/opcode/cgen-bitset.h $(INCDIR)/opcode/cgen.h \
+ $(INCDIR)/symcat.h $(INCDIR)/opcode/cgen-bitset.h mt-opc.h \
$(INCDIR)/libiberty.h $(INCDIR)/ansidecl.h $(INCDIR)/safe-ctype.h
ns32k-dis.lo: ns32k-dis.c $(BFD_H) $(INCDIR)/ansidecl.h \
$(INCDIR)/symcat.h sysdep.h config.h $(INCDIR)/ansidecl.h \
bfd_mmix_arch) ta="$ta mmix-dis.lo mmix-opc.lo" ;;
bfd_mn10200_arch) ta="$ta m10200-dis.lo m10200-opc.lo" ;;
bfd_mn10300_arch) ta="$ta m10300-dis.lo m10300-opc.lo" ;;
- bfd_ms1_arch) ta="$ta ms1-asm.lo ms1-desc.lo ms1-dis.lo ms1-ibld.lo ms1-opc.lo" using_cgen=yes ;;
+ bfd_mt_arch) ta="$ta mt-asm.lo mt-desc.lo mt-dis.lo mt-ibld.lo mt-opc.lo" using_cgen=yes ;;
bfd_msp430_arch) ta="$ta msp430-dis.lo" ;;
bfd_ns32k_arch) ta="$ta ns32k-dis.lo" ;;
bfd_openrisc_arch) ta="$ta openrisc-asm.lo openrisc-desc.lo openrisc-dis.lo openrisc-ibld.lo openrisc-opc.lo" using_cgen=yes ;;
bfd_mmix_arch) ta="$ta mmix-dis.lo mmix-opc.lo" ;;
bfd_mn10200_arch) ta="$ta m10200-dis.lo m10200-opc.lo" ;;
bfd_mn10300_arch) ta="$ta m10300-dis.lo m10300-opc.lo" ;;
- bfd_ms1_arch) ta="$ta mt-asm.lo ms1-desc.lo ms1-dis.lo ms1-ibld.lo ms1-opc.lo" using_cgen=yes ;;
+ bfd_mt_arch) ta="$ta mt-asm.lo mt-desc.lo mt-dis.lo mt-ibld.lo mt-opc.lo" using_cgen=yes ;;
bfd_msp430_arch) ta="$ta msp430-dis.lo" ;;
bfd_ns32k_arch) ta="$ta ns32k-dis.lo" ;;
bfd_openrisc_arch) ta="$ta openrisc-asm.lo openrisc-desc.lo openrisc-dis.lo openrisc-ibld.lo openrisc-opc.lo" using_cgen=yes ;;
#define ARCH_mmix
#define ARCH_mn10200
#define ARCH_mn10300
-#define ARCH_ms1
+#define ARCH_mt
#define ARCH_msp430
#define ARCH_ns32k
#define ARCH_openrisc
disassemble = print_insn_maxq_little;
break;
#endif
-#ifdef ARCH_ms1
- case bfd_arch_ms1:
- disassemble = print_insn_ms1;
+#ifdef ARCH_mt
+ case bfd_arch_mt:
+ disassemble = print_insn_mt;
break;
#endif
#ifdef ARCH_msp430
#include "ansidecl.h"
#include "bfd.h"
#include "symcat.h"
-#include "ms1-desc.h"
-#include "ms1-opc.h"
+#include "mt-desc.h"
+#include "mt-opc.h"
#include "opintl.h"
#include "xregex.h"
#include "libiberty.h"
bfd_vma value;
/* Is it a control transfer instructions? */
- if (opindex == (CGEN_OPERAND_TYPE) MS1_OPERAND_LOOPSIZE)
+ if (opindex == (CGEN_OPERAND_TYPE) MT_OPERAND_LOOPSIZE)
{
- code = BFD_RELOC_MS1_PCINSN8;
+ code = BFD_RELOC_MT_PCINSN8;
errmsg = cgen_parse_address (cd, strp, opindex, code,
& result_type, & value);
*valuep = value;
bfd_vma value;
/* Is it a control transfer instructions? */
- if (opindex == (CGEN_OPERAND_TYPE) MS1_OPERAND_IMM16O)
+ if (opindex == (CGEN_OPERAND_TYPE) MT_OPERAND_IMM16O)
{
code = BFD_RELOC_16_PCREL;
errmsg = cgen_parse_address (cd, strp, opindex, code,
/* If it's not a control transfer instruction, then
we have to check for %OP relocating operators. */
- if (opindex == (CGEN_OPERAND_TYPE) MS1_OPERAND_IMM16L)
+ if (opindex == (CGEN_OPERAND_TYPE) MT_OPERAND_IMM16L)
;
else if (strncmp (*strp, "%hi16", 5) == 0)
{
{
/* Parse hex values like 0xffff as unsigned, and sign extend
them manually. */
- int parse_signed = (opindex == (CGEN_OPERAND_TYPE)MS1_OPERAND_IMM16);
+ int parse_signed = (opindex == (CGEN_OPERAND_TYPE)MT_OPERAND_IMM16);
if ((*strp)[0] == '0'
&& ((*strp)[1] == 'x' || (*strp)[1] == 'X'))
}
else
{
- /* MS1_OPERAND_IMM16Z. Parse as an unsigned integer. */
+ /* MT_OPERAND_IMM16Z. Parse as an unsigned integer. */
errmsg = cgen_parse_unsigned_integer (cd, strp, opindex, (unsigned long *) valuep);
- if (opindex == (CGEN_OPERAND_TYPE) MS1_OPERAND_IMM16
+ if (opindex == (CGEN_OPERAND_TYPE) MT_OPERAND_IMM16
&& *valuep >= 0x8000
&& *valuep <= 0xffff)
*valuep -= 0x10000;
/* -- dis.c */
-const char * ms1_cgen_parse_operand
+const char * mt_cgen_parse_operand
(CGEN_CPU_DESC, int, const char **, CGEN_FIELDS *);
/* Main entry point for operand parsing.
the handlers. */
const char *
-ms1_cgen_parse_operand (CGEN_CPU_DESC cd,
+mt_cgen_parse_operand (CGEN_CPU_DESC cd,
int opindex,
const char ** strp,
CGEN_FIELDS * fields)
switch (opindex)
{
- case MS1_OPERAND_A23 :
- errmsg = cgen_parse_unsigned_integer (cd, strp, MS1_OPERAND_A23, (unsigned long *) (& fields->f_a23));
+ case MT_OPERAND_A23 :
+ errmsg = cgen_parse_unsigned_integer (cd, strp, MT_OPERAND_A23, (unsigned long *) (& fields->f_a23));
break;
- case MS1_OPERAND_BALL :
- errmsg = parse_ball (cd, strp, MS1_OPERAND_BALL, (unsigned long *) (& fields->f_ball));
+ case MT_OPERAND_BALL :
+ errmsg = parse_ball (cd, strp, MT_OPERAND_BALL, (unsigned long *) (& fields->f_ball));
break;
- case MS1_OPERAND_BALL2 :
- errmsg = parse_ball (cd, strp, MS1_OPERAND_BALL2, (unsigned long *) (& fields->f_ball2));
+ case MT_OPERAND_BALL2 :
+ errmsg = parse_ball (cd, strp, MT_OPERAND_BALL2, (unsigned long *) (& fields->f_ball2));
break;
- case MS1_OPERAND_BANKADDR :
- errmsg = cgen_parse_unsigned_integer (cd, strp, MS1_OPERAND_BANKADDR, (unsigned long *) (& fields->f_bankaddr));
+ case MT_OPERAND_BANKADDR :
+ errmsg = cgen_parse_unsigned_integer (cd, strp, MT_OPERAND_BANKADDR, (unsigned long *) (& fields->f_bankaddr));
break;
- case MS1_OPERAND_BRC :
- errmsg = cgen_parse_unsigned_integer (cd, strp, MS1_OPERAND_BRC, (unsigned long *) (& fields->f_brc));
+ case MT_OPERAND_BRC :
+ errmsg = cgen_parse_unsigned_integer (cd, strp, MT_OPERAND_BRC, (unsigned long *) (& fields->f_brc));
break;
- case MS1_OPERAND_BRC2 :
- errmsg = cgen_parse_unsigned_integer (cd, strp, MS1_OPERAND_BRC2, (unsigned long *) (& fields->f_brc2));
+ case MT_OPERAND_BRC2 :
+ errmsg = cgen_parse_unsigned_integer (cd, strp, MT_OPERAND_BRC2, (unsigned long *) (& fields->f_brc2));
break;
- case MS1_OPERAND_CB1INCR :
- errmsg = cgen_parse_signed_integer (cd, strp, MS1_OPERAND_CB1INCR, (long *) (& fields->f_cb1incr));
+ case MT_OPERAND_CB1INCR :
+ errmsg = cgen_parse_signed_integer (cd, strp, MT_OPERAND_CB1INCR, (long *) (& fields->f_cb1incr));
break;
- case MS1_OPERAND_CB1SEL :
- errmsg = cgen_parse_unsigned_integer (cd, strp, MS1_OPERAND_CB1SEL, (unsigned long *) (& fields->f_cb1sel));
+ case MT_OPERAND_CB1SEL :
+ errmsg = cgen_parse_unsigned_integer (cd, strp, MT_OPERAND_CB1SEL, (unsigned long *) (& fields->f_cb1sel));
break;
- case MS1_OPERAND_CB2INCR :
- errmsg = cgen_parse_signed_integer (cd, strp, MS1_OPERAND_CB2INCR, (long *) (& fields->f_cb2incr));
+ case MT_OPERAND_CB2INCR :
+ errmsg = cgen_parse_signed_integer (cd, strp, MT_OPERAND_CB2INCR, (long *) (& fields->f_cb2incr));
break;
- case MS1_OPERAND_CB2SEL :
- errmsg = cgen_parse_unsigned_integer (cd, strp, MS1_OPERAND_CB2SEL, (unsigned long *) (& fields->f_cb2sel));
+ case MT_OPERAND_CB2SEL :
+ errmsg = cgen_parse_unsigned_integer (cd, strp, MT_OPERAND_CB2SEL, (unsigned long *) (& fields->f_cb2sel));
break;
- case MS1_OPERAND_CBRB :
- errmsg = parse_cbrb (cd, strp, MS1_OPERAND_CBRB, (unsigned long *) (& fields->f_cbrb));
+ case MT_OPERAND_CBRB :
+ errmsg = parse_cbrb (cd, strp, MT_OPERAND_CBRB, (unsigned long *) (& fields->f_cbrb));
break;
- case MS1_OPERAND_CBS :
- errmsg = cgen_parse_unsigned_integer (cd, strp, MS1_OPERAND_CBS, (unsigned long *) (& fields->f_cbs));
+ case MT_OPERAND_CBS :
+ errmsg = cgen_parse_unsigned_integer (cd, strp, MT_OPERAND_CBS, (unsigned long *) (& fields->f_cbs));
break;
- case MS1_OPERAND_CBX :
- errmsg = cgen_parse_unsigned_integer (cd, strp, MS1_OPERAND_CBX, (unsigned long *) (& fields->f_cbx));
+ case MT_OPERAND_CBX :
+ errmsg = cgen_parse_unsigned_integer (cd, strp, MT_OPERAND_CBX, (unsigned long *) (& fields->f_cbx));
break;
- case MS1_OPERAND_CCB :
- errmsg = cgen_parse_unsigned_integer (cd, strp, MS1_OPERAND_CCB, (unsigned long *) (& fields->f_ccb));
+ case MT_OPERAND_CCB :
+ errmsg = cgen_parse_unsigned_integer (cd, strp, MT_OPERAND_CCB, (unsigned long *) (& fields->f_ccb));
break;
- case MS1_OPERAND_CDB :
- errmsg = cgen_parse_unsigned_integer (cd, strp, MS1_OPERAND_CDB, (unsigned long *) (& fields->f_cdb));
+ case MT_OPERAND_CDB :
+ errmsg = cgen_parse_unsigned_integer (cd, strp, MT_OPERAND_CDB, (unsigned long *) (& fields->f_cdb));
break;
- case MS1_OPERAND_CELL :
- errmsg = cgen_parse_unsigned_integer (cd, strp, MS1_OPERAND_CELL, (unsigned long *) (& fields->f_cell));
+ case MT_OPERAND_CELL :
+ errmsg = cgen_parse_unsigned_integer (cd, strp, MT_OPERAND_CELL, (unsigned long *) (& fields->f_cell));
break;
- case MS1_OPERAND_COLNUM :
- errmsg = cgen_parse_unsigned_integer (cd, strp, MS1_OPERAND_COLNUM, (unsigned long *) (& fields->f_colnum));
+ case MT_OPERAND_COLNUM :
+ errmsg = cgen_parse_unsigned_integer (cd, strp, MT_OPERAND_COLNUM, (unsigned long *) (& fields->f_colnum));
break;
- case MS1_OPERAND_CONTNUM :
- errmsg = cgen_parse_unsigned_integer (cd, strp, MS1_OPERAND_CONTNUM, (unsigned long *) (& fields->f_contnum));
+ case MT_OPERAND_CONTNUM :
+ errmsg = cgen_parse_unsigned_integer (cd, strp, MT_OPERAND_CONTNUM, (unsigned long *) (& fields->f_contnum));
break;
- case MS1_OPERAND_CR :
- errmsg = cgen_parse_unsigned_integer (cd, strp, MS1_OPERAND_CR, (unsigned long *) (& fields->f_cr));
+ case MT_OPERAND_CR :
+ errmsg = cgen_parse_unsigned_integer (cd, strp, MT_OPERAND_CR, (unsigned long *) (& fields->f_cr));
break;
- case MS1_OPERAND_CTXDISP :
- errmsg = cgen_parse_unsigned_integer (cd, strp, MS1_OPERAND_CTXDISP, (unsigned long *) (& fields->f_ctxdisp));
+ case MT_OPERAND_CTXDISP :
+ errmsg = cgen_parse_unsigned_integer (cd, strp, MT_OPERAND_CTXDISP, (unsigned long *) (& fields->f_ctxdisp));
break;
- case MS1_OPERAND_DUP :
- errmsg = parse_dup (cd, strp, MS1_OPERAND_DUP, (unsigned long *) (& fields->f_dup));
+ case MT_OPERAND_DUP :
+ errmsg = parse_dup (cd, strp, MT_OPERAND_DUP, (unsigned long *) (& fields->f_dup));
break;
- case MS1_OPERAND_FBDISP :
- errmsg = cgen_parse_unsigned_integer (cd, strp, MS1_OPERAND_FBDISP, (unsigned long *) (& fields->f_fbdisp));
+ case MT_OPERAND_FBDISP :
+ errmsg = cgen_parse_unsigned_integer (cd, strp, MT_OPERAND_FBDISP, (unsigned long *) (& fields->f_fbdisp));
break;
- case MS1_OPERAND_FBINCR :
- errmsg = cgen_parse_unsigned_integer (cd, strp, MS1_OPERAND_FBINCR, (unsigned long *) (& fields->f_fbincr));
+ case MT_OPERAND_FBINCR :
+ errmsg = cgen_parse_unsigned_integer (cd, strp, MT_OPERAND_FBINCR, (unsigned long *) (& fields->f_fbincr));
break;
- case MS1_OPERAND_FRDR :
- errmsg = cgen_parse_keyword (cd, strp, & ms1_cgen_opval_h_spr, & fields->f_dr);
+ case MT_OPERAND_FRDR :
+ errmsg = cgen_parse_keyword (cd, strp, & mt_cgen_opval_h_spr, & fields->f_dr);
break;
- case MS1_OPERAND_FRDRRR :
- errmsg = cgen_parse_keyword (cd, strp, & ms1_cgen_opval_h_spr, & fields->f_drrr);
+ case MT_OPERAND_FRDRRR :
+ errmsg = cgen_parse_keyword (cd, strp, & mt_cgen_opval_h_spr, & fields->f_drrr);
break;
- case MS1_OPERAND_FRSR1 :
- errmsg = cgen_parse_keyword (cd, strp, & ms1_cgen_opval_h_spr, & fields->f_sr1);
+ case MT_OPERAND_FRSR1 :
+ errmsg = cgen_parse_keyword (cd, strp, & mt_cgen_opval_h_spr, & fields->f_sr1);
break;
- case MS1_OPERAND_FRSR2 :
- errmsg = cgen_parse_keyword (cd, strp, & ms1_cgen_opval_h_spr, & fields->f_sr2);
+ case MT_OPERAND_FRSR2 :
+ errmsg = cgen_parse_keyword (cd, strp, & mt_cgen_opval_h_spr, & fields->f_sr2);
break;
- case MS1_OPERAND_ID :
- errmsg = cgen_parse_unsigned_integer (cd, strp, MS1_OPERAND_ID, (unsigned long *) (& fields->f_id));
+ case MT_OPERAND_ID :
+ errmsg = cgen_parse_unsigned_integer (cd, strp, MT_OPERAND_ID, (unsigned long *) (& fields->f_id));
break;
- case MS1_OPERAND_IMM16 :
- errmsg = parse_imm16 (cd, strp, MS1_OPERAND_IMM16, (long *) (& fields->f_imm16s));
+ case MT_OPERAND_IMM16 :
+ errmsg = parse_imm16 (cd, strp, MT_OPERAND_IMM16, (long *) (& fields->f_imm16s));
break;
- case MS1_OPERAND_IMM16L :
- errmsg = cgen_parse_unsigned_integer (cd, strp, MS1_OPERAND_IMM16L, (unsigned long *) (& fields->f_imm16l));
+ case MT_OPERAND_IMM16L :
+ errmsg = cgen_parse_unsigned_integer (cd, strp, MT_OPERAND_IMM16L, (unsigned long *) (& fields->f_imm16l));
break;
- case MS1_OPERAND_IMM16O :
- errmsg = parse_imm16 (cd, strp, MS1_OPERAND_IMM16O, (unsigned long *) (& fields->f_imm16s));
+ case MT_OPERAND_IMM16O :
+ errmsg = parse_imm16 (cd, strp, MT_OPERAND_IMM16O, (unsigned long *) (& fields->f_imm16s));
break;
- case MS1_OPERAND_IMM16Z :
- errmsg = parse_imm16 (cd, strp, MS1_OPERAND_IMM16Z, (unsigned long *) (& fields->f_imm16u));
+ case MT_OPERAND_IMM16Z :
+ errmsg = parse_imm16 (cd, strp, MT_OPERAND_IMM16Z, (unsigned long *) (& fields->f_imm16u));
break;
- case MS1_OPERAND_INCAMT :
- errmsg = cgen_parse_unsigned_integer (cd, strp, MS1_OPERAND_INCAMT, (unsigned long *) (& fields->f_incamt));
+ case MT_OPERAND_INCAMT :
+ errmsg = cgen_parse_unsigned_integer (cd, strp, MT_OPERAND_INCAMT, (unsigned long *) (& fields->f_incamt));
break;
- case MS1_OPERAND_INCR :
- errmsg = cgen_parse_unsigned_integer (cd, strp, MS1_OPERAND_INCR, (unsigned long *) (& fields->f_incr));
+ case MT_OPERAND_INCR :
+ errmsg = cgen_parse_unsigned_integer (cd, strp, MT_OPERAND_INCR, (unsigned long *) (& fields->f_incr));
break;
- case MS1_OPERAND_LENGTH :
- errmsg = cgen_parse_unsigned_integer (cd, strp, MS1_OPERAND_LENGTH, (unsigned long *) (& fields->f_length));
+ case MT_OPERAND_LENGTH :
+ errmsg = cgen_parse_unsigned_integer (cd, strp, MT_OPERAND_LENGTH, (unsigned long *) (& fields->f_length));
break;
- case MS1_OPERAND_LOOPSIZE :
- errmsg = parse_loopsize (cd, strp, MS1_OPERAND_LOOPSIZE, (unsigned long *) (& fields->f_loopo));
+ case MT_OPERAND_LOOPSIZE :
+ errmsg = parse_loopsize (cd, strp, MT_OPERAND_LOOPSIZE, (unsigned long *) (& fields->f_loopo));
break;
- case MS1_OPERAND_MASK :
- errmsg = cgen_parse_unsigned_integer (cd, strp, MS1_OPERAND_MASK, (unsigned long *) (& fields->f_mask));
+ case MT_OPERAND_MASK :
+ errmsg = cgen_parse_unsigned_integer (cd, strp, MT_OPERAND_MASK, (unsigned long *) (& fields->f_mask));
break;
- case MS1_OPERAND_MASK1 :
- errmsg = cgen_parse_unsigned_integer (cd, strp, MS1_OPERAND_MASK1, (unsigned long *) (& fields->f_mask1));
+ case MT_OPERAND_MASK1 :
+ errmsg = cgen_parse_unsigned_integer (cd, strp, MT_OPERAND_MASK1, (unsigned long *) (& fields->f_mask1));
break;
- case MS1_OPERAND_MODE :
- errmsg = cgen_parse_unsigned_integer (cd, strp, MS1_OPERAND_MODE, (unsigned long *) (& fields->f_mode));
+ case MT_OPERAND_MODE :
+ errmsg = cgen_parse_unsigned_integer (cd, strp, MT_OPERAND_MODE, (unsigned long *) (& fields->f_mode));
break;
- case MS1_OPERAND_PERM :
- errmsg = cgen_parse_unsigned_integer (cd, strp, MS1_OPERAND_PERM, (unsigned long *) (& fields->f_perm));
+ case MT_OPERAND_PERM :
+ errmsg = cgen_parse_unsigned_integer (cd, strp, MT_OPERAND_PERM, (unsigned long *) (& fields->f_perm));
break;
- case MS1_OPERAND_RBBC :
- errmsg = parse_rbbc (cd, strp, MS1_OPERAND_RBBC, (unsigned long *) (& fields->f_rbbc));
+ case MT_OPERAND_RBBC :
+ errmsg = parse_rbbc (cd, strp, MT_OPERAND_RBBC, (unsigned long *) (& fields->f_rbbc));
break;
- case MS1_OPERAND_RC :
- errmsg = parse_rc (cd, strp, MS1_OPERAND_RC, (unsigned long *) (& fields->f_rc));
+ case MT_OPERAND_RC :
+ errmsg = parse_rc (cd, strp, MT_OPERAND_RC, (unsigned long *) (& fields->f_rc));
break;
- case MS1_OPERAND_RC1 :
- errmsg = parse_rc (cd, strp, MS1_OPERAND_RC1, (unsigned long *) (& fields->f_rc1));
+ case MT_OPERAND_RC1 :
+ errmsg = parse_rc (cd, strp, MT_OPERAND_RC1, (unsigned long *) (& fields->f_rc1));
break;
- case MS1_OPERAND_RC2 :
- errmsg = parse_rc (cd, strp, MS1_OPERAND_RC2, (unsigned long *) (& fields->f_rc2));
+ case MT_OPERAND_RC2 :
+ errmsg = parse_rc (cd, strp, MT_OPERAND_RC2, (unsigned long *) (& fields->f_rc2));
break;
- case MS1_OPERAND_RC3 :
- errmsg = parse_rc (cd, strp, MS1_OPERAND_RC3, (unsigned long *) (& fields->f_rc3));
+ case MT_OPERAND_RC3 :
+ errmsg = parse_rc (cd, strp, MT_OPERAND_RC3, (unsigned long *) (& fields->f_rc3));
break;
- case MS1_OPERAND_RCNUM :
- errmsg = cgen_parse_unsigned_integer (cd, strp, MS1_OPERAND_RCNUM, (unsigned long *) (& fields->f_rcnum));
+ case MT_OPERAND_RCNUM :
+ errmsg = cgen_parse_unsigned_integer (cd, strp, MT_OPERAND_RCNUM, (unsigned long *) (& fields->f_rcnum));
break;
- case MS1_OPERAND_RDA :
- errmsg = cgen_parse_unsigned_integer (cd, strp, MS1_OPERAND_RDA, (unsigned long *) (& fields->f_rda));
+ case MT_OPERAND_RDA :
+ errmsg = cgen_parse_unsigned_integer (cd, strp, MT_OPERAND_RDA, (unsigned long *) (& fields->f_rda));
break;
- case MS1_OPERAND_ROWNUM :
- errmsg = cgen_parse_unsigned_integer (cd, strp, MS1_OPERAND_ROWNUM, (unsigned long *) (& fields->f_rownum));
+ case MT_OPERAND_ROWNUM :
+ errmsg = cgen_parse_unsigned_integer (cd, strp, MT_OPERAND_ROWNUM, (unsigned long *) (& fields->f_rownum));
break;
- case MS1_OPERAND_ROWNUM1 :
- errmsg = cgen_parse_unsigned_integer (cd, strp, MS1_OPERAND_ROWNUM1, (unsigned long *) (& fields->f_rownum1));
+ case MT_OPERAND_ROWNUM1 :
+ errmsg = cgen_parse_unsigned_integer (cd, strp, MT_OPERAND_ROWNUM1, (unsigned long *) (& fields->f_rownum1));
break;
- case MS1_OPERAND_ROWNUM2 :
- errmsg = cgen_parse_unsigned_integer (cd, strp, MS1_OPERAND_ROWNUM2, (unsigned long *) (& fields->f_rownum2));
+ case MT_OPERAND_ROWNUM2 :
+ errmsg = cgen_parse_unsigned_integer (cd, strp, MT_OPERAND_ROWNUM2, (unsigned long *) (& fields->f_rownum2));
break;
- case MS1_OPERAND_SIZE :
- errmsg = cgen_parse_unsigned_integer (cd, strp, MS1_OPERAND_SIZE, (unsigned long *) (& fields->f_size));
+ case MT_OPERAND_SIZE :
+ errmsg = cgen_parse_unsigned_integer (cd, strp, MT_OPERAND_SIZE, (unsigned long *) (& fields->f_size));
break;
- case MS1_OPERAND_TYPE :
- errmsg = parse_type (cd, strp, MS1_OPERAND_TYPE, (unsigned long *) (& fields->f_type));
+ case MT_OPERAND_TYPE :
+ errmsg = parse_type (cd, strp, MT_OPERAND_TYPE, (unsigned long *) (& fields->f_type));
break;
- case MS1_OPERAND_WR :
- errmsg = cgen_parse_unsigned_integer (cd, strp, MS1_OPERAND_WR, (unsigned long *) (& fields->f_wr));
+ case MT_OPERAND_WR :
+ errmsg = cgen_parse_unsigned_integer (cd, strp, MT_OPERAND_WR, (unsigned long *) (& fields->f_wr));
break;
- case MS1_OPERAND_XMODE :
- errmsg = parse_xmode (cd, strp, MS1_OPERAND_XMODE, (unsigned long *) (& fields->f_xmode));
+ case MT_OPERAND_XMODE :
+ errmsg = parse_xmode (cd, strp, MT_OPERAND_XMODE, (unsigned long *) (& fields->f_xmode));
break;
default :
return errmsg;
}
-cgen_parse_fn * const ms1_cgen_parse_handlers[] =
+cgen_parse_fn * const mt_cgen_parse_handlers[] =
{
parse_insn_normal,
};
void
-ms1_cgen_init_asm (CGEN_CPU_DESC cd)
+mt_cgen_init_asm (CGEN_CPU_DESC cd)
{
- ms1_cgen_init_opcode_table (cd);
- ms1_cgen_init_ibld_table (cd);
- cd->parse_handlers = & ms1_cgen_parse_handlers[0];
- cd->parse_operand = ms1_cgen_parse_operand;
+ mt_cgen_init_opcode_table (cd);
+ mt_cgen_init_ibld_table (cd);
+ cd->parse_handlers = & mt_cgen_parse_handlers[0];
+ cd->parse_operand = mt_cgen_parse_operand;
}
\f
opcode) with the pattern '.*'
It then compiles the regex and stores it in the opcode, for
- later use by ms1_cgen_assemble_insn
+ later use by mt_cgen_assemble_insn
Returns NULL for success, an error message for failure. */
char *
-ms1_cgen_build_insn_regex (CGEN_INSN *insn)
+mt_cgen_build_insn_regex (CGEN_INSN *insn)
{
CGEN_OPCODE *opc = (CGEN_OPCODE *) CGEN_INSN_OPCODE (insn);
const char *mnem = CGEN_INSN_MNEMONIC (insn);
mind helps keep the design clean. */
const CGEN_INSN *
-ms1_cgen_assemble_insn (CGEN_CPU_DESC cd,
+mt_cgen_assemble_insn (CGEN_CPU_DESC cd,
const char *str,
CGEN_FIELDS *fields,
CGEN_INSN_BYTES_PTR buf,
/* Not usually needed as unsupported opcodes
shouldn't be in the hash lists. */
/* Is this insn supported by the selected cpu? */
- if (! ms1_cgen_insn_supported (cd, insn))
+ if (! mt_cgen_insn_supported (cd, insn))
continue;
#endif
/* If the RELAXED attribute is set, this is an insn that shouldn't be
-/* CPU data for ms1.
+/* CPU data for mt.
THIS FILE IS MACHINE GENERATED WITH CGEN.
#include "ansidecl.h"
#include "bfd.h"
#include "symcat.h"
-#include "ms1-desc.h"
-#include "ms1-opc.h"
+#include "mt-desc.h"
+#include "mt-opc.h"
#include "opintl.h"
#include "libiberty.h"
#include "xregex.h"
static const CGEN_ATTR_ENTRY ISA_attr[] ATTRIBUTE_UNUSED =
{
- { "ms1", ISA_MS1 },
+ { "mt", ISA_MT },
{ "max", ISA_MAX },
{ 0, 0 }
};
-const CGEN_ATTR_TABLE ms1_cgen_ifield_attr_table[] =
+const CGEN_ATTR_TABLE mt_cgen_ifield_attr_table[] =
{
{ "MACH", & MACH_attr[0], & MACH_attr[0] },
{ "VIRTUAL", &bool_attr[0], &bool_attr[0] },
{ 0, 0, 0 }
};
-const CGEN_ATTR_TABLE ms1_cgen_hardware_attr_table[] =
+const CGEN_ATTR_TABLE mt_cgen_hardware_attr_table[] =
{
{ "MACH", & MACH_attr[0], & MACH_attr[0] },
{ "VIRTUAL", &bool_attr[0], &bool_attr[0] },
{ 0, 0, 0 }
};
-const CGEN_ATTR_TABLE ms1_cgen_operand_attr_table[] =
+const CGEN_ATTR_TABLE mt_cgen_operand_attr_table[] =
{
{ "MACH", & MACH_attr[0], & MACH_attr[0] },
{ "VIRTUAL", &bool_attr[0], &bool_attr[0] },
{ 0, 0, 0 }
};
-const CGEN_ATTR_TABLE ms1_cgen_insn_attr_table[] =
+const CGEN_ATTR_TABLE mt_cgen_insn_attr_table[] =
{
{ "MACH", & MACH_attr[0], & MACH_attr[0] },
{ "ALIAS", &bool_attr[0], &bool_attr[0] },
/* Instruction set variants. */
-static const CGEN_ISA ms1_cgen_isa_table[] = {
- { "ms1", 32, 32, 32, 32 },
+static const CGEN_ISA mt_cgen_isa_table[] = {
+ { "mt", 32, 32, 32, 32 },
{ 0, 0, 0, 0, 0 }
};
/* Machine variants. */
-static const CGEN_MACH ms1_cgen_mach_table[] = {
+static const CGEN_MACH mt_cgen_mach_table[] = {
{ "ms1", "ms1", MACH_MS1, 0 },
{ "ms1-003", "ms1-003", MACH_MS1_003, 0 },
{ "ms2", "ms2", MACH_MS2, 0 },
{ 0, 0, 0, 0 }
};
-static CGEN_KEYWORD_ENTRY ms1_cgen_opval_msys_syms_entries[] =
+static CGEN_KEYWORD_ENTRY mt_cgen_opval_msys_syms_entries[] =
{
{ "DUP", 1, {0, {{{0, 0}}}}, 0, 0 },
{ "XX", 0, {0, {{{0, 0}}}}, 0, 0 }
};
-CGEN_KEYWORD ms1_cgen_opval_msys_syms =
+CGEN_KEYWORD mt_cgen_opval_msys_syms =
{
- & ms1_cgen_opval_msys_syms_entries[0],
+ & mt_cgen_opval_msys_syms_entries[0],
2,
0, 0, 0, 0, ""
};
-static CGEN_KEYWORD_ENTRY ms1_cgen_opval_h_spr_entries[] =
+static CGEN_KEYWORD_ENTRY mt_cgen_opval_h_spr_entries[] =
{
{ "R0", 0, {0, {{{0, 0}}}}, 0, 0 },
{ "R1", 1, {0, {{{0, 0}}}}, 0, 0 },
{ "ira", 15, {0, {{{0, 0}}}}, 0, 0 }
};
-CGEN_KEYWORD ms1_cgen_opval_h_spr =
+CGEN_KEYWORD mt_cgen_opval_h_spr =
{
- & ms1_cgen_opval_h_spr_entries[0],
+ & mt_cgen_opval_h_spr_entries[0],
20,
0, 0, 0, 0, ""
};
#define A(a) (1 << CGEN_HW_/**/a)
#endif
-const CGEN_HW_ENTRY ms1_cgen_hw_table[] =
+const CGEN_HW_ENTRY mt_cgen_hw_table[] =
{
{ "h-memory", HW_H_MEMORY, CGEN_ASM_NONE, 0, { 0, { { { (1<<MACH_BASE), 0 } } } } },
{ "h-sint", HW_H_SINT, CGEN_ASM_NONE, 0, { 0, { { { (1<<MACH_BASE), 0 } } } } },
{ "h-uint", HW_H_UINT, CGEN_ASM_NONE, 0, { 0, { { { (1<<MACH_BASE), 0 } } } } },
{ "h-addr", HW_H_ADDR, CGEN_ASM_NONE, 0, { 0, { { { (1<<MACH_BASE), 0 } } } } },
{ "h-iaddr", HW_H_IADDR, CGEN_ASM_NONE, 0, { 0, { { { (1<<MACH_BASE), 0 } } } } },
- { "h-spr", HW_H_SPR, CGEN_ASM_KEYWORD, (PTR) & ms1_cgen_opval_h_spr, { 0, { { { (1<<MACH_BASE), 0 } } } } },
+ { "h-spr", HW_H_SPR, CGEN_ASM_KEYWORD, (PTR) & mt_cgen_opval_h_spr, { 0, { { { (1<<MACH_BASE), 0 } } } } },
{ "h-pc", HW_H_PC, CGEN_ASM_NONE, 0, { 0|A(PROFILE)|A(PC), { { { (1<<MACH_BASE), 0 } } } } },
{ 0, 0, CGEN_ASM_NONE, 0, { 0, { { { (1<<MACH_BASE), 0 } } } } }
};
#define A(a) (1 << CGEN_IFLD_/**/a)
#endif
-const CGEN_IFLD ms1_cgen_ifld_table[] =
+const CGEN_IFLD mt_cgen_ifld_table[] =
{
- { MS1_F_NIL, "f-nil", 0, 0, 0, 0, { 0, { { { (1<<MACH_BASE), 0 } } } } },
- { MS1_F_ANYOF, "f-anyof", 0, 0, 0, 0, { 0, { { { (1<<MACH_BASE), 0 } } } } },
- { MS1_F_MSYS, "f-msys", 0, 32, 31, 1, { 0, { { { (1<<MACH_BASE), 0 } } } } },
- { MS1_F_OPC, "f-opc", 0, 32, 30, 6, { 0, { { { (1<<MACH_BASE), 0 } } } } },
- { MS1_F_IMM, "f-imm", 0, 32, 24, 1, { 0, { { { (1<<MACH_BASE), 0 } } } } },
- { MS1_F_UU24, "f-uu24", 0, 32, 23, 24, { 0, { { { (1<<MACH_BASE), 0 } } } } },
- { MS1_F_SR1, "f-sr1", 0, 32, 23, 4, { 0|A(ABS_ADDR), { { { (1<<MACH_BASE), 0 } } } } },
- { MS1_F_SR2, "f-sr2", 0, 32, 19, 4, { 0|A(ABS_ADDR), { { { (1<<MACH_BASE), 0 } } } } },
- { MS1_F_DR, "f-dr", 0, 32, 19, 4, { 0|A(ABS_ADDR), { { { (1<<MACH_BASE), 0 } } } } },
- { MS1_F_DRRR, "f-drrr", 0, 32, 15, 4, { 0|A(ABS_ADDR), { { { (1<<MACH_BASE), 0 } } } } },
- { MS1_F_IMM16U, "f-imm16u", 0, 32, 15, 16, { 0, { { { (1<<MACH_BASE), 0 } } } } },
- { MS1_F_IMM16S, "f-imm16s", 0, 32, 15, 16, { 0, { { { (1<<MACH_BASE), 0 } } } } },
- { MS1_F_IMM16A, "f-imm16a", 0, 32, 15, 16, { 0|A(PCREL_ADDR), { { { (1<<MACH_BASE), 0 } } } } },
- { MS1_F_UU4A, "f-uu4a", 0, 32, 19, 4, { 0, { { { (1<<MACH_BASE), 0 } } } } },
- { MS1_F_UU4B, "f-uu4b", 0, 32, 23, 4, { 0, { { { (1<<MACH_BASE), 0 } } } } },
- { MS1_F_UU12, "f-uu12", 0, 32, 11, 12, { 0, { { { (1<<MACH_BASE), 0 } } } } },
- { MS1_F_UU8, "f-uu8", 0, 32, 15, 8, { 0, { { { (1<<MACH_BASE), 0 } } } } },
- { MS1_F_UU16, "f-uu16", 0, 32, 15, 16, { 0, { { { (1<<MACH_BASE), 0 } } } } },
- { MS1_F_UU1, "f-uu1", 0, 32, 7, 1, { 0, { { { (1<<MACH_BASE), 0 } } } } },
- { MS1_F_MSOPC, "f-msopc", 0, 32, 30, 5, { 0, { { { (1<<MACH_BASE), 0 } } } } },
- { MS1_F_UU_26_25, "f-uu-26-25", 0, 32, 25, 26, { 0, { { { (1<<MACH_BASE), 0 } } } } },
- { MS1_F_MASK, "f-mask", 0, 32, 25, 16, { 0, { { { (1<<MACH_BASE), 0 } } } } },
- { MS1_F_BANKADDR, "f-bankaddr", 0, 32, 25, 13, { 0, { { { (1<<MACH_BASE), 0 } } } } },
- { MS1_F_RDA, "f-rda", 0, 32, 25, 1, { 0, { { { (1<<MACH_BASE), 0 } } } } },
- { MS1_F_UU_2_25, "f-uu-2-25", 0, 32, 25, 2, { 0, { { { (1<<MACH_BASE), 0 } } } } },
- { MS1_F_RBBC, "f-rbbc", 0, 32, 25, 2, { 0, { { { (1<<MACH_BASE), 0 } } } } },
- { MS1_F_PERM, "f-perm", 0, 32, 25, 2, { 0, { { { (1<<MACH_BASE), 0 } } } } },
- { MS1_F_MODE, "f-mode", 0, 32, 25, 2, { 0, { { { (1<<MACH_BASE), 0 } } } } },
- { MS1_F_UU_1_24, "f-uu-1-24", 0, 32, 24, 1, { 0, { { { (1<<MACH_BASE), 0 } } } } },
- { MS1_F_WR, "f-wr", 0, 32, 24, 1, { 0, { { { (1<<MACH_BASE), 0 } } } } },
- { MS1_F_FBINCR, "f-fbincr", 0, 32, 23, 4, { 0, { { { (1<<MACH_BASE), 0 } } } } },
- { MS1_F_UU_2_23, "f-uu-2-23", 0, 32, 23, 2, { 0, { { { (1<<MACH_BASE), 0 } } } } },
- { MS1_F_XMODE, "f-xmode", 0, 32, 23, 1, { 0, { { { (1<<MACH_BASE), 0 } } } } },
- { MS1_F_A23, "f-a23", 0, 32, 23, 1, { 0, { { { (1<<MACH_BASE), 0 } } } } },
- { MS1_F_MASK1, "f-mask1", 0, 32, 22, 3, { 0, { { { (1<<MACH_BASE), 0 } } } } },
- { MS1_F_CR, "f-cr", 0, 32, 22, 3, { 0, { { { (1<<MACH_BASE), 0 } } } } },
- { MS1_F_TYPE, "f-type", 0, 32, 21, 2, { 0, { { { (1<<MACH_BASE), 0 } } } } },
- { MS1_F_INCAMT, "f-incamt", 0, 32, 19, 8, { 0, { { { (1<<MACH_BASE), 0 } } } } },
- { MS1_F_CBS, "f-cbs", 0, 32, 19, 2, { 0, { { { (1<<MACH_BASE), 0 } } } } },
- { MS1_F_UU_1_19, "f-uu-1-19", 0, 32, 19, 1, { 0, { { { (1<<MACH_BASE), 0 } } } } },
- { MS1_F_BALL, "f-ball", 0, 32, 19, 1, { 0, { { { (1<<MACH_BASE), 0 } } } } },
- { MS1_F_COLNUM, "f-colnum", 0, 32, 18, 3, { 0, { { { (1<<MACH_BASE), 0 } } } } },
- { MS1_F_BRC, "f-brc", 0, 32, 18, 3, { 0, { { { (1<<MACH_BASE), 0 } } } } },
- { MS1_F_INCR, "f-incr", 0, 32, 17, 6, { 0, { { { (1<<MACH_BASE), 0 } } } } },
- { MS1_F_FBDISP, "f-fbdisp", 0, 32, 15, 6, { 0, { { { (1<<MACH_BASE), 0 } } } } },
- { MS1_F_UU_4_15, "f-uu-4-15", 0, 32, 15, 4, { 0, { { { (1<<MACH_BASE), 0 } } } } },
- { MS1_F_LENGTH, "f-length", 0, 32, 15, 3, { 0, { { { (1<<MACH_BASE), 0 } } } } },
- { MS1_F_UU_1_15, "f-uu-1-15", 0, 32, 15, 1, { 0, { { { (1<<MACH_BASE), 0 } } } } },
- { MS1_F_RC, "f-rc", 0, 32, 15, 1, { 0, { { { (1<<MACH_BASE), 0 } } } } },
- { MS1_F_RCNUM, "f-rcnum", 0, 32, 14, 3, { 0, { { { (1<<MACH_BASE), 0 } } } } },
- { MS1_F_ROWNUM, "f-rownum", 0, 32, 14, 3, { 0, { { { (1<<MACH_BASE), 0 } } } } },
- { MS1_F_CBX, "f-cbx", 0, 32, 14, 3, { 0, { { { (1<<MACH_BASE), 0 } } } } },
- { MS1_F_ID, "f-id", 0, 32, 14, 1, { 0, { { { (1<<MACH_BASE), 0 } } } } },
- { MS1_F_SIZE, "f-size", 0, 32, 13, 14, { 0, { { { (1<<MACH_BASE), 0 } } } } },
- { MS1_F_ROWNUM1, "f-rownum1", 0, 32, 12, 3, { 0, { { { (1<<MACH_BASE), 0 } } } } },
- { MS1_F_UU_3_11, "f-uu-3-11", 0, 32, 11, 3, { 0, { { { (1<<MACH_BASE), 0 } } } } },
- { MS1_F_RC1, "f-rc1", 0, 32, 11, 1, { 0, { { { (1<<MACH_BASE), 0 } } } } },
- { MS1_F_CCB, "f-ccb", 0, 32, 11, 1, { 0, { { { (1<<MACH_BASE), 0 } } } } },
- { MS1_F_CBRB, "f-cbrb", 0, 32, 10, 1, { 0, { { { (1<<MACH_BASE), 0 } } } } },
- { MS1_F_CDB, "f-cdb", 0, 32, 10, 1, { 0, { { { (1<<MACH_BASE), 0 } } } } },
- { MS1_F_ROWNUM2, "f-rownum2", 0, 32, 9, 3, { 0, { { { (1<<MACH_BASE), 0 } } } } },
- { MS1_F_CELL, "f-cell", 0, 32, 9, 3, { 0, { { { (1<<MACH_BASE), 0 } } } } },
- { MS1_F_UU_3_9, "f-uu-3-9", 0, 32, 9, 3, { 0, { { { (1<<MACH_BASE), 0 } } } } },
- { MS1_F_CONTNUM, "f-contnum", 0, 32, 8, 9, { 0, { { { (1<<MACH_BASE), 0 } } } } },
- { MS1_F_UU_1_6, "f-uu-1-6", 0, 32, 6, 1, { 0, { { { (1<<MACH_BASE), 0 } } } } },
- { MS1_F_DUP, "f-dup", 0, 32, 6, 1, { 0, { { { (1<<MACH_BASE), 0 } } } } },
- { MS1_F_RC2, "f-rc2", 0, 32, 6, 1, { 0, { { { (1<<MACH_BASE), 0 } } } } },
- { MS1_F_CTXDISP, "f-ctxdisp", 0, 32, 5, 6, { 0, { { { (1<<MACH_BASE), 0 } } } } },
- { MS1_F_IMM16L, "f-imm16l", 0, 32, 23, 16, { 0, { { { (1<<MACH_BASE), 0 } } } } },
- { MS1_F_LOOPO, "f-loopo", 0, 32, 7, 8, { 0, { { { (1<<MACH_BASE), 0 } } } } },
- { MS1_F_CB1SEL, "f-cb1sel", 0, 32, 25, 3, { 0, { { { (1<<MACH_BASE), 0 } } } } },
- { MS1_F_CB2SEL, "f-cb2sel", 0, 32, 22, 3, { 0, { { { (1<<MACH_BASE), 0 } } } } },
- { MS1_F_CB1INCR, "f-cb1incr", 0, 32, 19, 6, { 0|A(SIGNED), { { { (1<<MACH_BASE), 0 } } } } },
- { MS1_F_CB2INCR, "f-cb2incr", 0, 32, 13, 6, { 0|A(SIGNED), { { { (1<<MACH_BASE), 0 } } } } },
- { MS1_F_RC3, "f-rc3", 0, 32, 7, 1, { 0, { { { (1<<MACH_BASE), 0 } } } } },
- { MS1_F_MSYSFRSR2, "f-msysfrsr2", 0, 32, 19, 4, { 0, { { { (1<<MACH_BASE), 0 } } } } },
- { MS1_F_BRC2, "f-brc2", 0, 32, 14, 3, { 0, { { { (1<<MACH_BASE), 0 } } } } },
- { MS1_F_BALL2, "f-ball2", 0, 32, 15, 1, { 0, { { { (1<<MACH_BASE), 0 } } } } },
+ { MT_F_NIL, "f-nil", 0, 0, 0, 0, { 0, { { { (1<<MACH_BASE), 0 } } } } },
+ { MT_F_ANYOF, "f-anyof", 0, 0, 0, 0, { 0, { { { (1<<MACH_BASE), 0 } } } } },
+ { MT_F_MSYS, "f-msys", 0, 32, 31, 1, { 0, { { { (1<<MACH_BASE), 0 } } } } },
+ { MT_F_OPC, "f-opc", 0, 32, 30, 6, { 0, { { { (1<<MACH_BASE), 0 } } } } },
+ { MT_F_IMM, "f-imm", 0, 32, 24, 1, { 0, { { { (1<<MACH_BASE), 0 } } } } },
+ { MT_F_UU24, "f-uu24", 0, 32, 23, 24, { 0, { { { (1<<MACH_BASE), 0 } } } } },
+ { MT_F_SR1, "f-sr1", 0, 32, 23, 4, { 0|A(ABS_ADDR), { { { (1<<MACH_BASE), 0 } } } } },
+ { MT_F_SR2, "f-sr2", 0, 32, 19, 4, { 0|A(ABS_ADDR), { { { (1<<MACH_BASE), 0 } } } } },
+ { MT_F_DR, "f-dr", 0, 32, 19, 4, { 0|A(ABS_ADDR), { { { (1<<MACH_BASE), 0 } } } } },
+ { MT_F_DRRR, "f-drrr", 0, 32, 15, 4, { 0|A(ABS_ADDR), { { { (1<<MACH_BASE), 0 } } } } },
+ { MT_F_IMM16U, "f-imm16u", 0, 32, 15, 16, { 0, { { { (1<<MACH_BASE), 0 } } } } },
+ { MT_F_IMM16S, "f-imm16s", 0, 32, 15, 16, { 0, { { { (1<<MACH_BASE), 0 } } } } },
+ { MT_F_IMM16A, "f-imm16a", 0, 32, 15, 16, { 0|A(PCREL_ADDR), { { { (1<<MACH_BASE), 0 } } } } },
+ { MT_F_UU4A, "f-uu4a", 0, 32, 19, 4, { 0, { { { (1<<MACH_BASE), 0 } } } } },
+ { MT_F_UU4B, "f-uu4b", 0, 32, 23, 4, { 0, { { { (1<<MACH_BASE), 0 } } } } },
+ { MT_F_UU12, "f-uu12", 0, 32, 11, 12, { 0, { { { (1<<MACH_BASE), 0 } } } } },
+ { MT_F_UU8, "f-uu8", 0, 32, 15, 8, { 0, { { { (1<<MACH_BASE), 0 } } } } },
+ { MT_F_UU16, "f-uu16", 0, 32, 15, 16, { 0, { { { (1<<MACH_BASE), 0 } } } } },
+ { MT_F_UU1, "f-uu1", 0, 32, 7, 1, { 0, { { { (1<<MACH_BASE), 0 } } } } },
+ { MT_F_MSOPC, "f-msopc", 0, 32, 30, 5, { 0, { { { (1<<MACH_BASE), 0 } } } } },
+ { MT_F_UU_26_25, "f-uu-26-25", 0, 32, 25, 26, { 0, { { { (1<<MACH_BASE), 0 } } } } },
+ { MT_F_MASK, "f-mask", 0, 32, 25, 16, { 0, { { { (1<<MACH_BASE), 0 } } } } },
+ { MT_F_BANKADDR, "f-bankaddr", 0, 32, 25, 13, { 0, { { { (1<<MACH_BASE), 0 } } } } },
+ { MT_F_RDA, "f-rda", 0, 32, 25, 1, { 0, { { { (1<<MACH_BASE), 0 } } } } },
+ { MT_F_UU_2_25, "f-uu-2-25", 0, 32, 25, 2, { 0, { { { (1<<MACH_BASE), 0 } } } } },
+ { MT_F_RBBC, "f-rbbc", 0, 32, 25, 2, { 0, { { { (1<<MACH_BASE), 0 } } } } },
+ { MT_F_PERM, "f-perm", 0, 32, 25, 2, { 0, { { { (1<<MACH_BASE), 0 } } } } },
+ { MT_F_MODE, "f-mode", 0, 32, 25, 2, { 0, { { { (1<<MACH_BASE), 0 } } } } },
+ { MT_F_UU_1_24, "f-uu-1-24", 0, 32, 24, 1, { 0, { { { (1<<MACH_BASE), 0 } } } } },
+ { MT_F_WR, "f-wr", 0, 32, 24, 1, { 0, { { { (1<<MACH_BASE), 0 } } } } },
+ { MT_F_FBINCR, "f-fbincr", 0, 32, 23, 4, { 0, { { { (1<<MACH_BASE), 0 } } } } },
+ { MT_F_UU_2_23, "f-uu-2-23", 0, 32, 23, 2, { 0, { { { (1<<MACH_BASE), 0 } } } } },
+ { MT_F_XMODE, "f-xmode", 0, 32, 23, 1, { 0, { { { (1<<MACH_BASE), 0 } } } } },
+ { MT_F_A23, "f-a23", 0, 32, 23, 1, { 0, { { { (1<<MACH_BASE), 0 } } } } },
+ { MT_F_MASK1, "f-mask1", 0, 32, 22, 3, { 0, { { { (1<<MACH_BASE), 0 } } } } },
+ { MT_F_CR, "f-cr", 0, 32, 22, 3, { 0, { { { (1<<MACH_BASE), 0 } } } } },
+ { MT_F_TYPE, "f-type", 0, 32, 21, 2, { 0, { { { (1<<MACH_BASE), 0 } } } } },
+ { MT_F_INCAMT, "f-incamt", 0, 32, 19, 8, { 0, { { { (1<<MACH_BASE), 0 } } } } },
+ { MT_F_CBS, "f-cbs", 0, 32, 19, 2, { 0, { { { (1<<MACH_BASE), 0 } } } } },
+ { MT_F_UU_1_19, "f-uu-1-19", 0, 32, 19, 1, { 0, { { { (1<<MACH_BASE), 0 } } } } },
+ { MT_F_BALL, "f-ball", 0, 32, 19, 1, { 0, { { { (1<<MACH_BASE), 0 } } } } },
+ { MT_F_COLNUM, "f-colnum", 0, 32, 18, 3, { 0, { { { (1<<MACH_BASE), 0 } } } } },
+ { MT_F_BRC, "f-brc", 0, 32, 18, 3, { 0, { { { (1<<MACH_BASE), 0 } } } } },
+ { MT_F_INCR, "f-incr", 0, 32, 17, 6, { 0, { { { (1<<MACH_BASE), 0 } } } } },
+ { MT_F_FBDISP, "f-fbdisp", 0, 32, 15, 6, { 0, { { { (1<<MACH_BASE), 0 } } } } },
+ { MT_F_UU_4_15, "f-uu-4-15", 0, 32, 15, 4, { 0, { { { (1<<MACH_BASE), 0 } } } } },
+ { MT_F_LENGTH, "f-length", 0, 32, 15, 3, { 0, { { { (1<<MACH_BASE), 0 } } } } },
+ { MT_F_UU_1_15, "f-uu-1-15", 0, 32, 15, 1, { 0, { { { (1<<MACH_BASE), 0 } } } } },
+ { MT_F_RC, "f-rc", 0, 32, 15, 1, { 0, { { { (1<<MACH_BASE), 0 } } } } },
+ { MT_F_RCNUM, "f-rcnum", 0, 32, 14, 3, { 0, { { { (1<<MACH_BASE), 0 } } } } },
+ { MT_F_ROWNUM, "f-rownum", 0, 32, 14, 3, { 0, { { { (1<<MACH_BASE), 0 } } } } },
+ { MT_F_CBX, "f-cbx", 0, 32, 14, 3, { 0, { { { (1<<MACH_BASE), 0 } } } } },
+ { MT_F_ID, "f-id", 0, 32, 14, 1, { 0, { { { (1<<MACH_BASE), 0 } } } } },
+ { MT_F_SIZE, "f-size", 0, 32, 13, 14, { 0, { { { (1<<MACH_BASE), 0 } } } } },
+ { MT_F_ROWNUM1, "f-rownum1", 0, 32, 12, 3, { 0, { { { (1<<MACH_BASE), 0 } } } } },
+ { MT_F_UU_3_11, "f-uu-3-11", 0, 32, 11, 3, { 0, { { { (1<<MACH_BASE), 0 } } } } },
+ { MT_F_RC1, "f-rc1", 0, 32, 11, 1, { 0, { { { (1<<MACH_BASE), 0 } } } } },
+ { MT_F_CCB, "f-ccb", 0, 32, 11, 1, { 0, { { { (1<<MACH_BASE), 0 } } } } },
+ { MT_F_CBRB, "f-cbrb", 0, 32, 10, 1, { 0, { { { (1<<MACH_BASE), 0 } } } } },
+ { MT_F_CDB, "f-cdb", 0, 32, 10, 1, { 0, { { { (1<<MACH_BASE), 0 } } } } },
+ { MT_F_ROWNUM2, "f-rownum2", 0, 32, 9, 3, { 0, { { { (1<<MACH_BASE), 0 } } } } },
+ { MT_F_CELL, "f-cell", 0, 32, 9, 3, { 0, { { { (1<<MACH_BASE), 0 } } } } },
+ { MT_F_UU_3_9, "f-uu-3-9", 0, 32, 9, 3, { 0, { { { (1<<MACH_BASE), 0 } } } } },
+ { MT_F_CONTNUM, "f-contnum", 0, 32, 8, 9, { 0, { { { (1<<MACH_BASE), 0 } } } } },
+ { MT_F_UU_1_6, "f-uu-1-6", 0, 32, 6, 1, { 0, { { { (1<<MACH_BASE), 0 } } } } },
+ { MT_F_DUP, "f-dup", 0, 32, 6, 1, { 0, { { { (1<<MACH_BASE), 0 } } } } },
+ { MT_F_RC2, "f-rc2", 0, 32, 6, 1, { 0, { { { (1<<MACH_BASE), 0 } } } } },
+ { MT_F_CTXDISP, "f-ctxdisp", 0, 32, 5, 6, { 0, { { { (1<<MACH_BASE), 0 } } } } },
+ { MT_F_IMM16L, "f-imm16l", 0, 32, 23, 16, { 0, { { { (1<<MACH_BASE), 0 } } } } },
+ { MT_F_LOOPO, "f-loopo", 0, 32, 7, 8, { 0, { { { (1<<MACH_BASE), 0 } } } } },
+ { MT_F_CB1SEL, "f-cb1sel", 0, 32, 25, 3, { 0, { { { (1<<MACH_BASE), 0 } } } } },
+ { MT_F_CB2SEL, "f-cb2sel", 0, 32, 22, 3, { 0, { { { (1<<MACH_BASE), 0 } } } } },
+ { MT_F_CB1INCR, "f-cb1incr", 0, 32, 19, 6, { 0|A(SIGNED), { { { (1<<MACH_BASE), 0 } } } } },
+ { MT_F_CB2INCR, "f-cb2incr", 0, 32, 13, 6, { 0|A(SIGNED), { { { (1<<MACH_BASE), 0 } } } } },
+ { MT_F_RC3, "f-rc3", 0, 32, 7, 1, { 0, { { { (1<<MACH_BASE), 0 } } } } },
+ { MT_F_MSYSFRSR2, "f-msysfrsr2", 0, 32, 19, 4, { 0, { { { (1<<MACH_BASE), 0 } } } } },
+ { MT_F_BRC2, "f-brc2", 0, 32, 14, 3, { 0, { { { (1<<MACH_BASE), 0 } } } } },
+ { MT_F_BALL2, "f-ball2", 0, 32, 15, 1, { 0, { { { (1<<MACH_BASE), 0 } } } } },
{ 0, 0, 0, 0, 0, 0, { 0, { { { (1<<MACH_BASE), 0 } } } } }
};
#define A(a) (1 << CGEN_OPERAND_/**/a)
#endif
#if defined (__STDC__) || defined (ALMOST_STDC) || defined (HAVE_STRINGIZE)
-#define OPERAND(op) MS1_OPERAND_##op
+#define OPERAND(op) MT_OPERAND_##op
#else
-#define OPERAND(op) MS1_OPERAND_/**/op
+#define OPERAND(op) MT_OPERAND_/**/op
#endif
-const CGEN_OPERAND ms1_cgen_operand_table[] =
+const CGEN_OPERAND mt_cgen_operand_table[] =
{
/* pc: program counter */
- { "pc", MS1_OPERAND_PC, HW_H_PC, 0, 0,
- { 0, { (const PTR) &ms1_cgen_ifld_table[MS1_F_NIL] } },
+ { "pc", MT_OPERAND_PC, HW_H_PC, 0, 0,
+ { 0, { (const PTR) &mt_cgen_ifld_table[MT_F_NIL] } },
{ 0|A(SEM_ONLY), { { { (1<<MACH_BASE), 0 } } } } },
/* frsr1: register */
- { "frsr1", MS1_OPERAND_FRSR1, HW_H_SPR, 23, 4,
- { 0, { (const PTR) &ms1_cgen_ifld_table[MS1_F_SR1] } },
+ { "frsr1", MT_OPERAND_FRSR1, HW_H_SPR, 23, 4,
+ { 0, { (const PTR) &mt_cgen_ifld_table[MT_F_SR1] } },
{ 0|A(ABS_ADDR), { { { (1<<MACH_BASE), 0 } } } } },
/* frsr2: register */
- { "frsr2", MS1_OPERAND_FRSR2, HW_H_SPR, 19, 4,
- { 0, { (const PTR) &ms1_cgen_ifld_table[MS1_F_SR2] } },
+ { "frsr2", MT_OPERAND_FRSR2, HW_H_SPR, 19, 4,
+ { 0, { (const PTR) &mt_cgen_ifld_table[MT_F_SR2] } },
{ 0|A(ABS_ADDR), { { { (1<<MACH_BASE), 0 } } } } },
/* frdr: register */
- { "frdr", MS1_OPERAND_FRDR, HW_H_SPR, 19, 4,
- { 0, { (const PTR) &ms1_cgen_ifld_table[MS1_F_DR] } },
+ { "frdr", MT_OPERAND_FRDR, HW_H_SPR, 19, 4,
+ { 0, { (const PTR) &mt_cgen_ifld_table[MT_F_DR] } },
{ 0|A(ABS_ADDR), { { { (1<<MACH_BASE), 0 } } } } },
/* frdrrr: register */
- { "frdrrr", MS1_OPERAND_FRDRRR, HW_H_SPR, 15, 4,
- { 0, { (const PTR) &ms1_cgen_ifld_table[MS1_F_DRRR] } },
+ { "frdrrr", MT_OPERAND_FRDRRR, HW_H_SPR, 15, 4,
+ { 0, { (const PTR) &mt_cgen_ifld_table[MT_F_DRRR] } },
{ 0|A(ABS_ADDR), { { { (1<<MACH_BASE), 0 } } } } },
/* imm16: immediate value - sign extd */
- { "imm16", MS1_OPERAND_IMM16, HW_H_SINT, 15, 16,
- { 0, { (const PTR) &ms1_cgen_ifld_table[MS1_F_IMM16S] } },
+ { "imm16", MT_OPERAND_IMM16, HW_H_SINT, 15, 16,
+ { 0, { (const PTR) &mt_cgen_ifld_table[MT_F_IMM16S] } },
{ 0, { { { (1<<MACH_BASE), 0 } } } } },
/* imm16z: immediate value - zero extd */
- { "imm16z", MS1_OPERAND_IMM16Z, HW_H_UINT, 15, 16,
- { 0, { (const PTR) &ms1_cgen_ifld_table[MS1_F_IMM16U] } },
+ { "imm16z", MT_OPERAND_IMM16Z, HW_H_UINT, 15, 16,
+ { 0, { (const PTR) &mt_cgen_ifld_table[MT_F_IMM16U] } },
{ 0, { { { (1<<MACH_BASE), 0 } } } } },
/* imm16o: immediate value */
- { "imm16o", MS1_OPERAND_IMM16O, HW_H_UINT, 15, 16,
- { 0, { (const PTR) &ms1_cgen_ifld_table[MS1_F_IMM16S] } },
+ { "imm16o", MT_OPERAND_IMM16O, HW_H_UINT, 15, 16,
+ { 0, { (const PTR) &mt_cgen_ifld_table[MT_F_IMM16S] } },
{ 0|A(PCREL_ADDR), { { { (1<<MACH_BASE), 0 } } } } },
/* rc: rc */
- { "rc", MS1_OPERAND_RC, HW_H_UINT, 15, 1,
- { 0, { (const PTR) &ms1_cgen_ifld_table[MS1_F_RC] } },
+ { "rc", MT_OPERAND_RC, HW_H_UINT, 15, 1,
+ { 0, { (const PTR) &mt_cgen_ifld_table[MT_F_RC] } },
{ 0, { { { (1<<MACH_BASE), 0 } } } } },
/* rcnum: rcnum */
- { "rcnum", MS1_OPERAND_RCNUM, HW_H_UINT, 14, 3,
- { 0, { (const PTR) &ms1_cgen_ifld_table[MS1_F_RCNUM] } },
+ { "rcnum", MT_OPERAND_RCNUM, HW_H_UINT, 14, 3,
+ { 0, { (const PTR) &mt_cgen_ifld_table[MT_F_RCNUM] } },
{ 0, { { { (1<<MACH_BASE), 0 } } } } },
/* contnum: context number */
- { "contnum", MS1_OPERAND_CONTNUM, HW_H_UINT, 8, 9,
- { 0, { (const PTR) &ms1_cgen_ifld_table[MS1_F_CONTNUM] } },
+ { "contnum", MT_OPERAND_CONTNUM, HW_H_UINT, 8, 9,
+ { 0, { (const PTR) &mt_cgen_ifld_table[MT_F_CONTNUM] } },
{ 0, { { { (1<<MACH_BASE), 0 } } } } },
/* rbbc: omega network configuration */
- { "rbbc", MS1_OPERAND_RBBC, HW_H_UINT, 25, 2,
- { 0, { (const PTR) &ms1_cgen_ifld_table[MS1_F_RBBC] } },
+ { "rbbc", MT_OPERAND_RBBC, HW_H_UINT, 25, 2,
+ { 0, { (const PTR) &mt_cgen_ifld_table[MT_F_RBBC] } },
{ 0, { { { (1<<MACH_BASE), 0 } } } } },
/* colnum: column number */
- { "colnum", MS1_OPERAND_COLNUM, HW_H_UINT, 18, 3,
- { 0, { (const PTR) &ms1_cgen_ifld_table[MS1_F_COLNUM] } },
+ { "colnum", MT_OPERAND_COLNUM, HW_H_UINT, 18, 3,
+ { 0, { (const PTR) &mt_cgen_ifld_table[MT_F_COLNUM] } },
{ 0, { { { (1<<MACH_BASE), 0 } } } } },
/* rownum: row number */
- { "rownum", MS1_OPERAND_ROWNUM, HW_H_UINT, 14, 3,
- { 0, { (const PTR) &ms1_cgen_ifld_table[MS1_F_ROWNUM] } },
+ { "rownum", MT_OPERAND_ROWNUM, HW_H_UINT, 14, 3,
+ { 0, { (const PTR) &mt_cgen_ifld_table[MT_F_ROWNUM] } },
{ 0, { { { (1<<MACH_BASE), 0 } } } } },
/* rownum1: row number */
- { "rownum1", MS1_OPERAND_ROWNUM1, HW_H_UINT, 12, 3,
- { 0, { (const PTR) &ms1_cgen_ifld_table[MS1_F_ROWNUM1] } },
+ { "rownum1", MT_OPERAND_ROWNUM1, HW_H_UINT, 12, 3,
+ { 0, { (const PTR) &mt_cgen_ifld_table[MT_F_ROWNUM1] } },
{ 0, { { { (1<<MACH_BASE), 0 } } } } },
/* rownum2: row number */
- { "rownum2", MS1_OPERAND_ROWNUM2, HW_H_UINT, 9, 3,
- { 0, { (const PTR) &ms1_cgen_ifld_table[MS1_F_ROWNUM2] } },
+ { "rownum2", MT_OPERAND_ROWNUM2, HW_H_UINT, 9, 3,
+ { 0, { (const PTR) &mt_cgen_ifld_table[MT_F_ROWNUM2] } },
{ 0, { { { (1<<MACH_BASE), 0 } } } } },
/* rc1: rc1 */
- { "rc1", MS1_OPERAND_RC1, HW_H_UINT, 11, 1,
- { 0, { (const PTR) &ms1_cgen_ifld_table[MS1_F_RC1] } },
+ { "rc1", MT_OPERAND_RC1, HW_H_UINT, 11, 1,
+ { 0, { (const PTR) &mt_cgen_ifld_table[MT_F_RC1] } },
{ 0, { { { (1<<MACH_BASE), 0 } } } } },
/* rc2: rc2 */
- { "rc2", MS1_OPERAND_RC2, HW_H_UINT, 6, 1,
- { 0, { (const PTR) &ms1_cgen_ifld_table[MS1_F_RC2] } },
+ { "rc2", MT_OPERAND_RC2, HW_H_UINT, 6, 1,
+ { 0, { (const PTR) &mt_cgen_ifld_table[MT_F_RC2] } },
{ 0, { { { (1<<MACH_BASE), 0 } } } } },
/* cbrb: data-bus orientation */
- { "cbrb", MS1_OPERAND_CBRB, HW_H_UINT, 10, 1,
- { 0, { (const PTR) &ms1_cgen_ifld_table[MS1_F_CBRB] } },
+ { "cbrb", MT_OPERAND_CBRB, HW_H_UINT, 10, 1,
+ { 0, { (const PTR) &mt_cgen_ifld_table[MT_F_CBRB] } },
{ 0, { { { (1<<MACH_BASE), 0 } } } } },
/* cell: cell */
- { "cell", MS1_OPERAND_CELL, HW_H_UINT, 9, 3,
- { 0, { (const PTR) &ms1_cgen_ifld_table[MS1_F_CELL] } },
+ { "cell", MT_OPERAND_CELL, HW_H_UINT, 9, 3,
+ { 0, { (const PTR) &mt_cgen_ifld_table[MT_F_CELL] } },
{ 0, { { { (1<<MACH_BASE), 0 } } } } },
/* dup: dup */
- { "dup", MS1_OPERAND_DUP, HW_H_UINT, 6, 1,
- { 0, { (const PTR) &ms1_cgen_ifld_table[MS1_F_DUP] } },
+ { "dup", MT_OPERAND_DUP, HW_H_UINT, 6, 1,
+ { 0, { (const PTR) &mt_cgen_ifld_table[MT_F_DUP] } },
{ 0, { { { (1<<MACH_BASE), 0 } } } } },
/* ctxdisp: context displacement */
- { "ctxdisp", MS1_OPERAND_CTXDISP, HW_H_UINT, 5, 6,
- { 0, { (const PTR) &ms1_cgen_ifld_table[MS1_F_CTXDISP] } },
+ { "ctxdisp", MT_OPERAND_CTXDISP, HW_H_UINT, 5, 6,
+ { 0, { (const PTR) &mt_cgen_ifld_table[MT_F_CTXDISP] } },
{ 0, { { { (1<<MACH_BASE), 0 } } } } },
/* fbdisp: frame buffer displacement */
- { "fbdisp", MS1_OPERAND_FBDISP, HW_H_UINT, 15, 6,
- { 0, { (const PTR) &ms1_cgen_ifld_table[MS1_F_FBDISP] } },
+ { "fbdisp", MT_OPERAND_FBDISP, HW_H_UINT, 15, 6,
+ { 0, { (const PTR) &mt_cgen_ifld_table[MT_F_FBDISP] } },
{ 0, { { { (1<<MACH_BASE), 0 } } } } },
/* type: type */
- { "type", MS1_OPERAND_TYPE, HW_H_UINT, 21, 2,
- { 0, { (const PTR) &ms1_cgen_ifld_table[MS1_F_TYPE] } },
+ { "type", MT_OPERAND_TYPE, HW_H_UINT, 21, 2,
+ { 0, { (const PTR) &mt_cgen_ifld_table[MT_F_TYPE] } },
{ 0, { { { (1<<MACH_BASE), 0 } } } } },
/* mask: mask */
- { "mask", MS1_OPERAND_MASK, HW_H_UINT, 25, 16,
- { 0, { (const PTR) &ms1_cgen_ifld_table[MS1_F_MASK] } },
+ { "mask", MT_OPERAND_MASK, HW_H_UINT, 25, 16,
+ { 0, { (const PTR) &mt_cgen_ifld_table[MT_F_MASK] } },
{ 0, { { { (1<<MACH_BASE), 0 } } } } },
/* bankaddr: bank address */
- { "bankaddr", MS1_OPERAND_BANKADDR, HW_H_UINT, 25, 13,
- { 0, { (const PTR) &ms1_cgen_ifld_table[MS1_F_BANKADDR] } },
+ { "bankaddr", MT_OPERAND_BANKADDR, HW_H_UINT, 25, 13,
+ { 0, { (const PTR) &mt_cgen_ifld_table[MT_F_BANKADDR] } },
{ 0, { { { (1<<MACH_BASE), 0 } } } } },
/* incamt: increment amount */
- { "incamt", MS1_OPERAND_INCAMT, HW_H_UINT, 19, 8,
- { 0, { (const PTR) &ms1_cgen_ifld_table[MS1_F_INCAMT] } },
+ { "incamt", MT_OPERAND_INCAMT, HW_H_UINT, 19, 8,
+ { 0, { (const PTR) &mt_cgen_ifld_table[MT_F_INCAMT] } },
{ 0, { { { (1<<MACH_BASE), 0 } } } } },
/* xmode: xmode */
- { "xmode", MS1_OPERAND_XMODE, HW_H_UINT, 23, 1,
- { 0, { (const PTR) &ms1_cgen_ifld_table[MS1_F_XMODE] } },
+ { "xmode", MT_OPERAND_XMODE, HW_H_UINT, 23, 1,
+ { 0, { (const PTR) &mt_cgen_ifld_table[MT_F_XMODE] } },
{ 0, { { { (1<<MACH_BASE), 0 } } } } },
/* mask1: mask1 */
- { "mask1", MS1_OPERAND_MASK1, HW_H_UINT, 22, 3,
- { 0, { (const PTR) &ms1_cgen_ifld_table[MS1_F_MASK1] } },
+ { "mask1", MT_OPERAND_MASK1, HW_H_UINT, 22, 3,
+ { 0, { (const PTR) &mt_cgen_ifld_table[MT_F_MASK1] } },
{ 0, { { { (1<<MACH_BASE), 0 } } } } },
/* ball: b_all */
- { "ball", MS1_OPERAND_BALL, HW_H_UINT, 19, 1,
- { 0, { (const PTR) &ms1_cgen_ifld_table[MS1_F_BALL] } },
+ { "ball", MT_OPERAND_BALL, HW_H_UINT, 19, 1,
+ { 0, { (const PTR) &mt_cgen_ifld_table[MT_F_BALL] } },
{ 0, { { { (1<<MACH_BASE), 0 } } } } },
/* brc: b_r_c */
- { "brc", MS1_OPERAND_BRC, HW_H_UINT, 18, 3,
- { 0, { (const PTR) &ms1_cgen_ifld_table[MS1_F_BRC] } },
+ { "brc", MT_OPERAND_BRC, HW_H_UINT, 18, 3,
+ { 0, { (const PTR) &mt_cgen_ifld_table[MT_F_BRC] } },
{ 0, { { { (1<<MACH_BASE), 0 } } } } },
/* rda: rd */
- { "rda", MS1_OPERAND_RDA, HW_H_UINT, 25, 1,
- { 0, { (const PTR) &ms1_cgen_ifld_table[MS1_F_RDA] } },
+ { "rda", MT_OPERAND_RDA, HW_H_UINT, 25, 1,
+ { 0, { (const PTR) &mt_cgen_ifld_table[MT_F_RDA] } },
{ 0, { { { (1<<MACH_BASE), 0 } } } } },
/* wr: wr */
- { "wr", MS1_OPERAND_WR, HW_H_UINT, 24, 1,
- { 0, { (const PTR) &ms1_cgen_ifld_table[MS1_F_WR] } },
+ { "wr", MT_OPERAND_WR, HW_H_UINT, 24, 1,
+ { 0, { (const PTR) &mt_cgen_ifld_table[MT_F_WR] } },
{ 0, { { { (1<<MACH_BASE), 0 } } } } },
/* ball2: b_all2 */
- { "ball2", MS1_OPERAND_BALL2, HW_H_UINT, 15, 1,
- { 0, { (const PTR) &ms1_cgen_ifld_table[MS1_F_BALL2] } },
+ { "ball2", MT_OPERAND_BALL2, HW_H_UINT, 15, 1,
+ { 0, { (const PTR) &mt_cgen_ifld_table[MT_F_BALL2] } },
{ 0, { { { (1<<MACH_BASE), 0 } } } } },
/* brc2: b_r_c2 */
- { "brc2", MS1_OPERAND_BRC2, HW_H_UINT, 14, 3,
- { 0, { (const PTR) &ms1_cgen_ifld_table[MS1_F_BRC2] } },
+ { "brc2", MT_OPERAND_BRC2, HW_H_UINT, 14, 3,
+ { 0, { (const PTR) &mt_cgen_ifld_table[MT_F_BRC2] } },
{ 0, { { { (1<<MACH_BASE), 0 } } } } },
/* perm: perm */
- { "perm", MS1_OPERAND_PERM, HW_H_UINT, 25, 2,
- { 0, { (const PTR) &ms1_cgen_ifld_table[MS1_F_PERM] } },
+ { "perm", MT_OPERAND_PERM, HW_H_UINT, 25, 2,
+ { 0, { (const PTR) &mt_cgen_ifld_table[MT_F_PERM] } },
{ 0, { { { (1<<MACH_BASE), 0 } } } } },
/* a23: a23 */
- { "a23", MS1_OPERAND_A23, HW_H_UINT, 23, 1,
- { 0, { (const PTR) &ms1_cgen_ifld_table[MS1_F_A23] } },
+ { "a23", MT_OPERAND_A23, HW_H_UINT, 23, 1,
+ { 0, { (const PTR) &mt_cgen_ifld_table[MT_F_A23] } },
{ 0, { { { (1<<MACH_BASE), 0 } } } } },
/* cr: c-r */
- { "cr", MS1_OPERAND_CR, HW_H_UINT, 22, 3,
- { 0, { (const PTR) &ms1_cgen_ifld_table[MS1_F_CR] } },
+ { "cr", MT_OPERAND_CR, HW_H_UINT, 22, 3,
+ { 0, { (const PTR) &mt_cgen_ifld_table[MT_F_CR] } },
{ 0, { { { (1<<MACH_BASE), 0 } } } } },
/* cbs: cbs */
- { "cbs", MS1_OPERAND_CBS, HW_H_UINT, 19, 2,
- { 0, { (const PTR) &ms1_cgen_ifld_table[MS1_F_CBS] } },
+ { "cbs", MT_OPERAND_CBS, HW_H_UINT, 19, 2,
+ { 0, { (const PTR) &mt_cgen_ifld_table[MT_F_CBS] } },
{ 0, { { { (1<<MACH_BASE), 0 } } } } },
/* incr: incr */
- { "incr", MS1_OPERAND_INCR, HW_H_UINT, 17, 6,
- { 0, { (const PTR) &ms1_cgen_ifld_table[MS1_F_INCR] } },
+ { "incr", MT_OPERAND_INCR, HW_H_UINT, 17, 6,
+ { 0, { (const PTR) &mt_cgen_ifld_table[MT_F_INCR] } },
{ 0, { { { (1<<MACH_BASE), 0 } } } } },
/* length: length */
- { "length", MS1_OPERAND_LENGTH, HW_H_UINT, 15, 3,
- { 0, { (const PTR) &ms1_cgen_ifld_table[MS1_F_LENGTH] } },
+ { "length", MT_OPERAND_LENGTH, HW_H_UINT, 15, 3,
+ { 0, { (const PTR) &mt_cgen_ifld_table[MT_F_LENGTH] } },
{ 0, { { { (1<<MACH_BASE), 0 } } } } },
/* cbx: cbx */
- { "cbx", MS1_OPERAND_CBX, HW_H_UINT, 14, 3,
- { 0, { (const PTR) &ms1_cgen_ifld_table[MS1_F_CBX] } },
+ { "cbx", MT_OPERAND_CBX, HW_H_UINT, 14, 3,
+ { 0, { (const PTR) &mt_cgen_ifld_table[MT_F_CBX] } },
{ 0, { { { (1<<MACH_BASE), 0 } } } } },
/* ccb: ccb */
- { "ccb", MS1_OPERAND_CCB, HW_H_UINT, 11, 1,
- { 0, { (const PTR) &ms1_cgen_ifld_table[MS1_F_CCB] } },
+ { "ccb", MT_OPERAND_CCB, HW_H_UINT, 11, 1,
+ { 0, { (const PTR) &mt_cgen_ifld_table[MT_F_CCB] } },
{ 0, { { { (1<<MACH_BASE), 0 } } } } },
/* cdb: cdb */
- { "cdb", MS1_OPERAND_CDB, HW_H_UINT, 10, 1,
- { 0, { (const PTR) &ms1_cgen_ifld_table[MS1_F_CDB] } },
+ { "cdb", MT_OPERAND_CDB, HW_H_UINT, 10, 1,
+ { 0, { (const PTR) &mt_cgen_ifld_table[MT_F_CDB] } },
{ 0, { { { (1<<MACH_BASE), 0 } } } } },
/* mode: mode */
- { "mode", MS1_OPERAND_MODE, HW_H_UINT, 25, 2,
- { 0, { (const PTR) &ms1_cgen_ifld_table[MS1_F_MODE] } },
+ { "mode", MT_OPERAND_MODE, HW_H_UINT, 25, 2,
+ { 0, { (const PTR) &mt_cgen_ifld_table[MT_F_MODE] } },
{ 0, { { { (1<<MACH_BASE), 0 } } } } },
/* id: i/d */
- { "id", MS1_OPERAND_ID, HW_H_UINT, 14, 1,
- { 0, { (const PTR) &ms1_cgen_ifld_table[MS1_F_ID] } },
+ { "id", MT_OPERAND_ID, HW_H_UINT, 14, 1,
+ { 0, { (const PTR) &mt_cgen_ifld_table[MT_F_ID] } },
{ 0, { { { (1<<MACH_BASE), 0 } } } } },
/* size: size */
- { "size", MS1_OPERAND_SIZE, HW_H_UINT, 13, 14,
- { 0, { (const PTR) &ms1_cgen_ifld_table[MS1_F_SIZE] } },
+ { "size", MT_OPERAND_SIZE, HW_H_UINT, 13, 14,
+ { 0, { (const PTR) &mt_cgen_ifld_table[MT_F_SIZE] } },
{ 0, { { { (1<<MACH_BASE), 0 } } } } },
/* fbincr: fb incr */
- { "fbincr", MS1_OPERAND_FBINCR, HW_H_UINT, 23, 4,
- { 0, { (const PTR) &ms1_cgen_ifld_table[MS1_F_FBINCR] } },
+ { "fbincr", MT_OPERAND_FBINCR, HW_H_UINT, 23, 4,
+ { 0, { (const PTR) &mt_cgen_ifld_table[MT_F_FBINCR] } },
{ 0, { { { (1<<MACH_BASE), 0 } } } } },
/* loopsize: immediate value */
- { "loopsize", MS1_OPERAND_LOOPSIZE, HW_H_UINT, 7, 8,
- { 0, { (const PTR) &ms1_cgen_ifld_table[MS1_F_LOOPO] } },
+ { "loopsize", MT_OPERAND_LOOPSIZE, HW_H_UINT, 7, 8,
+ { 0, { (const PTR) &mt_cgen_ifld_table[MT_F_LOOPO] } },
{ 0|A(PCREL_ADDR), { { { (1<<MACH_MS2), 0 } } } } },
/* imm16l: immediate value */
- { "imm16l", MS1_OPERAND_IMM16L, HW_H_UINT, 23, 16,
- { 0, { (const PTR) &ms1_cgen_ifld_table[MS1_F_IMM16L] } },
+ { "imm16l", MT_OPERAND_IMM16L, HW_H_UINT, 23, 16,
+ { 0, { (const PTR) &mt_cgen_ifld_table[MT_F_IMM16L] } },
{ 0, { { { (1<<MACH_MS2), 0 } } } } },
/* rc3: rc3 */
- { "rc3", MS1_OPERAND_RC3, HW_H_UINT, 7, 1,
- { 0, { (const PTR) &ms1_cgen_ifld_table[MS1_F_RC3] } },
+ { "rc3", MT_OPERAND_RC3, HW_H_UINT, 7, 1,
+ { 0, { (const PTR) &mt_cgen_ifld_table[MT_F_RC3] } },
{ 0, { { { (1<<MACH_MS2), 0 } } } } },
/* cb1sel: cb1sel */
- { "cb1sel", MS1_OPERAND_CB1SEL, HW_H_UINT, 25, 3,
- { 0, { (const PTR) &ms1_cgen_ifld_table[MS1_F_CB1SEL] } },
+ { "cb1sel", MT_OPERAND_CB1SEL, HW_H_UINT, 25, 3,
+ { 0, { (const PTR) &mt_cgen_ifld_table[MT_F_CB1SEL] } },
{ 0, { { { (1<<MACH_MS2), 0 } } } } },
/* cb2sel: cb2sel */
- { "cb2sel", MS1_OPERAND_CB2SEL, HW_H_UINT, 22, 3,
- { 0, { (const PTR) &ms1_cgen_ifld_table[MS1_F_CB2SEL] } },
+ { "cb2sel", MT_OPERAND_CB2SEL, HW_H_UINT, 22, 3,
+ { 0, { (const PTR) &mt_cgen_ifld_table[MT_F_CB2SEL] } },
{ 0, { { { (1<<MACH_MS2), 0 } } } } },
/* cb1incr: cb1incr */
- { "cb1incr", MS1_OPERAND_CB1INCR, HW_H_SINT, 19, 6,
- { 0, { (const PTR) &ms1_cgen_ifld_table[MS1_F_CB1INCR] } },
+ { "cb1incr", MT_OPERAND_CB1INCR, HW_H_SINT, 19, 6,
+ { 0, { (const PTR) &mt_cgen_ifld_table[MT_F_CB1INCR] } },
{ 0|A(SIGNED), { { { (1<<MACH_MS2), 0 } } } } },
/* cb2incr: cb2incr */
- { "cb2incr", MS1_OPERAND_CB2INCR, HW_H_SINT, 13, 6,
- { 0, { (const PTR) &ms1_cgen_ifld_table[MS1_F_CB2INCR] } },
+ { "cb2incr", MT_OPERAND_CB2INCR, HW_H_SINT, 13, 6,
+ { 0, { (const PTR) &mt_cgen_ifld_table[MT_F_CB2INCR] } },
{ 0|A(SIGNED), { { { (1<<MACH_MS2), 0 } } } } },
/* sentinel */
{ 0, 0, 0, 0, 0,
#define A(a) (1 << CGEN_INSN_/**/a)
#endif
-static const CGEN_IBASE ms1_cgen_insn_table[MAX_INSNS] =
+static const CGEN_IBASE mt_cgen_insn_table[MAX_INSNS] =
{
/* Special null first entry.
A `num' value of zero is thus invalid.
{ 0, 0, 0, 0, { 0, { { { (1<<MACH_BASE), 0 } } } } },
/* add $frdrrr,$frsr1,$frsr2 */
{
- MS1_INSN_ADD, "add", "add", 32,
+ MT_INSN_ADD, "add", "add", 32,
{ 0|A(USES_FRSR2)|A(USES_FRSR1)|A(USES_FRDRRR)|A(AL_INSN), { { { (1<<MACH_BASE), 0 } } } }
},
/* addu $frdrrr,$frsr1,$frsr2 */
{
- MS1_INSN_ADDU, "addu", "addu", 32,
+ MT_INSN_ADDU, "addu", "addu", 32,
{ 0|A(USES_FRSR2)|A(USES_FRSR1)|A(USES_FRDRRR)|A(AL_INSN), { { { (1<<MACH_BASE), 0 } } } }
},
/* addi $frdr,$frsr1,#$imm16 */
{
- MS1_INSN_ADDI, "addi", "addi", 32,
+ MT_INSN_ADDI, "addi", "addi", 32,
{ 0|A(USES_FRSR1)|A(USES_FRDR)|A(AL_INSN), { { { (1<<MACH_BASE), 0 } } } }
},
/* addui $frdr,$frsr1,#$imm16z */
{
- MS1_INSN_ADDUI, "addui", "addui", 32,
+ MT_INSN_ADDUI, "addui", "addui", 32,
{ 0|A(USES_FRSR1)|A(USES_FRDR)|A(AL_INSN), { { { (1<<MACH_BASE), 0 } } } }
},
/* sub $frdrrr,$frsr1,$frsr2 */
{
- MS1_INSN_SUB, "sub", "sub", 32,
+ MT_INSN_SUB, "sub", "sub", 32,
{ 0|A(USES_FRSR2)|A(USES_FRSR1)|A(USES_FRDRRR)|A(AL_INSN), { { { (1<<MACH_BASE), 0 } } } }
},
/* subu $frdrrr,$frsr1,$frsr2 */
{
- MS1_INSN_SUBU, "subu", "subu", 32,
+ MT_INSN_SUBU, "subu", "subu", 32,
{ 0|A(USES_FRSR2)|A(USES_FRSR1)|A(USES_FRDRRR)|A(AL_INSN), { { { (1<<MACH_BASE), 0 } } } }
},
/* subi $frdr,$frsr1,#$imm16 */
{
- MS1_INSN_SUBI, "subi", "subi", 32,
+ MT_INSN_SUBI, "subi", "subi", 32,
{ 0|A(USES_FRSR1)|A(USES_FRDR)|A(AL_INSN), { { { (1<<MACH_BASE), 0 } } } }
},
/* subui $frdr,$frsr1,#$imm16z */
{
- MS1_INSN_SUBUI, "subui", "subui", 32,
+ MT_INSN_SUBUI, "subui", "subui", 32,
{ 0|A(USES_FRSR1)|A(USES_FRDR)|A(AL_INSN), { { { (1<<MACH_BASE), 0 } } } }
},
/* mul $frdrrr,$frsr1,$frsr2 */
{
- MS1_INSN_MUL, "mul", "mul", 32,
+ MT_INSN_MUL, "mul", "mul", 32,
{ 0|A(USES_FRSR2)|A(USES_FRSR1)|A(USES_FRDRRR)|A(AL_INSN), { { { (1<<MACH_MS1_003)|(1<<MACH_MS2), 0 } } } }
},
/* muli $frdr,$frsr1,#$imm16 */
{
- MS1_INSN_MULI, "muli", "muli", 32,
+ MT_INSN_MULI, "muli", "muli", 32,
{ 0|A(USES_FRSR1)|A(USES_FRDR)|A(AL_INSN), { { { (1<<MACH_MS1_003)|(1<<MACH_MS2), 0 } } } }
},
/* and $frdrrr,$frsr1,$frsr2 */
{
- MS1_INSN_AND, "and", "and", 32,
+ MT_INSN_AND, "and", "and", 32,
{ 0|A(USES_FRSR2)|A(USES_FRSR1)|A(USES_FRDRRR)|A(AL_INSN), { { { (1<<MACH_BASE), 0 } } } }
},
/* andi $frdr,$frsr1,#$imm16z */
{
- MS1_INSN_ANDI, "andi", "andi", 32,
+ MT_INSN_ANDI, "andi", "andi", 32,
{ 0|A(USES_FRSR1)|A(USES_FRDR)|A(AL_INSN), { { { (1<<MACH_BASE), 0 } } } }
},
/* or $frdrrr,$frsr1,$frsr2 */
{
- MS1_INSN_OR, "or", "or", 32,
+ MT_INSN_OR, "or", "or", 32,
{ 0|A(USES_FRSR2)|A(USES_FRSR1)|A(USES_FRDRRR)|A(AL_INSN), { { { (1<<MACH_BASE), 0 } } } }
},
/* nop */
{
- MS1_INSN_NOP, "nop", "nop", 32,
+ MT_INSN_NOP, "nop", "nop", 32,
{ 0, { { { (1<<MACH_BASE), 0 } } } }
},
/* ori $frdr,$frsr1,#$imm16z */
{
- MS1_INSN_ORI, "ori", "ori", 32,
+ MT_INSN_ORI, "ori", "ori", 32,
{ 0|A(USES_FRSR1)|A(USES_FRDR)|A(AL_INSN), { { { (1<<MACH_BASE), 0 } } } }
},
/* xor $frdrrr,$frsr1,$frsr2 */
{
- MS1_INSN_XOR, "xor", "xor", 32,
+ MT_INSN_XOR, "xor", "xor", 32,
{ 0|A(USES_FRSR2)|A(USES_FRSR1)|A(USES_FRDRRR)|A(AL_INSN), { { { (1<<MACH_BASE), 0 } } } }
},
/* xori $frdr,$frsr1,#$imm16z */
{
- MS1_INSN_XORI, "xori", "xori", 32,
+ MT_INSN_XORI, "xori", "xori", 32,
{ 0|A(USES_FRSR1)|A(USES_FRDR)|A(AL_INSN), { { { (1<<MACH_BASE), 0 } } } }
},
/* nand $frdrrr,$frsr1,$frsr2 */
{
- MS1_INSN_NAND, "nand", "nand", 32,
+ MT_INSN_NAND, "nand", "nand", 32,
{ 0|A(USES_FRSR2)|A(USES_FRSR1)|A(USES_FRDRRR)|A(AL_INSN), { { { (1<<MACH_BASE), 0 } } } }
},
/* nandi $frdr,$frsr1,#$imm16z */
{
- MS1_INSN_NANDI, "nandi", "nandi", 32,
+ MT_INSN_NANDI, "nandi", "nandi", 32,
{ 0|A(USES_FRSR1)|A(USES_FRDR)|A(AL_INSN), { { { (1<<MACH_BASE), 0 } } } }
},
/* nor $frdrrr,$frsr1,$frsr2 */
{
- MS1_INSN_NOR, "nor", "nor", 32,
+ MT_INSN_NOR, "nor", "nor", 32,
{ 0|A(USES_FRSR2)|A(USES_FRSR1)|A(USES_FRDRRR)|A(AL_INSN), { { { (1<<MACH_BASE), 0 } } } }
},
/* nori $frdr,$frsr1,#$imm16z */
{
- MS1_INSN_NORI, "nori", "nori", 32,
+ MT_INSN_NORI, "nori", "nori", 32,
{ 0|A(USES_FRSR1)|A(USES_FRDR)|A(AL_INSN), { { { (1<<MACH_BASE), 0 } } } }
},
/* xnor $frdrrr,$frsr1,$frsr2 */
{
- MS1_INSN_XNOR, "xnor", "xnor", 32,
+ MT_INSN_XNOR, "xnor", "xnor", 32,
{ 0|A(USES_FRSR2)|A(USES_FRSR1)|A(USES_FRDRRR)|A(AL_INSN), { { { (1<<MACH_BASE), 0 } } } }
},
/* xnori $frdr,$frsr1,#$imm16z */
{
- MS1_INSN_XNORI, "xnori", "xnori", 32,
+ MT_INSN_XNORI, "xnori", "xnori", 32,
{ 0|A(USES_FRSR1)|A(USES_FRDR)|A(AL_INSN), { { { (1<<MACH_BASE), 0 } } } }
},
/* ldui $frdr,#$imm16z */
{
- MS1_INSN_LDUI, "ldui", "ldui", 32,
+ MT_INSN_LDUI, "ldui", "ldui", 32,
{ 0|A(USES_FRDR)|A(AL_INSN), { { { (1<<MACH_BASE), 0 } } } }
},
/* lsl $frdrrr,$frsr1,$frsr2 */
{
- MS1_INSN_LSL, "lsl", "lsl", 32,
+ MT_INSN_LSL, "lsl", "lsl", 32,
{ 0|A(USES_FRSR2)|A(USES_FRSR1)|A(USES_FRDRRR), { { { (1<<MACH_BASE), 0 } } } }
},
/* lsli $frdr,$frsr1,#$imm16 */
{
- MS1_INSN_LSLI, "lsli", "lsli", 32,
+ MT_INSN_LSLI, "lsli", "lsli", 32,
{ 0|A(USES_FRSR1)|A(USES_FRDR), { { { (1<<MACH_BASE), 0 } } } }
},
/* lsr $frdrrr,$frsr1,$frsr2 */
{
- MS1_INSN_LSR, "lsr", "lsr", 32,
+ MT_INSN_LSR, "lsr", "lsr", 32,
{ 0|A(USES_FRSR2)|A(USES_FRSR1)|A(USES_FRDRRR), { { { (1<<MACH_BASE), 0 } } } }
},
/* lsri $frdr,$frsr1,#$imm16 */
{
- MS1_INSN_LSRI, "lsri", "lsri", 32,
+ MT_INSN_LSRI, "lsri", "lsri", 32,
{ 0|A(USES_FRSR1)|A(USES_FRDR), { { { (1<<MACH_BASE), 0 } } } }
},
/* asr $frdrrr,$frsr1,$frsr2 */
{
- MS1_INSN_ASR, "asr", "asr", 32,
+ MT_INSN_ASR, "asr", "asr", 32,
{ 0|A(USES_FRSR2)|A(USES_FRSR1)|A(USES_FRDRRR), { { { (1<<MACH_BASE), 0 } } } }
},
/* asri $frdr,$frsr1,#$imm16 */
{
- MS1_INSN_ASRI, "asri", "asri", 32,
+ MT_INSN_ASRI, "asri", "asri", 32,
{ 0|A(USES_FRSR1)|A(USES_FRDR), { { { (1<<MACH_BASE), 0 } } } }
},
/* brlt $frsr1,$frsr2,$imm16o */
{
- MS1_INSN_BRLT, "brlt", "brlt", 32,
+ MT_INSN_BRLT, "brlt", "brlt", 32,
{ 0|A(USES_FRSR2)|A(USES_FRSR1)|A(USES_FRDRRR)|A(DELAY_SLOT)|A(BR_INSN), { { { (1<<MACH_BASE), 0 } } } }
},
/* brle $frsr1,$frsr2,$imm16o */
{
- MS1_INSN_BRLE, "brle", "brle", 32,
+ MT_INSN_BRLE, "brle", "brle", 32,
{ 0|A(USES_FRSR2)|A(USES_FRSR1)|A(DELAY_SLOT)|A(BR_INSN), { { { (1<<MACH_BASE), 0 } } } }
},
/* breq $frsr1,$frsr2,$imm16o */
{
- MS1_INSN_BREQ, "breq", "breq", 32,
+ MT_INSN_BREQ, "breq", "breq", 32,
{ 0|A(USES_FRSR2)|A(USES_FRSR1)|A(DELAY_SLOT)|A(BR_INSN), { { { (1<<MACH_BASE), 0 } } } }
},
/* brne $frsr1,$frsr2,$imm16o */
{
- MS1_INSN_BRNE, "brne", "brne", 32,
+ MT_INSN_BRNE, "brne", "brne", 32,
{ 0|A(USES_FRSR2)|A(USES_FRSR1)|A(DELAY_SLOT)|A(BR_INSN), { { { (1<<MACH_BASE), 0 } } } }
},
/* jmp $imm16o */
{
- MS1_INSN_JMP, "jmp", "jmp", 32,
+ MT_INSN_JMP, "jmp", "jmp", 32,
{ 0|A(BR_INSN)|A(DELAY_SLOT), { { { (1<<MACH_BASE), 0 } } } }
},
/* jal $frdrrr,$frsr1 */
{
- MS1_INSN_JAL, "jal", "jal", 32,
+ MT_INSN_JAL, "jal", "jal", 32,
{ 0|A(JAL_HAZARD)|A(USES_FRSR1)|A(USES_FRDR)|A(BR_INSN)|A(DELAY_SLOT), { { { (1<<MACH_BASE), 0 } } } }
},
/* dbnz $frsr1,$imm16o */
{
- MS1_INSN_DBNZ, "dbnz", "dbnz", 32,
+ MT_INSN_DBNZ, "dbnz", "dbnz", 32,
{ 0|A(USES_FRSR1)|A(DELAY_SLOT)|A(BR_INSN), { { { (1<<MACH_MS1_003)|(1<<MACH_MS2), 0 } } } }
},
/* ei */
{
- MS1_INSN_EI, "ei", "ei", 32,
+ MT_INSN_EI, "ei", "ei", 32,
{ 0, { { { (1<<MACH_BASE), 0 } } } }
},
/* di */
{
- MS1_INSN_DI, "di", "di", 32,
+ MT_INSN_DI, "di", "di", 32,
{ 0, { { { (1<<MACH_BASE), 0 } } } }
},
/* si $frdrrr */
{
- MS1_INSN_SI, "si", "si", 32,
+ MT_INSN_SI, "si", "si", 32,
{ 0|A(USES_FRDR)|A(BR_INSN)|A(DELAY_SLOT), { { { (1<<MACH_BASE), 0 } } } }
},
/* reti $frsr1 */
{
- MS1_INSN_RETI, "reti", "reti", 32,
+ MT_INSN_RETI, "reti", "reti", 32,
{ 0|A(JAL_HAZARD)|A(USES_FRSR1)|A(BR_INSN)|A(DELAY_SLOT), { { { (1<<MACH_BASE), 0 } } } }
},
/* ldw $frdr,$frsr1,#$imm16 */
{
- MS1_INSN_LDW, "ldw", "ldw", 32,
+ MT_INSN_LDW, "ldw", "ldw", 32,
{ 0|A(USES_FRSR1)|A(USES_FRDR)|A(MEMORY_ACCESS)|A(LOAD_DELAY), { { { (1<<MACH_BASE), 0 } } } }
},
/* stw $frsr2,$frsr1,#$imm16 */
{
- MS1_INSN_STW, "stw", "stw", 32,
+ MT_INSN_STW, "stw", "stw", 32,
{ 0|A(USES_FRSR2)|A(USES_FRSR1)|A(MEMORY_ACCESS), { { { (1<<MACH_BASE), 0 } } } }
},
/* break */
{
- MS1_INSN_BREAK, "break", "break", 32,
+ MT_INSN_BREAK, "break", "break", 32,
{ 0, { { { (1<<MACH_BASE), 0 } } } }
},
/* iflush */
{
- MS1_INSN_IFLUSH, "iflush", "iflush", 32,
+ MT_INSN_IFLUSH, "iflush", "iflush", 32,
{ 0, { { { (1<<MACH_MS1_003)|(1<<MACH_MS2), 0 } } } }
},
/* ldctxt $frsr1,$frsr2,#$rc,#$rcnum,#$contnum */
{
- MS1_INSN_LDCTXT, "ldctxt", "ldctxt", 32,
+ MT_INSN_LDCTXT, "ldctxt", "ldctxt", 32,
{ 0, { { { (1<<MACH_MS1), 0 } } } }
},
/* ldfb $frsr1,$frsr2,#$imm16z */
{
- MS1_INSN_LDFB, "ldfb", "ldfb", 32,
+ MT_INSN_LDFB, "ldfb", "ldfb", 32,
{ 0, { { { (1<<MACH_MS1), 0 } } } }
},
/* stfb $frsr1,$frsr2,#$imm16z */
{
- MS1_INSN_STFB, "stfb", "stfb", 32,
+ MT_INSN_STFB, "stfb", "stfb", 32,
{ 0, { { { (1<<MACH_MS1), 0 } } } }
},
/* fbcb $frsr1,#$rbbc,#$ball,#$brc,#$rc1,#$cbrb,#$cell,#$dup,#$ctxdisp */
{
- MS1_INSN_FBCB, "fbcb", "fbcb", 32,
+ MT_INSN_FBCB, "fbcb", "fbcb", 32,
{ 0, { { { (1<<MACH_MS1)|(1<<MACH_MS1_003), 0 } } } }
},
/* mfbcb $frsr1,#$rbbc,$frsr2,#$rc1,#$cbrb,#$cell,#$dup,#$ctxdisp */
{
- MS1_INSN_MFBCB, "mfbcb", "mfbcb", 32,
+ MT_INSN_MFBCB, "mfbcb", "mfbcb", 32,
{ 0, { { { (1<<MACH_BASE), 0 } } } }
},
/* fbcci $frsr1,#$rbbc,#$ball,#$brc,#$fbdisp,#$cell,#$dup,#$ctxdisp */
{
- MS1_INSN_FBCCI, "fbcci", "fbcci", 32,
+ MT_INSN_FBCCI, "fbcci", "fbcci", 32,
{ 0, { { { (1<<MACH_BASE), 0 } } } }
},
/* fbrci $frsr1,#$rbbc,#$ball,#$brc,#$fbdisp,#$cell,#$dup,#$ctxdisp */
{
- MS1_INSN_FBRCI, "fbrci", "fbrci", 32,
+ MT_INSN_FBRCI, "fbrci", "fbrci", 32,
{ 0, { { { (1<<MACH_BASE), 0 } } } }
},
/* fbcri $frsr1,#$rbbc,#$ball,#$brc,#$fbdisp,#$cell,#$dup,#$ctxdisp */
{
- MS1_INSN_FBCRI, "fbcri", "fbcri", 32,
+ MT_INSN_FBCRI, "fbcri", "fbcri", 32,
{ 0, { { { (1<<MACH_BASE), 0 } } } }
},
/* fbrri $frsr1,#$rbbc,#$ball,#$brc,#$fbdisp,#$cell,#$dup,#$ctxdisp */
{
- MS1_INSN_FBRRI, "fbrri", "fbrri", 32,
+ MT_INSN_FBRRI, "fbrri", "fbrri", 32,
{ 0, { { { (1<<MACH_BASE), 0 } } } }
},
/* mfbcci $frsr1,#$rbbc,$frsr2,#$fbdisp,#$cell,#$dup,#$ctxdisp */
{
- MS1_INSN_MFBCCI, "mfbcci", "mfbcci", 32,
+ MT_INSN_MFBCCI, "mfbcci", "mfbcci", 32,
{ 0, { { { (1<<MACH_BASE), 0 } } } }
},
/* mfbrci $frsr1,#$rbbc,$frsr2,#$fbdisp,#$cell,#$dup,#$ctxdisp */
{
- MS1_INSN_MFBRCI, "mfbrci", "mfbrci", 32,
+ MT_INSN_MFBRCI, "mfbrci", "mfbrci", 32,
{ 0, { { { (1<<MACH_BASE), 0 } } } }
},
/* mfbcri $frsr1,#$rbbc,$frsr2,#$fbdisp,#$cell,#$dup,#$ctxdisp */
{
- MS1_INSN_MFBCRI, "mfbcri", "mfbcri", 32,
+ MT_INSN_MFBCRI, "mfbcri", "mfbcri", 32,
{ 0, { { { (1<<MACH_BASE), 0 } } } }
},
/* mfbrri $frsr1,#$rbbc,$frsr2,#$fbdisp,#$cell,#$dup,#$ctxdisp */
{
- MS1_INSN_MFBRRI, "mfbrri", "mfbrri", 32,
+ MT_INSN_MFBRRI, "mfbrri", "mfbrri", 32,
{ 0, { { { (1<<MACH_BASE), 0 } } } }
},
/* fbcbdr $frsr1,#$rbbc,$frsr2,#$ball2,#$brc2,#$rc1,#$cbrb,#$cell,#$dup,#$ctxdisp */
{
- MS1_INSN_FBCBDR, "fbcbdr", "fbcbdr", 32,
+ MT_INSN_FBCBDR, "fbcbdr", "fbcbdr", 32,
{ 0, { { { (1<<MACH_BASE), 0 } } } }
},
/* rcfbcb #$rbbc,#$type,#$ball,#$brc,#$rownum,#$rc1,#$cbrb,#$cell,#$dup,#$ctxdisp */
{
- MS1_INSN_RCFBCB, "rcfbcb", "rcfbcb", 32,
+ MT_INSN_RCFBCB, "rcfbcb", "rcfbcb", 32,
{ 0, { { { (1<<MACH_BASE), 0 } } } }
},
/* mrcfbcb $frsr2,#$rbbc,#$type,#$rownum,#$rc1,#$cbrb,#$cell,#$dup,#$ctxdisp */
{
- MS1_INSN_MRCFBCB, "mrcfbcb", "mrcfbcb", 32,
+ MT_INSN_MRCFBCB, "mrcfbcb", "mrcfbcb", 32,
{ 0, { { { (1<<MACH_BASE), 0 } } } }
},
/* cbcast #$mask,#$rc2,#$ctxdisp */
{
- MS1_INSN_CBCAST, "cbcast", "cbcast", 32,
+ MT_INSN_CBCAST, "cbcast", "cbcast", 32,
{ 0, { { { (1<<MACH_BASE), 0 } } } }
},
/* dupcbcast #$mask,#$cell,#$rc2,#$ctxdisp */
{
- MS1_INSN_DUPCBCAST, "dupcbcast", "dupcbcast", 32,
+ MT_INSN_DUPCBCAST, "dupcbcast", "dupcbcast", 32,
{ 0, { { { (1<<MACH_BASE), 0 } } } }
},
/* wfbi #$bankaddr,#$rownum1,#$cell,#$dup,#$ctxdisp */
{
- MS1_INSN_WFBI, "wfbi", "wfbi", 32,
+ MT_INSN_WFBI, "wfbi", "wfbi", 32,
{ 0, { { { (1<<MACH_BASE), 0 } } } }
},
/* wfb $frsr1,$frsr2,#$fbdisp,#$rownum2,#$ctxdisp */
{
- MS1_INSN_WFB, "wfb", "wfb", 32,
+ MT_INSN_WFB, "wfb", "wfb", 32,
{ 0, { { { (1<<MACH_BASE), 0 } } } }
},
/* rcrisc $frdrrr,#$rbbc,$frsr1,#$colnum,#$rc1,#$cbrb,#$cell,#$dup,#$ctxdisp */
{
- MS1_INSN_RCRISC, "rcrisc", "rcrisc", 32,
+ MT_INSN_RCRISC, "rcrisc", "rcrisc", 32,
{ 0, { { { (1<<MACH_BASE), 0 } } } }
},
/* fbcbinc $frsr1,#$rbbc,#$incamt,#$rc1,#$cbrb,#$cell,#$dup,#$ctxdisp */
{
- MS1_INSN_FBCBINC, "fbcbinc", "fbcbinc", 32,
+ MT_INSN_FBCBINC, "fbcbinc", "fbcbinc", 32,
{ 0, { { { (1<<MACH_BASE), 0 } } } }
},
/* rcxmode $frsr2,#$rda,#$wr,#$xmode,#$mask1,#$fbdisp,#$rownum2,#$rc2,#$ctxdisp */
{
- MS1_INSN_RCXMODE, "rcxmode", "rcxmode", 32,
+ MT_INSN_RCXMODE, "rcxmode", "rcxmode", 32,
{ 0, { { { (1<<MACH_BASE), 0 } } } }
},
/* intlvr $frsr1,#$mode,$frsr2,#$id,#$size */
{
- MS1_INSN_INTERLEAVER, "interleaver", "intlvr", 32,
+ MT_INSN_INTERLEAVER, "interleaver", "intlvr", 32,
{ 0, { { { (1<<MACH_BASE), 0 } } } }
},
/* wfbinc #$rda,#$wr,#$fbincr,#$ball,#$colnum,#$length,#$rownum1,#$rownum2,#$dup,#$ctxdisp */
{
- MS1_INSN_WFBINC, "wfbinc", "wfbinc", 32,
+ MT_INSN_WFBINC, "wfbinc", "wfbinc", 32,
{ 0, { { { (1<<MACH_MS1_003)|(1<<MACH_MS2), 0 } } } }
},
/* mwfbinc $frsr2,#$rda,#$wr,#$fbincr,#$length,#$rownum1,#$rownum2,#$dup,#$ctxdisp */
{
- MS1_INSN_MWFBINC, "mwfbinc", "mwfbinc", 32,
+ MT_INSN_MWFBINC, "mwfbinc", "mwfbinc", 32,
{ 0, { { { (1<<MACH_MS1_003)|(1<<MACH_MS2), 0 } } } }
},
/* wfbincr $frsr1,#$rda,#$wr,#$ball,#$colnum,#$length,#$rownum1,#$rownum2,#$dup,#$ctxdisp */
{
- MS1_INSN_WFBINCR, "wfbincr", "wfbincr", 32,
+ MT_INSN_WFBINCR, "wfbincr", "wfbincr", 32,
{ 0, { { { (1<<MACH_MS1_003)|(1<<MACH_MS2), 0 } } } }
},
/* mwfbincr $frsr1,$frsr2,#$rda,#$wr,#$length,#$rownum1,#$rownum2,#$dup,#$ctxdisp */
{
- MS1_INSN_MWFBINCR, "mwfbincr", "mwfbincr", 32,
+ MT_INSN_MWFBINCR, "mwfbincr", "mwfbincr", 32,
{ 0, { { { (1<<MACH_MS1_003)|(1<<MACH_MS2), 0 } } } }
},
/* fbcbincs #$perm,#$a23,#$cr,#$cbs,#$incr,#$ccb,#$cdb,#$rownum2,#$dup,#$ctxdisp */
{
- MS1_INSN_FBCBINCS, "fbcbincs", "fbcbincs", 32,
+ MT_INSN_FBCBINCS, "fbcbincs", "fbcbincs", 32,
{ 0, { { { (1<<MACH_MS1_003)|(1<<MACH_MS2), 0 } } } }
},
/* mfbcbincs $frsr1,#$perm,#$cbs,#$incr,#$ccb,#$cdb,#$rownum2,#$dup,#$ctxdisp */
{
- MS1_INSN_MFBCBINCS, "mfbcbincs", "mfbcbincs", 32,
+ MT_INSN_MFBCBINCS, "mfbcbincs", "mfbcbincs", 32,
{ 0, { { { (1<<MACH_MS1_003)|(1<<MACH_MS2), 0 } } } }
},
/* fbcbincrs $frsr1,#$perm,#$ball,#$colnum,#$cbx,#$ccb,#$cdb,#$rownum2,#$dup,#$ctxdisp */
{
- MS1_INSN_FBCBINCRS, "fbcbincrs", "fbcbincrs", 32,
+ MT_INSN_FBCBINCRS, "fbcbincrs", "fbcbincrs", 32,
{ 0, { { { (1<<MACH_MS1_003)|(1<<MACH_MS2), 0 } } } }
},
/* mfbcbincrs $frsr1,$frsr2,#$perm,#$cbx,#$ccb,#$cdb,#$rownum2,#$dup,#$ctxdisp */
{
- MS1_INSN_MFBCBINCRS, "mfbcbincrs", "mfbcbincrs", 32,
+ MT_INSN_MFBCBINCRS, "mfbcbincrs", "mfbcbincrs", 32,
{ 0, { { { (1<<MACH_MS1_003)|(1<<MACH_MS2), 0 } } } }
},
/* loop $frsr1,$loopsize */
{
- MS1_INSN_LOOP, "loop", "loop", 32,
+ MT_INSN_LOOP, "loop", "loop", 32,
{ 0|A(USES_FRSR1)|A(DELAY_SLOT), { { { (1<<MACH_MS2), 0 } } } }
},
/* loopi #$imm16l,$loopsize */
{
- MS1_INSN_LOOPI, "loopi", "loopi", 32,
+ MT_INSN_LOOPI, "loopi", "loopi", 32,
{ 0|A(DELAY_SLOT), { { { (1<<MACH_MS2), 0 } } } }
},
/* dfbc #$cb1sel,#$cb2sel,#$cb1incr,#$cb2incr,#$rc3,#$rc2,#$ctxdisp */
{
- MS1_INSN_DFBC, "dfbc", "dfbc", 32,
+ MT_INSN_DFBC, "dfbc", "dfbc", 32,
{ 0, { { { (1<<MACH_MS2), 0 } } } }
},
/* dwfb #$cb1sel,#$cb2sel,#$cb1incr,#$cb2incr,#$rc2,#$ctxdisp */
{
- MS1_INSN_DWFB, "dwfb", "dwfb", 32,
+ MT_INSN_DWFB, "dwfb", "dwfb", 32,
{ 0, { { { (1<<MACH_MS2), 0 } } } }
},
/* fbwfb #$cb1sel,#$cb2sel,#$cb1incr,#$cb2incr,#$rc3,#$rc2,#$ctxdisp */
{
- MS1_INSN_FBWFB, "fbwfb", "fbwfb", 32,
+ MT_INSN_FBWFB, "fbwfb", "fbwfb", 32,
{ 0, { { { (1<<MACH_MS2), 0 } } } }
},
/* dfbr #$cb1sel,#$cb2sel,$frsr2,#$length,#$rownum1,#$rownum2,#$rc2,#$ctxdisp */
{
- MS1_INSN_DFBR, "dfbr", "dfbr", 32,
+ MT_INSN_DFBR, "dfbr", "dfbr", 32,
{ 0|A(USES_FRSR2), { { { (1<<MACH_MS2), 0 } } } }
},
};
static void build_ifield_table (CGEN_CPU_TABLE *);
static void build_operand_table (CGEN_CPU_TABLE *);
static void build_insn_table (CGEN_CPU_TABLE *);
-static void ms1_cgen_rebuild_tables (CGEN_CPU_TABLE *);
+static void mt_cgen_rebuild_tables (CGEN_CPU_TABLE *);
-/* Subroutine of ms1_cgen_cpu_open to look up a mach via its bfd name. */
+/* Subroutine of mt_cgen_cpu_open to look up a mach via its bfd name. */
static const CGEN_MACH *
lookup_mach_via_bfd_name (const CGEN_MACH *table, const char *name)
abort ();
}
-/* Subroutine of ms1_cgen_cpu_open to build the hardware table. */
+/* Subroutine of mt_cgen_cpu_open to build the hardware table. */
static void
build_hw_table (CGEN_CPU_TABLE *cd)
{
int i;
int machs = cd->machs;
- const CGEN_HW_ENTRY *init = & ms1_cgen_hw_table[0];
+ const CGEN_HW_ENTRY *init = & mt_cgen_hw_table[0];
/* MAX_HW is only an upper bound on the number of selected entries.
However each entry is indexed by it's enum so there can be holes in
the table. */
cd->hw_table.num_entries = MAX_HW;
}
-/* Subroutine of ms1_cgen_cpu_open to build the hardware table. */
+/* Subroutine of mt_cgen_cpu_open to build the hardware table. */
static void
build_ifield_table (CGEN_CPU_TABLE *cd)
{
- cd->ifld_table = & ms1_cgen_ifld_table[0];
+ cd->ifld_table = & mt_cgen_ifld_table[0];
}
-/* Subroutine of ms1_cgen_cpu_open to build the hardware table. */
+/* Subroutine of mt_cgen_cpu_open to build the hardware table. */
static void
build_operand_table (CGEN_CPU_TABLE *cd)
{
int i;
int machs = cd->machs;
- const CGEN_OPERAND *init = & ms1_cgen_operand_table[0];
+ const CGEN_OPERAND *init = & mt_cgen_operand_table[0];
/* MAX_OPERANDS is only an upper bound on the number of selected entries.
However each entry is indexed by it's enum so there can be holes in
the table. */
cd->operand_table.num_entries = MAX_OPERANDS;
}
-/* Subroutine of ms1_cgen_cpu_open to build the hardware table.
+/* Subroutine of mt_cgen_cpu_open to build the hardware table.
??? This could leave out insns not supported by the specified mach/isa,
but that would cause errors like "foo only supported by bar" to become
"unknown insn", so for now we include all insns and require the app to
build_insn_table (CGEN_CPU_TABLE *cd)
{
int i;
- const CGEN_IBASE *ib = & ms1_cgen_insn_table[0];
+ const CGEN_IBASE *ib = & mt_cgen_insn_table[0];
CGEN_INSN *insns = xmalloc (MAX_INSNS * sizeof (CGEN_INSN));
memset (insns, 0, MAX_INSNS * sizeof (CGEN_INSN));
cd->insn_table.num_init_entries = MAX_INSNS;
}
-/* Subroutine of ms1_cgen_cpu_open to rebuild the tables. */
+/* Subroutine of mt_cgen_cpu_open to rebuild the tables. */
static void
-ms1_cgen_rebuild_tables (CGEN_CPU_TABLE *cd)
+mt_cgen_rebuild_tables (CGEN_CPU_TABLE *cd)
{
int i;
CGEN_BITSET *isas = cd->isas;
for (i = 0; i < MAX_ISAS; ++i)
if (cgen_bitset_contains (isas, i))
{
- const CGEN_ISA *isa = & ms1_cgen_isa_table[i];
+ const CGEN_ISA *isa = & mt_cgen_isa_table[i];
/* Default insn sizes of all selected isas must be
equal or we set the result to 0, meaning "unknown". */
for (i = 0; i < MAX_MACHS; ++i)
if (((1 << i) & machs) != 0)
{
- const CGEN_MACH *mach = & ms1_cgen_mach_table[i];
+ const CGEN_MACH *mach = & mt_cgen_mach_table[i];
if (mach->insn_chunk_bitsize != 0)
{
if (cd->insn_chunk_bitsize != 0 && cd->insn_chunk_bitsize != mach->insn_chunk_bitsize)
{
- fprintf (stderr, "ms1_cgen_rebuild_tables: conflicting insn-chunk-bitsize values: `%d' vs. `%d'\n",
+ fprintf (stderr, "mt_cgen_rebuild_tables: conflicting insn-chunk-bitsize values: `%d' vs. `%d'\n",
cd->insn_chunk_bitsize, mach->insn_chunk_bitsize);
abort ();
}
K&R will no longer be supported - e.g. GDB is currently trying this. */
CGEN_CPU_DESC
-ms1_cgen_cpu_open (enum cgen_cpu_open_arg arg_type, ...)
+mt_cgen_cpu_open (enum cgen_cpu_open_arg arg_type, ...)
{
CGEN_CPU_TABLE *cd = (CGEN_CPU_TABLE *) xmalloc (sizeof (CGEN_CPU_TABLE));
static int init_p;
{
const char *name = va_arg (ap, const char *);
const CGEN_MACH *mach =
- lookup_mach_via_bfd_name (ms1_cgen_mach_table, name);
+ lookup_mach_via_bfd_name (mt_cgen_mach_table, name);
machs |= 1 << mach->num;
break;
endian = va_arg (ap, enum cgen_endian);
break;
default :
- fprintf (stderr, "ms1_cgen_cpu_open: unsupported argument `%d'\n",
+ fprintf (stderr, "mt_cgen_cpu_open: unsupported argument `%d'\n",
arg_type);
abort (); /* ??? return NULL? */
}
if (endian == CGEN_ENDIAN_UNKNOWN)
{
/* ??? If target has only one, could have a default. */
- fprintf (stderr, "ms1_cgen_cpu_open: no endianness specified\n");
+ fprintf (stderr, "mt_cgen_cpu_open: no endianness specified\n");
abort ();
}
cd->insn_endian = endian;
/* Table (re)builder. */
- cd->rebuild_tables = ms1_cgen_rebuild_tables;
- ms1_cgen_rebuild_tables (cd);
+ cd->rebuild_tables = mt_cgen_rebuild_tables;
+ mt_cgen_rebuild_tables (cd);
/* Default to not allowing signed overflow. */
cd->signed_overflow_ok_p = 0;
return (CGEN_CPU_DESC) cd;
}
-/* Cover fn to ms1_cgen_cpu_open to handle the simple case of 1 isa, 1 mach.
+/* Cover fn to mt_cgen_cpu_open to handle the simple case of 1 isa, 1 mach.
MACH_NAME is the bfd name of the mach. */
CGEN_CPU_DESC
-ms1_cgen_cpu_open_1 (const char *mach_name, enum cgen_endian endian)
+mt_cgen_cpu_open_1 (const char *mach_name, enum cgen_endian endian)
{
- return ms1_cgen_cpu_open (CGEN_CPU_OPEN_BFDMACH, mach_name,
+ return mt_cgen_cpu_open (CGEN_CPU_OPEN_BFDMACH, mach_name,
CGEN_CPU_OPEN_ENDIAN, endian,
CGEN_CPU_OPEN_END);
}
place as some simulator ports use this but they don't use libopcodes. */
void
-ms1_cgen_cpu_close (CGEN_CPU_DESC cd)
+mt_cgen_cpu_close (CGEN_CPU_DESC cd)
{
unsigned int i;
const CGEN_INSN *insns;
-/* CPU data header for ms1.
+/* CPU data header for mt.
THIS FILE IS MACHINE GENERATED WITH CGEN.
*/
-#ifndef MS1_CPU_H
-#define MS1_CPU_H
+#ifndef MT_CPU_H
+#define MT_CPU_H
#include "opcode/cgen-bitset.h"
-#define CGEN_ARCH ms1
+#define CGEN_ARCH mt
-/* Given symbol S, return ms1_cgen_<S>. */
+/* Given symbol S, return mt_cgen_<S>. */
#if defined (__STDC__) || defined (ALMOST_STDC) || defined (HAVE_STRINGIZE)
-#define CGEN_SYM(s) ms1##_cgen_##s
+#define CGEN_SYM(s) mt##_cgen_##s
#else
-#define CGEN_SYM(s) ms1/**/_cgen_/**/s
+#define CGEN_SYM(s) mt/**/_cgen_/**/s
#endif
/* Enum declaration for instruction set selection. */
typedef enum isa_attr {
- ISA_MS1, ISA_MAX
+ ISA_MT, ISA_MAX
} ISA_ATTR;
/* Number of architecture variants. */
#define CGEN_ATTR_CGEN_IFLD_SIGN_OPT_VALUE(attrs) (((attrs)->bool & (1 << CGEN_IFLD_SIGN_OPT)) != 0)
#define CGEN_ATTR_CGEN_IFLD_SIGNED_VALUE(attrs) (((attrs)->bool & (1 << CGEN_IFLD_SIGNED)) != 0)
-/* Enum declaration for ms1 ifield types. */
+/* Enum declaration for mt ifield types. */
typedef enum ifield_type {
- MS1_F_NIL, MS1_F_ANYOF, MS1_F_MSYS, MS1_F_OPC
- , MS1_F_IMM, MS1_F_UU24, MS1_F_SR1, MS1_F_SR2
- , MS1_F_DR, MS1_F_DRRR, MS1_F_IMM16U, MS1_F_IMM16S
- , MS1_F_IMM16A, MS1_F_UU4A, MS1_F_UU4B, MS1_F_UU12
- , MS1_F_UU8, MS1_F_UU16, MS1_F_UU1, MS1_F_MSOPC
- , MS1_F_UU_26_25, MS1_F_MASK, MS1_F_BANKADDR, MS1_F_RDA
- , MS1_F_UU_2_25, MS1_F_RBBC, MS1_F_PERM, MS1_F_MODE
- , MS1_F_UU_1_24, MS1_F_WR, MS1_F_FBINCR, MS1_F_UU_2_23
- , MS1_F_XMODE, MS1_F_A23, MS1_F_MASK1, MS1_F_CR
- , MS1_F_TYPE, MS1_F_INCAMT, MS1_F_CBS, MS1_F_UU_1_19
- , MS1_F_BALL, MS1_F_COLNUM, MS1_F_BRC, MS1_F_INCR
- , MS1_F_FBDISP, MS1_F_UU_4_15, MS1_F_LENGTH, MS1_F_UU_1_15
- , MS1_F_RC, MS1_F_RCNUM, MS1_F_ROWNUM, MS1_F_CBX
- , MS1_F_ID, MS1_F_SIZE, MS1_F_ROWNUM1, MS1_F_UU_3_11
- , MS1_F_RC1, MS1_F_CCB, MS1_F_CBRB, MS1_F_CDB
- , MS1_F_ROWNUM2, MS1_F_CELL, MS1_F_UU_3_9, MS1_F_CONTNUM
- , MS1_F_UU_1_6, MS1_F_DUP, MS1_F_RC2, MS1_F_CTXDISP
- , MS1_F_IMM16L, MS1_F_LOOPO, MS1_F_CB1SEL, MS1_F_CB2SEL
- , MS1_F_CB1INCR, MS1_F_CB2INCR, MS1_F_RC3, MS1_F_MSYSFRSR2
- , MS1_F_BRC2, MS1_F_BALL2, MS1_F_MAX
+ MT_F_NIL, MT_F_ANYOF, MT_F_MSYS, MT_F_OPC
+ , MT_F_IMM, MT_F_UU24, MT_F_SR1, MT_F_SR2
+ , MT_F_DR, MT_F_DRRR, MT_F_IMM16U, MT_F_IMM16S
+ , MT_F_IMM16A, MT_F_UU4A, MT_F_UU4B, MT_F_UU12
+ , MT_F_UU8, MT_F_UU16, MT_F_UU1, MT_F_MSOPC
+ , MT_F_UU_26_25, MT_F_MASK, MT_F_BANKADDR, MT_F_RDA
+ , MT_F_UU_2_25, MT_F_RBBC, MT_F_PERM, MT_F_MODE
+ , MT_F_UU_1_24, MT_F_WR, MT_F_FBINCR, MT_F_UU_2_23
+ , MT_F_XMODE, MT_F_A23, MT_F_MASK1, MT_F_CR
+ , MT_F_TYPE, MT_F_INCAMT, MT_F_CBS, MT_F_UU_1_19
+ , MT_F_BALL, MT_F_COLNUM, MT_F_BRC, MT_F_INCR
+ , MT_F_FBDISP, MT_F_UU_4_15, MT_F_LENGTH, MT_F_UU_1_15
+ , MT_F_RC, MT_F_RCNUM, MT_F_ROWNUM, MT_F_CBX
+ , MT_F_ID, MT_F_SIZE, MT_F_ROWNUM1, MT_F_UU_3_11
+ , MT_F_RC1, MT_F_CCB, MT_F_CBRB, MT_F_CDB
+ , MT_F_ROWNUM2, MT_F_CELL, MT_F_UU_3_9, MT_F_CONTNUM
+ , MT_F_UU_1_6, MT_F_DUP, MT_F_RC2, MT_F_CTXDISP
+ , MT_F_IMM16L, MT_F_LOOPO, MT_F_CB1SEL, MT_F_CB2SEL
+ , MT_F_CB1INCR, MT_F_CB2INCR, MT_F_RC3, MT_F_MSYSFRSR2
+ , MT_F_BRC2, MT_F_BALL2, MT_F_MAX
} IFIELD_TYPE;
-#define MAX_IFLD ((int) MS1_F_MAX)
+#define MAX_IFLD ((int) MT_F_MAX)
/* Hardware attribute indices. */
#define CGEN_ATTR_CGEN_HW_PC_VALUE(attrs) (((attrs)->bool & (1 << CGEN_HW_PC)) != 0)
#define CGEN_ATTR_CGEN_HW_PROFILE_VALUE(attrs) (((attrs)->bool & (1 << CGEN_HW_PROFILE)) != 0)
-/* Enum declaration for ms1 hardware types. */
+/* Enum declaration for mt hardware types. */
typedef enum cgen_hw_type {
HW_H_MEMORY, HW_H_SINT, HW_H_UINT, HW_H_ADDR
, HW_H_IADDR, HW_H_SPR, HW_H_PC, HW_MAX
#define CGEN_ATTR_CGEN_OPERAND_RELAX_VALUE(attrs) (((attrs)->bool & (1 << CGEN_OPERAND_RELAX)) != 0)
#define CGEN_ATTR_CGEN_OPERAND_SEM_ONLY_VALUE(attrs) (((attrs)->bool & (1 << CGEN_OPERAND_SEM_ONLY)) != 0)
-/* Enum declaration for ms1 operand types. */
+/* Enum declaration for mt operand types. */
typedef enum cgen_operand_type {
- MS1_OPERAND_PC, MS1_OPERAND_FRSR1, MS1_OPERAND_FRSR2, MS1_OPERAND_FRDR
- , MS1_OPERAND_FRDRRR, MS1_OPERAND_IMM16, MS1_OPERAND_IMM16Z, MS1_OPERAND_IMM16O
- , MS1_OPERAND_RC, MS1_OPERAND_RCNUM, MS1_OPERAND_CONTNUM, MS1_OPERAND_RBBC
- , MS1_OPERAND_COLNUM, MS1_OPERAND_ROWNUM, MS1_OPERAND_ROWNUM1, MS1_OPERAND_ROWNUM2
- , MS1_OPERAND_RC1, MS1_OPERAND_RC2, MS1_OPERAND_CBRB, MS1_OPERAND_CELL
- , MS1_OPERAND_DUP, MS1_OPERAND_CTXDISP, MS1_OPERAND_FBDISP, MS1_OPERAND_TYPE
- , MS1_OPERAND_MASK, MS1_OPERAND_BANKADDR, MS1_OPERAND_INCAMT, MS1_OPERAND_XMODE
- , MS1_OPERAND_MASK1, MS1_OPERAND_BALL, MS1_OPERAND_BRC, MS1_OPERAND_RDA
- , MS1_OPERAND_WR, MS1_OPERAND_BALL2, MS1_OPERAND_BRC2, MS1_OPERAND_PERM
- , MS1_OPERAND_A23, MS1_OPERAND_CR, MS1_OPERAND_CBS, MS1_OPERAND_INCR
- , MS1_OPERAND_LENGTH, MS1_OPERAND_CBX, MS1_OPERAND_CCB, MS1_OPERAND_CDB
- , MS1_OPERAND_MODE, MS1_OPERAND_ID, MS1_OPERAND_SIZE, MS1_OPERAND_FBINCR
- , MS1_OPERAND_LOOPSIZE, MS1_OPERAND_IMM16L, MS1_OPERAND_RC3, MS1_OPERAND_CB1SEL
- , MS1_OPERAND_CB2SEL, MS1_OPERAND_CB1INCR, MS1_OPERAND_CB2INCR, MS1_OPERAND_MAX
+ MT_OPERAND_PC, MT_OPERAND_FRSR1, MT_OPERAND_FRSR2, MT_OPERAND_FRDR
+ , MT_OPERAND_FRDRRR, MT_OPERAND_IMM16, MT_OPERAND_IMM16Z, MT_OPERAND_IMM16O
+ , MT_OPERAND_RC, MT_OPERAND_RCNUM, MT_OPERAND_CONTNUM, MT_OPERAND_RBBC
+ , MT_OPERAND_COLNUM, MT_OPERAND_ROWNUM, MT_OPERAND_ROWNUM1, MT_OPERAND_ROWNUM2
+ , MT_OPERAND_RC1, MT_OPERAND_RC2, MT_OPERAND_CBRB, MT_OPERAND_CELL
+ , MT_OPERAND_DUP, MT_OPERAND_CTXDISP, MT_OPERAND_FBDISP, MT_OPERAND_TYPE
+ , MT_OPERAND_MASK, MT_OPERAND_BANKADDR, MT_OPERAND_INCAMT, MT_OPERAND_XMODE
+ , MT_OPERAND_MASK1, MT_OPERAND_BALL, MT_OPERAND_BRC, MT_OPERAND_RDA
+ , MT_OPERAND_WR, MT_OPERAND_BALL2, MT_OPERAND_BRC2, MT_OPERAND_PERM
+ , MT_OPERAND_A23, MT_OPERAND_CR, MT_OPERAND_CBS, MT_OPERAND_INCR
+ , MT_OPERAND_LENGTH, MT_OPERAND_CBX, MT_OPERAND_CCB, MT_OPERAND_CDB
+ , MT_OPERAND_MODE, MT_OPERAND_ID, MT_OPERAND_SIZE, MT_OPERAND_FBINCR
+ , MT_OPERAND_LOOPSIZE, MT_OPERAND_IMM16L, MT_OPERAND_RC3, MT_OPERAND_CB1SEL
+ , MT_OPERAND_CB2SEL, MT_OPERAND_CB1INCR, MT_OPERAND_CB2INCR, MT_OPERAND_MAX
} CGEN_OPERAND_TYPE;
/* Number of operands types. */
/* cgen.h uses things we just defined. */
#include "opcode/cgen.h"
-extern const struct cgen_ifld ms1_cgen_ifld_table[];
+extern const struct cgen_ifld mt_cgen_ifld_table[];
/* Attributes. */
-extern const CGEN_ATTR_TABLE ms1_cgen_hardware_attr_table[];
-extern const CGEN_ATTR_TABLE ms1_cgen_ifield_attr_table[];
-extern const CGEN_ATTR_TABLE ms1_cgen_operand_attr_table[];
-extern const CGEN_ATTR_TABLE ms1_cgen_insn_attr_table[];
+extern const CGEN_ATTR_TABLE mt_cgen_hardware_attr_table[];
+extern const CGEN_ATTR_TABLE mt_cgen_ifield_attr_table[];
+extern const CGEN_ATTR_TABLE mt_cgen_operand_attr_table[];
+extern const CGEN_ATTR_TABLE mt_cgen_insn_attr_table[];
/* Hardware decls. */
-extern CGEN_KEYWORD ms1_cgen_opval_h_spr;
+extern CGEN_KEYWORD mt_cgen_opval_h_spr;
-extern const CGEN_HW_ENTRY ms1_cgen_hw_table[];
+extern const CGEN_HW_ENTRY mt_cgen_hw_table[];
-#endif /* MS1_CPU_H */
+#endif /* MT_CPU_H */
#include "bfd.h"
#include "symcat.h"
#include "libiberty.h"
-#include "ms1-desc.h"
-#include "ms1-opc.h"
+#include "mt-desc.h"
+#include "mt-opc.h"
#include "opintl.h"
/* Default text to print if an instruction isn't recognized. */
/* -- */
-void ms1_cgen_print_operand
+void mt_cgen_print_operand
(CGEN_CPU_DESC, int, PTR, CGEN_FIELDS *, void const *, bfd_vma, int);
/* Main entry point for printing operands.
the handlers. */
void
-ms1_cgen_print_operand (CGEN_CPU_DESC cd,
+mt_cgen_print_operand (CGEN_CPU_DESC cd,
int opindex,
void * xinfo,
CGEN_FIELDS *fields,
switch (opindex)
{
- case MS1_OPERAND_A23 :
+ case MT_OPERAND_A23 :
print_dollarhex (cd, info, fields->f_a23, 0, pc, length);
break;
- case MS1_OPERAND_BALL :
+ case MT_OPERAND_BALL :
print_dollarhex (cd, info, fields->f_ball, 0, pc, length);
break;
- case MS1_OPERAND_BALL2 :
+ case MT_OPERAND_BALL2 :
print_dollarhex (cd, info, fields->f_ball2, 0, pc, length);
break;
- case MS1_OPERAND_BANKADDR :
+ case MT_OPERAND_BANKADDR :
print_dollarhex (cd, info, fields->f_bankaddr, 0, pc, length);
break;
- case MS1_OPERAND_BRC :
+ case MT_OPERAND_BRC :
print_dollarhex (cd, info, fields->f_brc, 0, pc, length);
break;
- case MS1_OPERAND_BRC2 :
+ case MT_OPERAND_BRC2 :
print_dollarhex (cd, info, fields->f_brc2, 0, pc, length);
break;
- case MS1_OPERAND_CB1INCR :
+ case MT_OPERAND_CB1INCR :
print_dollarhex (cd, info, fields->f_cb1incr, 0|(1<<CGEN_OPERAND_SIGNED), pc, length);
break;
- case MS1_OPERAND_CB1SEL :
+ case MT_OPERAND_CB1SEL :
print_dollarhex (cd, info, fields->f_cb1sel, 0, pc, length);
break;
- case MS1_OPERAND_CB2INCR :
+ case MT_OPERAND_CB2INCR :
print_dollarhex (cd, info, fields->f_cb2incr, 0|(1<<CGEN_OPERAND_SIGNED), pc, length);
break;
- case MS1_OPERAND_CB2SEL :
+ case MT_OPERAND_CB2SEL :
print_dollarhex (cd, info, fields->f_cb2sel, 0, pc, length);
break;
- case MS1_OPERAND_CBRB :
+ case MT_OPERAND_CBRB :
print_dollarhex (cd, info, fields->f_cbrb, 0, pc, length);
break;
- case MS1_OPERAND_CBS :
+ case MT_OPERAND_CBS :
print_dollarhex (cd, info, fields->f_cbs, 0, pc, length);
break;
- case MS1_OPERAND_CBX :
+ case MT_OPERAND_CBX :
print_dollarhex (cd, info, fields->f_cbx, 0, pc, length);
break;
- case MS1_OPERAND_CCB :
+ case MT_OPERAND_CCB :
print_dollarhex (cd, info, fields->f_ccb, 0, pc, length);
break;
- case MS1_OPERAND_CDB :
+ case MT_OPERAND_CDB :
print_dollarhex (cd, info, fields->f_cdb, 0, pc, length);
break;
- case MS1_OPERAND_CELL :
+ case MT_OPERAND_CELL :
print_dollarhex (cd, info, fields->f_cell, 0, pc, length);
break;
- case MS1_OPERAND_COLNUM :
+ case MT_OPERAND_COLNUM :
print_dollarhex (cd, info, fields->f_colnum, 0, pc, length);
break;
- case MS1_OPERAND_CONTNUM :
+ case MT_OPERAND_CONTNUM :
print_dollarhex (cd, info, fields->f_contnum, 0, pc, length);
break;
- case MS1_OPERAND_CR :
+ case MT_OPERAND_CR :
print_dollarhex (cd, info, fields->f_cr, 0, pc, length);
break;
- case MS1_OPERAND_CTXDISP :
+ case MT_OPERAND_CTXDISP :
print_dollarhex (cd, info, fields->f_ctxdisp, 0, pc, length);
break;
- case MS1_OPERAND_DUP :
+ case MT_OPERAND_DUP :
print_dollarhex (cd, info, fields->f_dup, 0, pc, length);
break;
- case MS1_OPERAND_FBDISP :
+ case MT_OPERAND_FBDISP :
print_dollarhex (cd, info, fields->f_fbdisp, 0, pc, length);
break;
- case MS1_OPERAND_FBINCR :
+ case MT_OPERAND_FBINCR :
print_dollarhex (cd, info, fields->f_fbincr, 0, pc, length);
break;
- case MS1_OPERAND_FRDR :
- print_keyword (cd, info, & ms1_cgen_opval_h_spr, fields->f_dr, 0|(1<<CGEN_OPERAND_ABS_ADDR));
+ case MT_OPERAND_FRDR :
+ print_keyword (cd, info, & mt_cgen_opval_h_spr, fields->f_dr, 0|(1<<CGEN_OPERAND_ABS_ADDR));
break;
- case MS1_OPERAND_FRDRRR :
- print_keyword (cd, info, & ms1_cgen_opval_h_spr, fields->f_drrr, 0|(1<<CGEN_OPERAND_ABS_ADDR));
+ case MT_OPERAND_FRDRRR :
+ print_keyword (cd, info, & mt_cgen_opval_h_spr, fields->f_drrr, 0|(1<<CGEN_OPERAND_ABS_ADDR));
break;
- case MS1_OPERAND_FRSR1 :
- print_keyword (cd, info, & ms1_cgen_opval_h_spr, fields->f_sr1, 0|(1<<CGEN_OPERAND_ABS_ADDR));
+ case MT_OPERAND_FRSR1 :
+ print_keyword (cd, info, & mt_cgen_opval_h_spr, fields->f_sr1, 0|(1<<CGEN_OPERAND_ABS_ADDR));
break;
- case MS1_OPERAND_FRSR2 :
- print_keyword (cd, info, & ms1_cgen_opval_h_spr, fields->f_sr2, 0|(1<<CGEN_OPERAND_ABS_ADDR));
+ case MT_OPERAND_FRSR2 :
+ print_keyword (cd, info, & mt_cgen_opval_h_spr, fields->f_sr2, 0|(1<<CGEN_OPERAND_ABS_ADDR));
break;
- case MS1_OPERAND_ID :
+ case MT_OPERAND_ID :
print_dollarhex (cd, info, fields->f_id, 0, pc, length);
break;
- case MS1_OPERAND_IMM16 :
+ case MT_OPERAND_IMM16 :
print_dollarhex (cd, info, fields->f_imm16s, 0|(1<<CGEN_OPERAND_SIGNED), pc, length);
break;
- case MS1_OPERAND_IMM16L :
+ case MT_OPERAND_IMM16L :
print_dollarhex (cd, info, fields->f_imm16l, 0, pc, length);
break;
- case MS1_OPERAND_IMM16O :
+ case MT_OPERAND_IMM16O :
print_pcrel (cd, info, fields->f_imm16s, 0|(1<<CGEN_OPERAND_PCREL_ADDR), pc, length);
break;
- case MS1_OPERAND_IMM16Z :
+ case MT_OPERAND_IMM16Z :
print_dollarhex (cd, info, fields->f_imm16u, 0, pc, length);
break;
- case MS1_OPERAND_INCAMT :
+ case MT_OPERAND_INCAMT :
print_dollarhex (cd, info, fields->f_incamt, 0, pc, length);
break;
- case MS1_OPERAND_INCR :
+ case MT_OPERAND_INCR :
print_dollarhex (cd, info, fields->f_incr, 0, pc, length);
break;
- case MS1_OPERAND_LENGTH :
+ case MT_OPERAND_LENGTH :
print_dollarhex (cd, info, fields->f_length, 0, pc, length);
break;
- case MS1_OPERAND_LOOPSIZE :
+ case MT_OPERAND_LOOPSIZE :
print_pcrel (cd, info, fields->f_loopo, 0|(1<<CGEN_OPERAND_PCREL_ADDR), pc, length);
break;
- case MS1_OPERAND_MASK :
+ case MT_OPERAND_MASK :
print_dollarhex (cd, info, fields->f_mask, 0, pc, length);
break;
- case MS1_OPERAND_MASK1 :
+ case MT_OPERAND_MASK1 :
print_dollarhex (cd, info, fields->f_mask1, 0, pc, length);
break;
- case MS1_OPERAND_MODE :
+ case MT_OPERAND_MODE :
print_dollarhex (cd, info, fields->f_mode, 0, pc, length);
break;
- case MS1_OPERAND_PERM :
+ case MT_OPERAND_PERM :
print_dollarhex (cd, info, fields->f_perm, 0, pc, length);
break;
- case MS1_OPERAND_RBBC :
+ case MT_OPERAND_RBBC :
print_dollarhex (cd, info, fields->f_rbbc, 0, pc, length);
break;
- case MS1_OPERAND_RC :
+ case MT_OPERAND_RC :
print_dollarhex (cd, info, fields->f_rc, 0, pc, length);
break;
- case MS1_OPERAND_RC1 :
+ case MT_OPERAND_RC1 :
print_dollarhex (cd, info, fields->f_rc1, 0, pc, length);
break;
- case MS1_OPERAND_RC2 :
+ case MT_OPERAND_RC2 :
print_dollarhex (cd, info, fields->f_rc2, 0, pc, length);
break;
- case MS1_OPERAND_RC3 :
+ case MT_OPERAND_RC3 :
print_dollarhex (cd, info, fields->f_rc3, 0, pc, length);
break;
- case MS1_OPERAND_RCNUM :
+ case MT_OPERAND_RCNUM :
print_dollarhex (cd, info, fields->f_rcnum, 0, pc, length);
break;
- case MS1_OPERAND_RDA :
+ case MT_OPERAND_RDA :
print_dollarhex (cd, info, fields->f_rda, 0, pc, length);
break;
- case MS1_OPERAND_ROWNUM :
+ case MT_OPERAND_ROWNUM :
print_dollarhex (cd, info, fields->f_rownum, 0, pc, length);
break;
- case MS1_OPERAND_ROWNUM1 :
+ case MT_OPERAND_ROWNUM1 :
print_dollarhex (cd, info, fields->f_rownum1, 0, pc, length);
break;
- case MS1_OPERAND_ROWNUM2 :
+ case MT_OPERAND_ROWNUM2 :
print_dollarhex (cd, info, fields->f_rownum2, 0, pc, length);
break;
- case MS1_OPERAND_SIZE :
+ case MT_OPERAND_SIZE :
print_dollarhex (cd, info, fields->f_size, 0, pc, length);
break;
- case MS1_OPERAND_TYPE :
+ case MT_OPERAND_TYPE :
print_dollarhex (cd, info, fields->f_type, 0, pc, length);
break;
- case MS1_OPERAND_WR :
+ case MT_OPERAND_WR :
print_dollarhex (cd, info, fields->f_wr, 0, pc, length);
break;
- case MS1_OPERAND_XMODE :
+ case MT_OPERAND_XMODE :
print_dollarhex (cd, info, fields->f_xmode, 0, pc, length);
break;
}
}
-cgen_print_fn * const ms1_cgen_print_handlers[] =
+cgen_print_fn * const mt_cgen_print_handlers[] =
{
print_insn_normal,
};
void
-ms1_cgen_init_dis (CGEN_CPU_DESC cd)
+mt_cgen_init_dis (CGEN_CPU_DESC cd)
{
- ms1_cgen_init_opcode_table (cd);
- ms1_cgen_init_ibld_table (cd);
- cd->print_handlers = & ms1_cgen_print_handlers[0];
- cd->print_operand = ms1_cgen_print_operand;
+ mt_cgen_init_opcode_table (cd);
+ mt_cgen_init_ibld_table (cd);
+ cd->print_handlers = & mt_cgen_print_handlers[0];
+ cd->print_operand = mt_cgen_print_operand;
}
\f
}
/* We have an operand. */
- ms1_cgen_print_operand (cd, CGEN_SYNTAX_FIELD (*syn), info,
+ mt_cgen_print_operand (cd, CGEN_SYNTAX_FIELD (*syn), info,
fields, CGEN_INSN_ATTRS (insn), pc, length);
}
}
#ifdef CGEN_VALIDATE_INSN_SUPPORTED
/* Not needed as insn shouldn't be in hash lists if not supported. */
/* Supported by this cpu? */
- if (! ms1_cgen_insn_supported (cd, insn))
+ if (! mt_cgen_insn_supported (cd, insn))
{
insn_list = CGEN_DIS_NEXT_INSN (insn_list);
continue;
} cpu_desc_list;
int
-print_insn_ms1 (bfd_vma pc, disassemble_info *info)
+print_insn_mt (bfd_vma pc, disassemble_info *info)
{
static cpu_desc_list *cd_list = 0;
cpu_desc_list *cl = 0;
/* ??? gdb will set mach but leave the architecture as "unknown" */
#ifndef CGEN_BFD_ARCH
-#define CGEN_BFD_ARCH bfd_arch_ms1
+#define CGEN_BFD_ARCH bfd_arch_mt
#endif
arch = info->arch;
if (arch == bfd_arch_unknown)
prev_isa = cgen_bitset_copy (isa);
prev_mach = mach;
prev_endian = endian;
- cd = ms1_cgen_cpu_open (CGEN_CPU_OPEN_ISAS, prev_isa,
+ cd = mt_cgen_cpu_open (CGEN_CPU_OPEN_ISAS, prev_isa,
CGEN_CPU_OPEN_BFDMACH, mach_name,
CGEN_CPU_OPEN_ENDIAN, prev_endian,
CGEN_CPU_OPEN_END);
cl->next = cd_list;
cd_list = cl;
- ms1_cgen_init_dis (cd);
+ mt_cgen_init_dis (cd);
}
/* We try to have as much common code as possible.
-/* Instruction building/extraction support for ms1. -*- C -*-
+/* Instruction building/extraction support for mt. -*- C -*-
THIS FILE IS MACHINE GENERATED WITH CGEN: Cpu tools GENerator.
- the resultant file is machine generated, cgen-ibld.in isn't
#include "dis-asm.h"
#include "bfd.h"
#include "symcat.h"
-#include "ms1-desc.h"
-#include "ms1-opc.h"
+#include "mt-desc.h"
+#include "mt-opc.h"
#include "opintl.h"
#include "safe-ctype.h"
\f
/* Machine generated code added here. */
-const char * ms1_cgen_insert_operand
+const char * mt_cgen_insert_operand
(CGEN_CPU_DESC, int, CGEN_FIELDS *, CGEN_INSN_BYTES_PTR, bfd_vma);
/* Main entry point for operand insertion.
resolved during parsing. */
const char *
-ms1_cgen_insert_operand (CGEN_CPU_DESC cd,
+mt_cgen_insert_operand (CGEN_CPU_DESC cd,
int opindex,
CGEN_FIELDS * fields,
CGEN_INSN_BYTES_PTR buffer,
switch (opindex)
{
- case MS1_OPERAND_A23 :
+ case MT_OPERAND_A23 :
errmsg = insert_normal (cd, fields->f_a23, 0, 0, 23, 1, 32, total_length, buffer);
break;
- case MS1_OPERAND_BALL :
+ case MT_OPERAND_BALL :
errmsg = insert_normal (cd, fields->f_ball, 0, 0, 19, 1, 32, total_length, buffer);
break;
- case MS1_OPERAND_BALL2 :
+ case MT_OPERAND_BALL2 :
errmsg = insert_normal (cd, fields->f_ball2, 0, 0, 15, 1, 32, total_length, buffer);
break;
- case MS1_OPERAND_BANKADDR :
+ case MT_OPERAND_BANKADDR :
errmsg = insert_normal (cd, fields->f_bankaddr, 0, 0, 25, 13, 32, total_length, buffer);
break;
- case MS1_OPERAND_BRC :
+ case MT_OPERAND_BRC :
errmsg = insert_normal (cd, fields->f_brc, 0, 0, 18, 3, 32, total_length, buffer);
break;
- case MS1_OPERAND_BRC2 :
+ case MT_OPERAND_BRC2 :
errmsg = insert_normal (cd, fields->f_brc2, 0, 0, 14, 3, 32, total_length, buffer);
break;
- case MS1_OPERAND_CB1INCR :
+ case MT_OPERAND_CB1INCR :
errmsg = insert_normal (cd, fields->f_cb1incr, 0|(1<<CGEN_IFLD_SIGNED), 0, 19, 6, 32, total_length, buffer);
break;
- case MS1_OPERAND_CB1SEL :
+ case MT_OPERAND_CB1SEL :
errmsg = insert_normal (cd, fields->f_cb1sel, 0, 0, 25, 3, 32, total_length, buffer);
break;
- case MS1_OPERAND_CB2INCR :
+ case MT_OPERAND_CB2INCR :
errmsg = insert_normal (cd, fields->f_cb2incr, 0|(1<<CGEN_IFLD_SIGNED), 0, 13, 6, 32, total_length, buffer);
break;
- case MS1_OPERAND_CB2SEL :
+ case MT_OPERAND_CB2SEL :
errmsg = insert_normal (cd, fields->f_cb2sel, 0, 0, 22, 3, 32, total_length, buffer);
break;
- case MS1_OPERAND_CBRB :
+ case MT_OPERAND_CBRB :
errmsg = insert_normal (cd, fields->f_cbrb, 0, 0, 10, 1, 32, total_length, buffer);
break;
- case MS1_OPERAND_CBS :
+ case MT_OPERAND_CBS :
errmsg = insert_normal (cd, fields->f_cbs, 0, 0, 19, 2, 32, total_length, buffer);
break;
- case MS1_OPERAND_CBX :
+ case MT_OPERAND_CBX :
errmsg = insert_normal (cd, fields->f_cbx, 0, 0, 14, 3, 32, total_length, buffer);
break;
- case MS1_OPERAND_CCB :
+ case MT_OPERAND_CCB :
errmsg = insert_normal (cd, fields->f_ccb, 0, 0, 11, 1, 32, total_length, buffer);
break;
- case MS1_OPERAND_CDB :
+ case MT_OPERAND_CDB :
errmsg = insert_normal (cd, fields->f_cdb, 0, 0, 10, 1, 32, total_length, buffer);
break;
- case MS1_OPERAND_CELL :
+ case MT_OPERAND_CELL :
errmsg = insert_normal (cd, fields->f_cell, 0, 0, 9, 3, 32, total_length, buffer);
break;
- case MS1_OPERAND_COLNUM :
+ case MT_OPERAND_COLNUM :
errmsg = insert_normal (cd, fields->f_colnum, 0, 0, 18, 3, 32, total_length, buffer);
break;
- case MS1_OPERAND_CONTNUM :
+ case MT_OPERAND_CONTNUM :
errmsg = insert_normal (cd, fields->f_contnum, 0, 0, 8, 9, 32, total_length, buffer);
break;
- case MS1_OPERAND_CR :
+ case MT_OPERAND_CR :
errmsg = insert_normal (cd, fields->f_cr, 0, 0, 22, 3, 32, total_length, buffer);
break;
- case MS1_OPERAND_CTXDISP :
+ case MT_OPERAND_CTXDISP :
errmsg = insert_normal (cd, fields->f_ctxdisp, 0, 0, 5, 6, 32, total_length, buffer);
break;
- case MS1_OPERAND_DUP :
+ case MT_OPERAND_DUP :
errmsg = insert_normal (cd, fields->f_dup, 0, 0, 6, 1, 32, total_length, buffer);
break;
- case MS1_OPERAND_FBDISP :
+ case MT_OPERAND_FBDISP :
errmsg = insert_normal (cd, fields->f_fbdisp, 0, 0, 15, 6, 32, total_length, buffer);
break;
- case MS1_OPERAND_FBINCR :
+ case MT_OPERAND_FBINCR :
errmsg = insert_normal (cd, fields->f_fbincr, 0, 0, 23, 4, 32, total_length, buffer);
break;
- case MS1_OPERAND_FRDR :
+ case MT_OPERAND_FRDR :
errmsg = insert_normal (cd, fields->f_dr, 0|(1<<CGEN_IFLD_ABS_ADDR), 0, 19, 4, 32, total_length, buffer);
break;
- case MS1_OPERAND_FRDRRR :
+ case MT_OPERAND_FRDRRR :
errmsg = insert_normal (cd, fields->f_drrr, 0|(1<<CGEN_IFLD_ABS_ADDR), 0, 15, 4, 32, total_length, buffer);
break;
- case MS1_OPERAND_FRSR1 :
+ case MT_OPERAND_FRSR1 :
errmsg = insert_normal (cd, fields->f_sr1, 0|(1<<CGEN_IFLD_ABS_ADDR), 0, 23, 4, 32, total_length, buffer);
break;
- case MS1_OPERAND_FRSR2 :
+ case MT_OPERAND_FRSR2 :
errmsg = insert_normal (cd, fields->f_sr2, 0|(1<<CGEN_IFLD_ABS_ADDR), 0, 19, 4, 32, total_length, buffer);
break;
- case MS1_OPERAND_ID :
+ case MT_OPERAND_ID :
errmsg = insert_normal (cd, fields->f_id, 0, 0, 14, 1, 32, total_length, buffer);
break;
- case MS1_OPERAND_IMM16 :
+ case MT_OPERAND_IMM16 :
{
long value = fields->f_imm16s;
value = ((value) + (0));
errmsg = insert_normal (cd, value, 0|(1<<CGEN_IFLD_SIGNED), 0, 15, 16, 32, total_length, buffer);
}
break;
- case MS1_OPERAND_IMM16L :
+ case MT_OPERAND_IMM16L :
errmsg = insert_normal (cd, fields->f_imm16l, 0, 0, 23, 16, 32, total_length, buffer);
break;
- case MS1_OPERAND_IMM16O :
+ case MT_OPERAND_IMM16O :
{
long value = fields->f_imm16s;
value = ((value) + (0));
errmsg = insert_normal (cd, value, 0|(1<<CGEN_IFLD_SIGNED), 0, 15, 16, 32, total_length, buffer);
}
break;
- case MS1_OPERAND_IMM16Z :
+ case MT_OPERAND_IMM16Z :
errmsg = insert_normal (cd, fields->f_imm16u, 0, 0, 15, 16, 32, total_length, buffer);
break;
- case MS1_OPERAND_INCAMT :
+ case MT_OPERAND_INCAMT :
errmsg = insert_normal (cd, fields->f_incamt, 0, 0, 19, 8, 32, total_length, buffer);
break;
- case MS1_OPERAND_INCR :
+ case MT_OPERAND_INCR :
errmsg = insert_normal (cd, fields->f_incr, 0, 0, 17, 6, 32, total_length, buffer);
break;
- case MS1_OPERAND_LENGTH :
+ case MT_OPERAND_LENGTH :
errmsg = insert_normal (cd, fields->f_length, 0, 0, 15, 3, 32, total_length, buffer);
break;
- case MS1_OPERAND_LOOPSIZE :
+ case MT_OPERAND_LOOPSIZE :
{
long value = fields->f_loopo;
value = ((unsigned int) (value) >> (2));
errmsg = insert_normal (cd, value, 0, 0, 7, 8, 32, total_length, buffer);
}
break;
- case MS1_OPERAND_MASK :
+ case MT_OPERAND_MASK :
errmsg = insert_normal (cd, fields->f_mask, 0, 0, 25, 16, 32, total_length, buffer);
break;
- case MS1_OPERAND_MASK1 :
+ case MT_OPERAND_MASK1 :
errmsg = insert_normal (cd, fields->f_mask1, 0, 0, 22, 3, 32, total_length, buffer);
break;
- case MS1_OPERAND_MODE :
+ case MT_OPERAND_MODE :
errmsg = insert_normal (cd, fields->f_mode, 0, 0, 25, 2, 32, total_length, buffer);
break;
- case MS1_OPERAND_PERM :
+ case MT_OPERAND_PERM :
errmsg = insert_normal (cd, fields->f_perm, 0, 0, 25, 2, 32, total_length, buffer);
break;
- case MS1_OPERAND_RBBC :
+ case MT_OPERAND_RBBC :
errmsg = insert_normal (cd, fields->f_rbbc, 0, 0, 25, 2, 32, total_length, buffer);
break;
- case MS1_OPERAND_RC :
+ case MT_OPERAND_RC :
errmsg = insert_normal (cd, fields->f_rc, 0, 0, 15, 1, 32, total_length, buffer);
break;
- case MS1_OPERAND_RC1 :
+ case MT_OPERAND_RC1 :
errmsg = insert_normal (cd, fields->f_rc1, 0, 0, 11, 1, 32, total_length, buffer);
break;
- case MS1_OPERAND_RC2 :
+ case MT_OPERAND_RC2 :
errmsg = insert_normal (cd, fields->f_rc2, 0, 0, 6, 1, 32, total_length, buffer);
break;
- case MS1_OPERAND_RC3 :
+ case MT_OPERAND_RC3 :
errmsg = insert_normal (cd, fields->f_rc3, 0, 0, 7, 1, 32, total_length, buffer);
break;
- case MS1_OPERAND_RCNUM :
+ case MT_OPERAND_RCNUM :
errmsg = insert_normal (cd, fields->f_rcnum, 0, 0, 14, 3, 32, total_length, buffer);
break;
- case MS1_OPERAND_RDA :
+ case MT_OPERAND_RDA :
errmsg = insert_normal (cd, fields->f_rda, 0, 0, 25, 1, 32, total_length, buffer);
break;
- case MS1_OPERAND_ROWNUM :
+ case MT_OPERAND_ROWNUM :
errmsg = insert_normal (cd, fields->f_rownum, 0, 0, 14, 3, 32, total_length, buffer);
break;
- case MS1_OPERAND_ROWNUM1 :
+ case MT_OPERAND_ROWNUM1 :
errmsg = insert_normal (cd, fields->f_rownum1, 0, 0, 12, 3, 32, total_length, buffer);
break;
- case MS1_OPERAND_ROWNUM2 :
+ case MT_OPERAND_ROWNUM2 :
errmsg = insert_normal (cd, fields->f_rownum2, 0, 0, 9, 3, 32, total_length, buffer);
break;
- case MS1_OPERAND_SIZE :
+ case MT_OPERAND_SIZE :
errmsg = insert_normal (cd, fields->f_size, 0, 0, 13, 14, 32, total_length, buffer);
break;
- case MS1_OPERAND_TYPE :
+ case MT_OPERAND_TYPE :
errmsg = insert_normal (cd, fields->f_type, 0, 0, 21, 2, 32, total_length, buffer);
break;
- case MS1_OPERAND_WR :
+ case MT_OPERAND_WR :
errmsg = insert_normal (cd, fields->f_wr, 0, 0, 24, 1, 32, total_length, buffer);
break;
- case MS1_OPERAND_XMODE :
+ case MT_OPERAND_XMODE :
errmsg = insert_normal (cd, fields->f_xmode, 0, 0, 23, 1, 32, total_length, buffer);
break;
return errmsg;
}
-int ms1_cgen_extract_operand
+int mt_cgen_extract_operand
(CGEN_CPU_DESC, int, CGEN_EXTRACT_INFO *, CGEN_INSN_INT, CGEN_FIELDS *, bfd_vma);
/* Main entry point for operand extraction.
the handlers. */
int
-ms1_cgen_extract_operand (CGEN_CPU_DESC cd,
+mt_cgen_extract_operand (CGEN_CPU_DESC cd,
int opindex,
CGEN_EXTRACT_INFO *ex_info,
CGEN_INSN_INT insn_value,
switch (opindex)
{
- case MS1_OPERAND_A23 :
+ case MT_OPERAND_A23 :
length = extract_normal (cd, ex_info, insn_value, 0, 0, 23, 1, 32, total_length, pc, & fields->f_a23);
break;
- case MS1_OPERAND_BALL :
+ case MT_OPERAND_BALL :
length = extract_normal (cd, ex_info, insn_value, 0, 0, 19, 1, 32, total_length, pc, & fields->f_ball);
break;
- case MS1_OPERAND_BALL2 :
+ case MT_OPERAND_BALL2 :
length = extract_normal (cd, ex_info, insn_value, 0, 0, 15, 1, 32, total_length, pc, & fields->f_ball2);
break;
- case MS1_OPERAND_BANKADDR :
+ case MT_OPERAND_BANKADDR :
length = extract_normal (cd, ex_info, insn_value, 0, 0, 25, 13, 32, total_length, pc, & fields->f_bankaddr);
break;
- case MS1_OPERAND_BRC :
+ case MT_OPERAND_BRC :
length = extract_normal (cd, ex_info, insn_value, 0, 0, 18, 3, 32, total_length, pc, & fields->f_brc);
break;
- case MS1_OPERAND_BRC2 :
+ case MT_OPERAND_BRC2 :
length = extract_normal (cd, ex_info, insn_value, 0, 0, 14, 3, 32, total_length, pc, & fields->f_brc2);
break;
- case MS1_OPERAND_CB1INCR :
+ case MT_OPERAND_CB1INCR :
length = extract_normal (cd, ex_info, insn_value, 0|(1<<CGEN_IFLD_SIGNED), 0, 19, 6, 32, total_length, pc, & fields->f_cb1incr);
break;
- case MS1_OPERAND_CB1SEL :
+ case MT_OPERAND_CB1SEL :
length = extract_normal (cd, ex_info, insn_value, 0, 0, 25, 3, 32, total_length, pc, & fields->f_cb1sel);
break;
- case MS1_OPERAND_CB2INCR :
+ case MT_OPERAND_CB2INCR :
length = extract_normal (cd, ex_info, insn_value, 0|(1<<CGEN_IFLD_SIGNED), 0, 13, 6, 32, total_length, pc, & fields->f_cb2incr);
break;
- case MS1_OPERAND_CB2SEL :
+ case MT_OPERAND_CB2SEL :
length = extract_normal (cd, ex_info, insn_value, 0, 0, 22, 3, 32, total_length, pc, & fields->f_cb2sel);
break;
- case MS1_OPERAND_CBRB :
+ case MT_OPERAND_CBRB :
length = extract_normal (cd, ex_info, insn_value, 0, 0, 10, 1, 32, total_length, pc, & fields->f_cbrb);
break;
- case MS1_OPERAND_CBS :
+ case MT_OPERAND_CBS :
length = extract_normal (cd, ex_info, insn_value, 0, 0, 19, 2, 32, total_length, pc, & fields->f_cbs);
break;
- case MS1_OPERAND_CBX :
+ case MT_OPERAND_CBX :
length = extract_normal (cd, ex_info, insn_value, 0, 0, 14, 3, 32, total_length, pc, & fields->f_cbx);
break;
- case MS1_OPERAND_CCB :
+ case MT_OPERAND_CCB :
length = extract_normal (cd, ex_info, insn_value, 0, 0, 11, 1, 32, total_length, pc, & fields->f_ccb);
break;
- case MS1_OPERAND_CDB :
+ case MT_OPERAND_CDB :
length = extract_normal (cd, ex_info, insn_value, 0, 0, 10, 1, 32, total_length, pc, & fields->f_cdb);
break;
- case MS1_OPERAND_CELL :
+ case MT_OPERAND_CELL :
length = extract_normal (cd, ex_info, insn_value, 0, 0, 9, 3, 32, total_length, pc, & fields->f_cell);
break;
- case MS1_OPERAND_COLNUM :
+ case MT_OPERAND_COLNUM :
length = extract_normal (cd, ex_info, insn_value, 0, 0, 18, 3, 32, total_length, pc, & fields->f_colnum);
break;
- case MS1_OPERAND_CONTNUM :
+ case MT_OPERAND_CONTNUM :
length = extract_normal (cd, ex_info, insn_value, 0, 0, 8, 9, 32, total_length, pc, & fields->f_contnum);
break;
- case MS1_OPERAND_CR :
+ case MT_OPERAND_CR :
length = extract_normal (cd, ex_info, insn_value, 0, 0, 22, 3, 32, total_length, pc, & fields->f_cr);
break;
- case MS1_OPERAND_CTXDISP :
+ case MT_OPERAND_CTXDISP :
length = extract_normal (cd, ex_info, insn_value, 0, 0, 5, 6, 32, total_length, pc, & fields->f_ctxdisp);
break;
- case MS1_OPERAND_DUP :
+ case MT_OPERAND_DUP :
length = extract_normal (cd, ex_info, insn_value, 0, 0, 6, 1, 32, total_length, pc, & fields->f_dup);
break;
- case MS1_OPERAND_FBDISP :
+ case MT_OPERAND_FBDISP :
length = extract_normal (cd, ex_info, insn_value, 0, 0, 15, 6, 32, total_length, pc, & fields->f_fbdisp);
break;
- case MS1_OPERAND_FBINCR :
+ case MT_OPERAND_FBINCR :
length = extract_normal (cd, ex_info, insn_value, 0, 0, 23, 4, 32, total_length, pc, & fields->f_fbincr);
break;
- case MS1_OPERAND_FRDR :
+ case MT_OPERAND_FRDR :
length = extract_normal (cd, ex_info, insn_value, 0|(1<<CGEN_IFLD_ABS_ADDR), 0, 19, 4, 32, total_length, pc, & fields->f_dr);
break;
- case MS1_OPERAND_FRDRRR :
+ case MT_OPERAND_FRDRRR :
length = extract_normal (cd, ex_info, insn_value, 0|(1<<CGEN_IFLD_ABS_ADDR), 0, 15, 4, 32, total_length, pc, & fields->f_drrr);
break;
- case MS1_OPERAND_FRSR1 :
+ case MT_OPERAND_FRSR1 :
length = extract_normal (cd, ex_info, insn_value, 0|(1<<CGEN_IFLD_ABS_ADDR), 0, 23, 4, 32, total_length, pc, & fields->f_sr1);
break;
- case MS1_OPERAND_FRSR2 :
+ case MT_OPERAND_FRSR2 :
length = extract_normal (cd, ex_info, insn_value, 0|(1<<CGEN_IFLD_ABS_ADDR), 0, 19, 4, 32, total_length, pc, & fields->f_sr2);
break;
- case MS1_OPERAND_ID :
+ case MT_OPERAND_ID :
length = extract_normal (cd, ex_info, insn_value, 0, 0, 14, 1, 32, total_length, pc, & fields->f_id);
break;
- case MS1_OPERAND_IMM16 :
+ case MT_OPERAND_IMM16 :
{
long value;
length = extract_normal (cd, ex_info, insn_value, 0|(1<<CGEN_IFLD_SIGNED), 0, 15, 16, 32, total_length, pc, & value);
fields->f_imm16s = value;
}
break;
- case MS1_OPERAND_IMM16L :
+ case MT_OPERAND_IMM16L :
length = extract_normal (cd, ex_info, insn_value, 0, 0, 23, 16, 32, total_length, pc, & fields->f_imm16l);
break;
- case MS1_OPERAND_IMM16O :
+ case MT_OPERAND_IMM16O :
{
long value;
length = extract_normal (cd, ex_info, insn_value, 0|(1<<CGEN_IFLD_SIGNED), 0, 15, 16, 32, total_length, pc, & value);
fields->f_imm16s = value;
}
break;
- case MS1_OPERAND_IMM16Z :
+ case MT_OPERAND_IMM16Z :
length = extract_normal (cd, ex_info, insn_value, 0, 0, 15, 16, 32, total_length, pc, & fields->f_imm16u);
break;
- case MS1_OPERAND_INCAMT :
+ case MT_OPERAND_INCAMT :
length = extract_normal (cd, ex_info, insn_value, 0, 0, 19, 8, 32, total_length, pc, & fields->f_incamt);
break;
- case MS1_OPERAND_INCR :
+ case MT_OPERAND_INCR :
length = extract_normal (cd, ex_info, insn_value, 0, 0, 17, 6, 32, total_length, pc, & fields->f_incr);
break;
- case MS1_OPERAND_LENGTH :
+ case MT_OPERAND_LENGTH :
length = extract_normal (cd, ex_info, insn_value, 0, 0, 15, 3, 32, total_length, pc, & fields->f_length);
break;
- case MS1_OPERAND_LOOPSIZE :
+ case MT_OPERAND_LOOPSIZE :
{
long value;
length = extract_normal (cd, ex_info, insn_value, 0, 0, 7, 8, 32, total_length, pc, & value);
fields->f_loopo = value;
}
break;
- case MS1_OPERAND_MASK :
+ case MT_OPERAND_MASK :
length = extract_normal (cd, ex_info, insn_value, 0, 0, 25, 16, 32, total_length, pc, & fields->f_mask);
break;
- case MS1_OPERAND_MASK1 :
+ case MT_OPERAND_MASK1 :
length = extract_normal (cd, ex_info, insn_value, 0, 0, 22, 3, 32, total_length, pc, & fields->f_mask1);
break;
- case MS1_OPERAND_MODE :
+ case MT_OPERAND_MODE :
length = extract_normal (cd, ex_info, insn_value, 0, 0, 25, 2, 32, total_length, pc, & fields->f_mode);
break;
- case MS1_OPERAND_PERM :
+ case MT_OPERAND_PERM :
length = extract_normal (cd, ex_info, insn_value, 0, 0, 25, 2, 32, total_length, pc, & fields->f_perm);
break;
- case MS1_OPERAND_RBBC :
+ case MT_OPERAND_RBBC :
length = extract_normal (cd, ex_info, insn_value, 0, 0, 25, 2, 32, total_length, pc, & fields->f_rbbc);
break;
- case MS1_OPERAND_RC :
+ case MT_OPERAND_RC :
length = extract_normal (cd, ex_info, insn_value, 0, 0, 15, 1, 32, total_length, pc, & fields->f_rc);
break;
- case MS1_OPERAND_RC1 :
+ case MT_OPERAND_RC1 :
length = extract_normal (cd, ex_info, insn_value, 0, 0, 11, 1, 32, total_length, pc, & fields->f_rc1);
break;
- case MS1_OPERAND_RC2 :
+ case MT_OPERAND_RC2 :
length = extract_normal (cd, ex_info, insn_value, 0, 0, 6, 1, 32, total_length, pc, & fields->f_rc2);
break;
- case MS1_OPERAND_RC3 :
+ case MT_OPERAND_RC3 :
length = extract_normal (cd, ex_info, insn_value, 0, 0, 7, 1, 32, total_length, pc, & fields->f_rc3);
break;
- case MS1_OPERAND_RCNUM :
+ case MT_OPERAND_RCNUM :
length = extract_normal (cd, ex_info, insn_value, 0, 0, 14, 3, 32, total_length, pc, & fields->f_rcnum);
break;
- case MS1_OPERAND_RDA :
+ case MT_OPERAND_RDA :
length = extract_normal (cd, ex_info, insn_value, 0, 0, 25, 1, 32, total_length, pc, & fields->f_rda);
break;
- case MS1_OPERAND_ROWNUM :
+ case MT_OPERAND_ROWNUM :
length = extract_normal (cd, ex_info, insn_value, 0, 0, 14, 3, 32, total_length, pc, & fields->f_rownum);
break;
- case MS1_OPERAND_ROWNUM1 :
+ case MT_OPERAND_ROWNUM1 :
length = extract_normal (cd, ex_info, insn_value, 0, 0, 12, 3, 32, total_length, pc, & fields->f_rownum1);
break;
- case MS1_OPERAND_ROWNUM2 :
+ case MT_OPERAND_ROWNUM2 :
length = extract_normal (cd, ex_info, insn_value, 0, 0, 9, 3, 32, total_length, pc, & fields->f_rownum2);
break;
- case MS1_OPERAND_SIZE :
+ case MT_OPERAND_SIZE :
length = extract_normal (cd, ex_info, insn_value, 0, 0, 13, 14, 32, total_length, pc, & fields->f_size);
break;
- case MS1_OPERAND_TYPE :
+ case MT_OPERAND_TYPE :
length = extract_normal (cd, ex_info, insn_value, 0, 0, 21, 2, 32, total_length, pc, & fields->f_type);
break;
- case MS1_OPERAND_WR :
+ case MT_OPERAND_WR :
length = extract_normal (cd, ex_info, insn_value, 0, 0, 24, 1, 32, total_length, pc, & fields->f_wr);
break;
- case MS1_OPERAND_XMODE :
+ case MT_OPERAND_XMODE :
length = extract_normal (cd, ex_info, insn_value, 0, 0, 23, 1, 32, total_length, pc, & fields->f_xmode);
break;
return length;
}
-cgen_insert_fn * const ms1_cgen_insert_handlers[] =
+cgen_insert_fn * const mt_cgen_insert_handlers[] =
{
insert_insn_normal,
};
-cgen_extract_fn * const ms1_cgen_extract_handlers[] =
+cgen_extract_fn * const mt_cgen_extract_handlers[] =
{
extract_insn_normal,
};
-int ms1_cgen_get_int_operand (CGEN_CPU_DESC, int, const CGEN_FIELDS *);
-bfd_vma ms1_cgen_get_vma_operand (CGEN_CPU_DESC, int, const CGEN_FIELDS *);
+int mt_cgen_get_int_operand (CGEN_CPU_DESC, int, const CGEN_FIELDS *);
+bfd_vma mt_cgen_get_vma_operand (CGEN_CPU_DESC, int, const CGEN_FIELDS *);
/* Getting values from cgen_fields is handled by a collection of functions.
They are distinguished by the type of the VALUE argument they return.
not appropriate. */
int
-ms1_cgen_get_int_operand (CGEN_CPU_DESC cd ATTRIBUTE_UNUSED,
+mt_cgen_get_int_operand (CGEN_CPU_DESC cd ATTRIBUTE_UNUSED,
int opindex,
const CGEN_FIELDS * fields)
{
switch (opindex)
{
- case MS1_OPERAND_A23 :
+ case MT_OPERAND_A23 :
value = fields->f_a23;
break;
- case MS1_OPERAND_BALL :
+ case MT_OPERAND_BALL :
value = fields->f_ball;
break;
- case MS1_OPERAND_BALL2 :
+ case MT_OPERAND_BALL2 :
value = fields->f_ball2;
break;
- case MS1_OPERAND_BANKADDR :
+ case MT_OPERAND_BANKADDR :
value = fields->f_bankaddr;
break;
- case MS1_OPERAND_BRC :
+ case MT_OPERAND_BRC :
value = fields->f_brc;
break;
- case MS1_OPERAND_BRC2 :
+ case MT_OPERAND_BRC2 :
value = fields->f_brc2;
break;
- case MS1_OPERAND_CB1INCR :
+ case MT_OPERAND_CB1INCR :
value = fields->f_cb1incr;
break;
- case MS1_OPERAND_CB1SEL :
+ case MT_OPERAND_CB1SEL :
value = fields->f_cb1sel;
break;
- case MS1_OPERAND_CB2INCR :
+ case MT_OPERAND_CB2INCR :
value = fields->f_cb2incr;
break;
- case MS1_OPERAND_CB2SEL :
+ case MT_OPERAND_CB2SEL :
value = fields->f_cb2sel;
break;
- case MS1_OPERAND_CBRB :
+ case MT_OPERAND_CBRB :
value = fields->f_cbrb;
break;
- case MS1_OPERAND_CBS :
+ case MT_OPERAND_CBS :
value = fields->f_cbs;
break;
- case MS1_OPERAND_CBX :
+ case MT_OPERAND_CBX :
value = fields->f_cbx;
break;
- case MS1_OPERAND_CCB :
+ case MT_OPERAND_CCB :
value = fields->f_ccb;
break;
- case MS1_OPERAND_CDB :
+ case MT_OPERAND_CDB :
value = fields->f_cdb;
break;
- case MS1_OPERAND_CELL :
+ case MT_OPERAND_CELL :
value = fields->f_cell;
break;
- case MS1_OPERAND_COLNUM :
+ case MT_OPERAND_COLNUM :
value = fields->f_colnum;
break;
- case MS1_OPERAND_CONTNUM :
+ case MT_OPERAND_CONTNUM :
value = fields->f_contnum;
break;
- case MS1_OPERAND_CR :
+ case MT_OPERAND_CR :
value = fields->f_cr;
break;
- case MS1_OPERAND_CTXDISP :
+ case MT_OPERAND_CTXDISP :
value = fields->f_ctxdisp;
break;
- case MS1_OPERAND_DUP :
+ case MT_OPERAND_DUP :
value = fields->f_dup;
break;
- case MS1_OPERAND_FBDISP :
+ case MT_OPERAND_FBDISP :
value = fields->f_fbdisp;
break;
- case MS1_OPERAND_FBINCR :
+ case MT_OPERAND_FBINCR :
value = fields->f_fbincr;
break;
- case MS1_OPERAND_FRDR :
+ case MT_OPERAND_FRDR :
value = fields->f_dr;
break;
- case MS1_OPERAND_FRDRRR :
+ case MT_OPERAND_FRDRRR :
value = fields->f_drrr;
break;
- case MS1_OPERAND_FRSR1 :
+ case MT_OPERAND_FRSR1 :
value = fields->f_sr1;
break;
- case MS1_OPERAND_FRSR2 :
+ case MT_OPERAND_FRSR2 :
value = fields->f_sr2;
break;
- case MS1_OPERAND_ID :
+ case MT_OPERAND_ID :
value = fields->f_id;
break;
- case MS1_OPERAND_IMM16 :
+ case MT_OPERAND_IMM16 :
value = fields->f_imm16s;
break;
- case MS1_OPERAND_IMM16L :
+ case MT_OPERAND_IMM16L :
value = fields->f_imm16l;
break;
- case MS1_OPERAND_IMM16O :
+ case MT_OPERAND_IMM16O :
value = fields->f_imm16s;
break;
- case MS1_OPERAND_IMM16Z :
+ case MT_OPERAND_IMM16Z :
value = fields->f_imm16u;
break;
- case MS1_OPERAND_INCAMT :
+ case MT_OPERAND_INCAMT :
value = fields->f_incamt;
break;
- case MS1_OPERAND_INCR :
+ case MT_OPERAND_INCR :
value = fields->f_incr;
break;
- case MS1_OPERAND_LENGTH :
+ case MT_OPERAND_LENGTH :
value = fields->f_length;
break;
- case MS1_OPERAND_LOOPSIZE :
+ case MT_OPERAND_LOOPSIZE :
value = fields->f_loopo;
break;
- case MS1_OPERAND_MASK :
+ case MT_OPERAND_MASK :
value = fields->f_mask;
break;
- case MS1_OPERAND_MASK1 :
+ case MT_OPERAND_MASK1 :
value = fields->f_mask1;
break;
- case MS1_OPERAND_MODE :
+ case MT_OPERAND_MODE :
value = fields->f_mode;
break;
- case MS1_OPERAND_PERM :
+ case MT_OPERAND_PERM :
value = fields->f_perm;
break;
- case MS1_OPERAND_RBBC :
+ case MT_OPERAND_RBBC :
value = fields->f_rbbc;
break;
- case MS1_OPERAND_RC :
+ case MT_OPERAND_RC :
value = fields->f_rc;
break;
- case MS1_OPERAND_RC1 :
+ case MT_OPERAND_RC1 :
value = fields->f_rc1;
break;
- case MS1_OPERAND_RC2 :
+ case MT_OPERAND_RC2 :
value = fields->f_rc2;
break;
- case MS1_OPERAND_RC3 :
+ case MT_OPERAND_RC3 :
value = fields->f_rc3;
break;
- case MS1_OPERAND_RCNUM :
+ case MT_OPERAND_RCNUM :
value = fields->f_rcnum;
break;
- case MS1_OPERAND_RDA :
+ case MT_OPERAND_RDA :
value = fields->f_rda;
break;
- case MS1_OPERAND_ROWNUM :
+ case MT_OPERAND_ROWNUM :
value = fields->f_rownum;
break;
- case MS1_OPERAND_ROWNUM1 :
+ case MT_OPERAND_ROWNUM1 :
value = fields->f_rownum1;
break;
- case MS1_OPERAND_ROWNUM2 :
+ case MT_OPERAND_ROWNUM2 :
value = fields->f_rownum2;
break;
- case MS1_OPERAND_SIZE :
+ case MT_OPERAND_SIZE :
value = fields->f_size;
break;
- case MS1_OPERAND_TYPE :
+ case MT_OPERAND_TYPE :
value = fields->f_type;
break;
- case MS1_OPERAND_WR :
+ case MT_OPERAND_WR :
value = fields->f_wr;
break;
- case MS1_OPERAND_XMODE :
+ case MT_OPERAND_XMODE :
value = fields->f_xmode;
break;
}
bfd_vma
-ms1_cgen_get_vma_operand (CGEN_CPU_DESC cd ATTRIBUTE_UNUSED,
+mt_cgen_get_vma_operand (CGEN_CPU_DESC cd ATTRIBUTE_UNUSED,
int opindex,
const CGEN_FIELDS * fields)
{
switch (opindex)
{
- case MS1_OPERAND_A23 :
+ case MT_OPERAND_A23 :
value = fields->f_a23;
break;
- case MS1_OPERAND_BALL :
+ case MT_OPERAND_BALL :
value = fields->f_ball;
break;
- case MS1_OPERAND_BALL2 :
+ case MT_OPERAND_BALL2 :
value = fields->f_ball2;
break;
- case MS1_OPERAND_BANKADDR :
+ case MT_OPERAND_BANKADDR :
value = fields->f_bankaddr;
break;
- case MS1_OPERAND_BRC :
+ case MT_OPERAND_BRC :
value = fields->f_brc;
break;
- case MS1_OPERAND_BRC2 :
+ case MT_OPERAND_BRC2 :
value = fields->f_brc2;
break;
- case MS1_OPERAND_CB1INCR :
+ case MT_OPERAND_CB1INCR :
value = fields->f_cb1incr;
break;
- case MS1_OPERAND_CB1SEL :
+ case MT_OPERAND_CB1SEL :
value = fields->f_cb1sel;
break;
- case MS1_OPERAND_CB2INCR :
+ case MT_OPERAND_CB2INCR :
value = fields->f_cb2incr;
break;
- case MS1_OPERAND_CB2SEL :
+ case MT_OPERAND_CB2SEL :
value = fields->f_cb2sel;
break;
- case MS1_OPERAND_CBRB :
+ case MT_OPERAND_CBRB :
value = fields->f_cbrb;
break;
- case MS1_OPERAND_CBS :
+ case MT_OPERAND_CBS :
value = fields->f_cbs;
break;
- case MS1_OPERAND_CBX :
+ case MT_OPERAND_CBX :
value = fields->f_cbx;
break;
- case MS1_OPERAND_CCB :
+ case MT_OPERAND_CCB :
value = fields->f_ccb;
break;
- case MS1_OPERAND_CDB :
+ case MT_OPERAND_CDB :
value = fields->f_cdb;
break;
- case MS1_OPERAND_CELL :
+ case MT_OPERAND_CELL :
value = fields->f_cell;
break;
- case MS1_OPERAND_COLNUM :
+ case MT_OPERAND_COLNUM :
value = fields->f_colnum;
break;
- case MS1_OPERAND_CONTNUM :
+ case MT_OPERAND_CONTNUM :
value = fields->f_contnum;
break;
- case MS1_OPERAND_CR :
+ case MT_OPERAND_CR :
value = fields->f_cr;
break;
- case MS1_OPERAND_CTXDISP :
+ case MT_OPERAND_CTXDISP :
value = fields->f_ctxdisp;
break;
- case MS1_OPERAND_DUP :
+ case MT_OPERAND_DUP :
value = fields->f_dup;
break;
- case MS1_OPERAND_FBDISP :
+ case MT_OPERAND_FBDISP :
value = fields->f_fbdisp;
break;
- case MS1_OPERAND_FBINCR :
+ case MT_OPERAND_FBINCR :
value = fields->f_fbincr;
break;
- case MS1_OPERAND_FRDR :
+ case MT_OPERAND_FRDR :
value = fields->f_dr;
break;
- case MS1_OPERAND_FRDRRR :
+ case MT_OPERAND_FRDRRR :
value = fields->f_drrr;
break;
- case MS1_OPERAND_FRSR1 :
+ case MT_OPERAND_FRSR1 :
value = fields->f_sr1;
break;
- case MS1_OPERAND_FRSR2 :
+ case MT_OPERAND_FRSR2 :
value = fields->f_sr2;
break;
- case MS1_OPERAND_ID :
+ case MT_OPERAND_ID :
value = fields->f_id;
break;
- case MS1_OPERAND_IMM16 :
+ case MT_OPERAND_IMM16 :
value = fields->f_imm16s;
break;
- case MS1_OPERAND_IMM16L :
+ case MT_OPERAND_IMM16L :
value = fields->f_imm16l;
break;
- case MS1_OPERAND_IMM16O :
+ case MT_OPERAND_IMM16O :
value = fields->f_imm16s;
break;
- case MS1_OPERAND_IMM16Z :
+ case MT_OPERAND_IMM16Z :
value = fields->f_imm16u;
break;
- case MS1_OPERAND_INCAMT :
+ case MT_OPERAND_INCAMT :
value = fields->f_incamt;
break;
- case MS1_OPERAND_INCR :
+ case MT_OPERAND_INCR :
value = fields->f_incr;
break;
- case MS1_OPERAND_LENGTH :
+ case MT_OPERAND_LENGTH :
value = fields->f_length;
break;
- case MS1_OPERAND_LOOPSIZE :
+ case MT_OPERAND_LOOPSIZE :
value = fields->f_loopo;
break;
- case MS1_OPERAND_MASK :
+ case MT_OPERAND_MASK :
value = fields->f_mask;
break;
- case MS1_OPERAND_MASK1 :
+ case MT_OPERAND_MASK1 :
value = fields->f_mask1;
break;
- case MS1_OPERAND_MODE :
+ case MT_OPERAND_MODE :
value = fields->f_mode;
break;
- case MS1_OPERAND_PERM :
+ case MT_OPERAND_PERM :
value = fields->f_perm;
break;
- case MS1_OPERAND_RBBC :
+ case MT_OPERAND_RBBC :
value = fields->f_rbbc;
break;
- case MS1_OPERAND_RC :
+ case MT_OPERAND_RC :
value = fields->f_rc;
break;
- case MS1_OPERAND_RC1 :
+ case MT_OPERAND_RC1 :
value = fields->f_rc1;
break;
- case MS1_OPERAND_RC2 :
+ case MT_OPERAND_RC2 :
value = fields->f_rc2;
break;
- case MS1_OPERAND_RC3 :
+ case MT_OPERAND_RC3 :
value = fields->f_rc3;
break;
- case MS1_OPERAND_RCNUM :
+ case MT_OPERAND_RCNUM :
value = fields->f_rcnum;
break;
- case MS1_OPERAND_RDA :
+ case MT_OPERAND_RDA :
value = fields->f_rda;
break;
- case MS1_OPERAND_ROWNUM :
+ case MT_OPERAND_ROWNUM :
value = fields->f_rownum;
break;
- case MS1_OPERAND_ROWNUM1 :
+ case MT_OPERAND_ROWNUM1 :
value = fields->f_rownum1;
break;
- case MS1_OPERAND_ROWNUM2 :
+ case MT_OPERAND_ROWNUM2 :
value = fields->f_rownum2;
break;
- case MS1_OPERAND_SIZE :
+ case MT_OPERAND_SIZE :
value = fields->f_size;
break;
- case MS1_OPERAND_TYPE :
+ case MT_OPERAND_TYPE :
value = fields->f_type;
break;
- case MS1_OPERAND_WR :
+ case MT_OPERAND_WR :
value = fields->f_wr;
break;
- case MS1_OPERAND_XMODE :
+ case MT_OPERAND_XMODE :
value = fields->f_xmode;
break;
return value;
}
-void ms1_cgen_set_int_operand (CGEN_CPU_DESC, int, CGEN_FIELDS *, int);
-void ms1_cgen_set_vma_operand (CGEN_CPU_DESC, int, CGEN_FIELDS *, bfd_vma);
+void mt_cgen_set_int_operand (CGEN_CPU_DESC, int, CGEN_FIELDS *, int);
+void mt_cgen_set_vma_operand (CGEN_CPU_DESC, int, CGEN_FIELDS *, bfd_vma);
/* Stuffing values in cgen_fields is handled by a collection of functions.
They are distinguished by the type of the VALUE argument they accept.
not appropriate. */
void
-ms1_cgen_set_int_operand (CGEN_CPU_DESC cd ATTRIBUTE_UNUSED,
+mt_cgen_set_int_operand (CGEN_CPU_DESC cd ATTRIBUTE_UNUSED,
int opindex,
CGEN_FIELDS * fields,
int value)
{
switch (opindex)
{
- case MS1_OPERAND_A23 :
+ case MT_OPERAND_A23 :
fields->f_a23 = value;
break;
- case MS1_OPERAND_BALL :
+ case MT_OPERAND_BALL :
fields->f_ball = value;
break;
- case MS1_OPERAND_BALL2 :
+ case MT_OPERAND_BALL2 :
fields->f_ball2 = value;
break;
- case MS1_OPERAND_BANKADDR :
+ case MT_OPERAND_BANKADDR :
fields->f_bankaddr = value;
break;
- case MS1_OPERAND_BRC :
+ case MT_OPERAND_BRC :
fields->f_brc = value;
break;
- case MS1_OPERAND_BRC2 :
+ case MT_OPERAND_BRC2 :
fields->f_brc2 = value;
break;
- case MS1_OPERAND_CB1INCR :
+ case MT_OPERAND_CB1INCR :
fields->f_cb1incr = value;
break;
- case MS1_OPERAND_CB1SEL :
+ case MT_OPERAND_CB1SEL :
fields->f_cb1sel = value;
break;
- case MS1_OPERAND_CB2INCR :
+ case MT_OPERAND_CB2INCR :
fields->f_cb2incr = value;
break;
- case MS1_OPERAND_CB2SEL :
+ case MT_OPERAND_CB2SEL :
fields->f_cb2sel = value;
break;
- case MS1_OPERAND_CBRB :
+ case MT_OPERAND_CBRB :
fields->f_cbrb = value;
break;
- case MS1_OPERAND_CBS :
+ case MT_OPERAND_CBS :
fields->f_cbs = value;
break;
- case MS1_OPERAND_CBX :
+ case MT_OPERAND_CBX :
fields->f_cbx = value;
break;
- case MS1_OPERAND_CCB :
+ case MT_OPERAND_CCB :
fields->f_ccb = value;
break;
- case MS1_OPERAND_CDB :
+ case MT_OPERAND_CDB :
fields->f_cdb = value;
break;
- case MS1_OPERAND_CELL :
+ case MT_OPERAND_CELL :
fields->f_cell = value;
break;
- case MS1_OPERAND_COLNUM :
+ case MT_OPERAND_COLNUM :
fields->f_colnum = value;
break;
- case MS1_OPERAND_CONTNUM :
+ case MT_OPERAND_CONTNUM :
fields->f_contnum = value;
break;
- case MS1_OPERAND_CR :
+ case MT_OPERAND_CR :
fields->f_cr = value;
break;
- case MS1_OPERAND_CTXDISP :
+ case MT_OPERAND_CTXDISP :
fields->f_ctxdisp = value;
break;
- case MS1_OPERAND_DUP :
+ case MT_OPERAND_DUP :
fields->f_dup = value;
break;
- case MS1_OPERAND_FBDISP :
+ case MT_OPERAND_FBDISP :
fields->f_fbdisp = value;
break;
- case MS1_OPERAND_FBINCR :
+ case MT_OPERAND_FBINCR :
fields->f_fbincr = value;
break;
- case MS1_OPERAND_FRDR :
+ case MT_OPERAND_FRDR :
fields->f_dr = value;
break;
- case MS1_OPERAND_FRDRRR :
+ case MT_OPERAND_FRDRRR :
fields->f_drrr = value;
break;
- case MS1_OPERAND_FRSR1 :
+ case MT_OPERAND_FRSR1 :
fields->f_sr1 = value;
break;
- case MS1_OPERAND_FRSR2 :
+ case MT_OPERAND_FRSR2 :
fields->f_sr2 = value;
break;
- case MS1_OPERAND_ID :
+ case MT_OPERAND_ID :
fields->f_id = value;
break;
- case MS1_OPERAND_IMM16 :
+ case MT_OPERAND_IMM16 :
fields->f_imm16s = value;
break;
- case MS1_OPERAND_IMM16L :
+ case MT_OPERAND_IMM16L :
fields->f_imm16l = value;
break;
- case MS1_OPERAND_IMM16O :
+ case MT_OPERAND_IMM16O :
fields->f_imm16s = value;
break;
- case MS1_OPERAND_IMM16Z :
+ case MT_OPERAND_IMM16Z :
fields->f_imm16u = value;
break;
- case MS1_OPERAND_INCAMT :
+ case MT_OPERAND_INCAMT :
fields->f_incamt = value;
break;
- case MS1_OPERAND_INCR :
+ case MT_OPERAND_INCR :
fields->f_incr = value;
break;
- case MS1_OPERAND_LENGTH :
+ case MT_OPERAND_LENGTH :
fields->f_length = value;
break;
- case MS1_OPERAND_LOOPSIZE :
+ case MT_OPERAND_LOOPSIZE :
fields->f_loopo = value;
break;
- case MS1_OPERAND_MASK :
+ case MT_OPERAND_MASK :
fields->f_mask = value;
break;
- case MS1_OPERAND_MASK1 :
+ case MT_OPERAND_MASK1 :
fields->f_mask1 = value;
break;
- case MS1_OPERAND_MODE :
+ case MT_OPERAND_MODE :
fields->f_mode = value;
break;
- case MS1_OPERAND_PERM :
+ case MT_OPERAND_PERM :
fields->f_perm = value;
break;
- case MS1_OPERAND_RBBC :
+ case MT_OPERAND_RBBC :
fields->f_rbbc = value;
break;
- case MS1_OPERAND_RC :
+ case MT_OPERAND_RC :
fields->f_rc = value;
break;
- case MS1_OPERAND_RC1 :
+ case MT_OPERAND_RC1 :
fields->f_rc1 = value;
break;
- case MS1_OPERAND_RC2 :
+ case MT_OPERAND_RC2 :
fields->f_rc2 = value;
break;
- case MS1_OPERAND_RC3 :
+ case MT_OPERAND_RC3 :
fields->f_rc3 = value;
break;
- case MS1_OPERAND_RCNUM :
+ case MT_OPERAND_RCNUM :
fields->f_rcnum = value;
break;
- case MS1_OPERAND_RDA :
+ case MT_OPERAND_RDA :
fields->f_rda = value;
break;
- case MS1_OPERAND_ROWNUM :
+ case MT_OPERAND_ROWNUM :
fields->f_rownum = value;
break;
- case MS1_OPERAND_ROWNUM1 :
+ case MT_OPERAND_ROWNUM1 :
fields->f_rownum1 = value;
break;
- case MS1_OPERAND_ROWNUM2 :
+ case MT_OPERAND_ROWNUM2 :
fields->f_rownum2 = value;
break;
- case MS1_OPERAND_SIZE :
+ case MT_OPERAND_SIZE :
fields->f_size = value;
break;
- case MS1_OPERAND_TYPE :
+ case MT_OPERAND_TYPE :
fields->f_type = value;
break;
- case MS1_OPERAND_WR :
+ case MT_OPERAND_WR :
fields->f_wr = value;
break;
- case MS1_OPERAND_XMODE :
+ case MT_OPERAND_XMODE :
fields->f_xmode = value;
break;
}
void
-ms1_cgen_set_vma_operand (CGEN_CPU_DESC cd ATTRIBUTE_UNUSED,
+mt_cgen_set_vma_operand (CGEN_CPU_DESC cd ATTRIBUTE_UNUSED,
int opindex,
CGEN_FIELDS * fields,
bfd_vma value)
{
switch (opindex)
{
- case MS1_OPERAND_A23 :
+ case MT_OPERAND_A23 :
fields->f_a23 = value;
break;
- case MS1_OPERAND_BALL :
+ case MT_OPERAND_BALL :
fields->f_ball = value;
break;
- case MS1_OPERAND_BALL2 :
+ case MT_OPERAND_BALL2 :
fields->f_ball2 = value;
break;
- case MS1_OPERAND_BANKADDR :
+ case MT_OPERAND_BANKADDR :
fields->f_bankaddr = value;
break;
- case MS1_OPERAND_BRC :
+ case MT_OPERAND_BRC :
fields->f_brc = value;
break;
- case MS1_OPERAND_BRC2 :
+ case MT_OPERAND_BRC2 :
fields->f_brc2 = value;
break;
- case MS1_OPERAND_CB1INCR :
+ case MT_OPERAND_CB1INCR :
fields->f_cb1incr = value;
break;
- case MS1_OPERAND_CB1SEL :
+ case MT_OPERAND_CB1SEL :
fields->f_cb1sel = value;
break;
- case MS1_OPERAND_CB2INCR :
+ case MT_OPERAND_CB2INCR :
fields->f_cb2incr = value;
break;
- case MS1_OPERAND_CB2SEL :
+ case MT_OPERAND_CB2SEL :
fields->f_cb2sel = value;
break;
- case MS1_OPERAND_CBRB :
+ case MT_OPERAND_CBRB :
fields->f_cbrb = value;
break;
- case MS1_OPERAND_CBS :
+ case MT_OPERAND_CBS :
fields->f_cbs = value;
break;
- case MS1_OPERAND_CBX :
+ case MT_OPERAND_CBX :
fields->f_cbx = value;
break;
- case MS1_OPERAND_CCB :
+ case MT_OPERAND_CCB :
fields->f_ccb = value;
break;
- case MS1_OPERAND_CDB :
+ case MT_OPERAND_CDB :
fields->f_cdb = value;
break;
- case MS1_OPERAND_CELL :
+ case MT_OPERAND_CELL :
fields->f_cell = value;
break;
- case MS1_OPERAND_COLNUM :
+ case MT_OPERAND_COLNUM :
fields->f_colnum = value;
break;
- case MS1_OPERAND_CONTNUM :
+ case MT_OPERAND_CONTNUM :
fields->f_contnum = value;
break;
- case MS1_OPERAND_CR :
+ case MT_OPERAND_CR :
fields->f_cr = value;
break;
- case MS1_OPERAND_CTXDISP :
+ case MT_OPERAND_CTXDISP :
fields->f_ctxdisp = value;
break;
- case MS1_OPERAND_DUP :
+ case MT_OPERAND_DUP :
fields->f_dup = value;
break;
- case MS1_OPERAND_FBDISP :
+ case MT_OPERAND_FBDISP :
fields->f_fbdisp = value;
break;
- case MS1_OPERAND_FBINCR :
+ case MT_OPERAND_FBINCR :
fields->f_fbincr = value;
break;
- case MS1_OPERAND_FRDR :
+ case MT_OPERAND_FRDR :
fields->f_dr = value;
break;
- case MS1_OPERAND_FRDRRR :
+ case MT_OPERAND_FRDRRR :
fields->f_drrr = value;
break;
- case MS1_OPERAND_FRSR1 :
+ case MT_OPERAND_FRSR1 :
fields->f_sr1 = value;
break;
- case MS1_OPERAND_FRSR2 :
+ case MT_OPERAND_FRSR2 :
fields->f_sr2 = value;
break;
- case MS1_OPERAND_ID :
+ case MT_OPERAND_ID :
fields->f_id = value;
break;
- case MS1_OPERAND_IMM16 :
+ case MT_OPERAND_IMM16 :
fields->f_imm16s = value;
break;
- case MS1_OPERAND_IMM16L :
+ case MT_OPERAND_IMM16L :
fields->f_imm16l = value;
break;
- case MS1_OPERAND_IMM16O :
+ case MT_OPERAND_IMM16O :
fields->f_imm16s = value;
break;
- case MS1_OPERAND_IMM16Z :
+ case MT_OPERAND_IMM16Z :
fields->f_imm16u = value;
break;
- case MS1_OPERAND_INCAMT :
+ case MT_OPERAND_INCAMT :
fields->f_incamt = value;
break;
- case MS1_OPERAND_INCR :
+ case MT_OPERAND_INCR :
fields->f_incr = value;
break;
- case MS1_OPERAND_LENGTH :
+ case MT_OPERAND_LENGTH :
fields->f_length = value;
break;
- case MS1_OPERAND_LOOPSIZE :
+ case MT_OPERAND_LOOPSIZE :
fields->f_loopo = value;
break;
- case MS1_OPERAND_MASK :
+ case MT_OPERAND_MASK :
fields->f_mask = value;
break;
- case MS1_OPERAND_MASK1 :
+ case MT_OPERAND_MASK1 :
fields->f_mask1 = value;
break;
- case MS1_OPERAND_MODE :
+ case MT_OPERAND_MODE :
fields->f_mode = value;
break;
- case MS1_OPERAND_PERM :
+ case MT_OPERAND_PERM :
fields->f_perm = value;
break;
- case MS1_OPERAND_RBBC :
+ case MT_OPERAND_RBBC :
fields->f_rbbc = value;
break;
- case MS1_OPERAND_RC :
+ case MT_OPERAND_RC :
fields->f_rc = value;
break;
- case MS1_OPERAND_RC1 :
+ case MT_OPERAND_RC1 :
fields->f_rc1 = value;
break;
- case MS1_OPERAND_RC2 :
+ case MT_OPERAND_RC2 :
fields->f_rc2 = value;
break;
- case MS1_OPERAND_RC3 :
+ case MT_OPERAND_RC3 :
fields->f_rc3 = value;
break;
- case MS1_OPERAND_RCNUM :
+ case MT_OPERAND_RCNUM :
fields->f_rcnum = value;
break;
- case MS1_OPERAND_RDA :
+ case MT_OPERAND_RDA :
fields->f_rda = value;
break;
- case MS1_OPERAND_ROWNUM :
+ case MT_OPERAND_ROWNUM :
fields->f_rownum = value;
break;
- case MS1_OPERAND_ROWNUM1 :
+ case MT_OPERAND_ROWNUM1 :
fields->f_rownum1 = value;
break;
- case MS1_OPERAND_ROWNUM2 :
+ case MT_OPERAND_ROWNUM2 :
fields->f_rownum2 = value;
break;
- case MS1_OPERAND_SIZE :
+ case MT_OPERAND_SIZE :
fields->f_size = value;
break;
- case MS1_OPERAND_TYPE :
+ case MT_OPERAND_TYPE :
fields->f_type = value;
break;
- case MS1_OPERAND_WR :
+ case MT_OPERAND_WR :
fields->f_wr = value;
break;
- case MS1_OPERAND_XMODE :
+ case MT_OPERAND_XMODE :
fields->f_xmode = value;
break;
/* Function to call before using the instruction builder tables. */
void
-ms1_cgen_init_ibld_table (CGEN_CPU_DESC cd)
+mt_cgen_init_ibld_table (CGEN_CPU_DESC cd)
{
- cd->insert_handlers = & ms1_cgen_insert_handlers[0];
- cd->extract_handlers = & ms1_cgen_extract_handlers[0];
+ cd->insert_handlers = & mt_cgen_insert_handlers[0];
+ cd->extract_handlers = & mt_cgen_extract_handlers[0];
- cd->insert_operand = ms1_cgen_insert_operand;
- cd->extract_operand = ms1_cgen_extract_operand;
+ cd->insert_operand = mt_cgen_insert_operand;
+ cd->extract_operand = mt_cgen_extract_operand;
- cd->get_int_operand = ms1_cgen_get_int_operand;
- cd->set_int_operand = ms1_cgen_set_int_operand;
- cd->get_vma_operand = ms1_cgen_get_vma_operand;
- cd->set_vma_operand = ms1_cgen_set_vma_operand;
+ cd->get_int_operand = mt_cgen_get_int_operand;
+ cd->set_int_operand = mt_cgen_set_int_operand;
+ cd->get_vma_operand = mt_cgen_get_vma_operand;
+ cd->set_vma_operand = mt_cgen_set_vma_operand;
}
-/* Instruction opcode table for ms1.
+/* Instruction opcode table for mt.
THIS FILE IS MACHINE GENERATED WITH CGEN.
#include "ansidecl.h"
#include "bfd.h"
#include "symcat.h"
-#include "ms1-desc.h"
-#include "ms1-opc.h"
+#include "mt-desc.h"
+#include "mt-opc.h"
#include "libiberty.h"
/* -- opc.c */
/* Special check to ensure that instruction exists for given machine. */
int
-ms1_cgen_insn_supported (CGEN_CPU_DESC cd,
- const CGEN_INSN *insn)
+mt_cgen_insn_supported (CGEN_CPU_DESC cd,
+ const CGEN_INSN *insn)
{
int machs = CGEN_INSN_ATTR_VALUE (insn, CGEN_INSN_MACH);
/* A better hash function for instruction mnemonics. */
unsigned int
-ms1_asm_hash (const char* insn)
+mt_asm_hash (const char* insn)
{
unsigned int hash;
const char* m = insn;
/* Instruction formats. */
#if defined (__STDC__) || defined (ALMOST_STDC) || defined (HAVE_STRINGIZE)
-#define F(f) & ms1_cgen_ifld_table[MS1_##f]
+#define F(f) & mt_cgen_ifld_table[MT_##f]
#else
-#define F(f) & ms1_cgen_ifld_table[MS1_/**/f]
+#define F(f) & mt_cgen_ifld_table[MT_/**/f]
#endif
static const CGEN_IFMT ifmt_empty ATTRIBUTE_UNUSED = {
0, 0, 0x0, { { 0 } }
#define A(a) (1 << CGEN_INSN_/**/a)
#endif
#if defined (__STDC__) || defined (ALMOST_STDC) || defined (HAVE_STRINGIZE)
-#define OPERAND(op) MS1_OPERAND_##op
+#define OPERAND(op) MT_OPERAND_##op
#else
-#define OPERAND(op) MS1_OPERAND_/**/op
+#define OPERAND(op) MT_OPERAND_/**/op
#endif
#define MNEM CGEN_SYNTAX_MNEMONIC /* syntax value for mnemonic */
#define OP(field) CGEN_SYNTAX_MAKE_FIELD (OPERAND (field))
/* The instruction table. */
-static const CGEN_OPCODE ms1_cgen_insn_opcode_table[MAX_INSNS] =
+static const CGEN_OPCODE mt_cgen_insn_opcode_table[MAX_INSNS] =
{
/* Special null first entry.
A `num' value of zero is thus invalid.
/* Formats for ALIAS macro-insns. */
#if defined (__STDC__) || defined (ALMOST_STDC) || defined (HAVE_STRINGIZE)
-#define F(f) & ms1_cgen_ifld_table[MS1_##f]
+#define F(f) & mt_cgen_ifld_table[MT_##f]
#else
-#define F(f) & ms1_cgen_ifld_table[MS1_/**/f]
+#define F(f) & mt_cgen_ifld_table[MT_/**/f]
#endif
#undef F
#define A(a) (1 << CGEN_INSN_/**/a)
#endif
#if defined (__STDC__) || defined (ALMOST_STDC) || defined (HAVE_STRINGIZE)
-#define OPERAND(op) MS1_OPERAND_##op
+#define OPERAND(op) MT_OPERAND_##op
#else
-#define OPERAND(op) MS1_OPERAND_/**/op
+#define OPERAND(op) MT_OPERAND_/**/op
#endif
#define MNEM CGEN_SYNTAX_MNEMONIC /* syntax value for mnemonic */
#define OP(field) CGEN_SYNTAX_MAKE_FIELD (OPERAND (field))
/* The macro instruction table. */
-static const CGEN_IBASE ms1_cgen_macro_insn_table[] =
+static const CGEN_IBASE mt_cgen_macro_insn_table[] =
{
};
/* The macro instruction opcode table. */
-static const CGEN_OPCODE ms1_cgen_macro_insn_opcode_table[] =
+static const CGEN_OPCODE mt_cgen_macro_insn_opcode_table[] =
{
};
This plugs the opcode entries and macro instructions into the cpu table. */
void
-ms1_cgen_init_opcode_table (CGEN_CPU_DESC cd)
+mt_cgen_init_opcode_table (CGEN_CPU_DESC cd)
{
int i;
- int num_macros = (sizeof (ms1_cgen_macro_insn_table) /
- sizeof (ms1_cgen_macro_insn_table[0]));
- const CGEN_IBASE *ib = & ms1_cgen_macro_insn_table[0];
- const CGEN_OPCODE *oc = & ms1_cgen_macro_insn_opcode_table[0];
+ int num_macros = (sizeof (mt_cgen_macro_insn_table) /
+ sizeof (mt_cgen_macro_insn_table[0]));
+ const CGEN_IBASE *ib = & mt_cgen_macro_insn_table[0];
+ const CGEN_OPCODE *oc = & mt_cgen_macro_insn_opcode_table[0];
CGEN_INSN *insns = xmalloc (num_macros * sizeof (CGEN_INSN));
memset (insns, 0, num_macros * sizeof (CGEN_INSN));
{
insns[i].base = &ib[i];
insns[i].opcode = &oc[i];
- ms1_cgen_build_insn_regex (& insns[i]);
+ mt_cgen_build_insn_regex (& insns[i]);
}
cd->macro_insn_table.init_entries = insns;
cd->macro_insn_table.entry_size = sizeof (CGEN_IBASE);
cd->macro_insn_table.num_init_entries = num_macros;
- oc = & ms1_cgen_insn_opcode_table[0];
+ oc = & mt_cgen_insn_opcode_table[0];
insns = (CGEN_INSN *) cd->insn_table.init_entries;
for (i = 0; i < MAX_INSNS; ++i)
{
insns[i].opcode = &oc[i];
- ms1_cgen_build_insn_regex (& insns[i]);
+ mt_cgen_build_insn_regex (& insns[i]);
}
cd->sizeof_fields = sizeof (CGEN_FIELDS);
-/* Instruction opcode header for ms1.
+/* Instruction opcode header for mt.
THIS FILE IS MACHINE GENERATED WITH CGEN.
*/
-#ifndef MS1_OPC_H
-#define MS1_OPC_H
+#ifndef MT_OPC_H
+#define MT_OPC_H
/* -- opc.h */
#define CGEN_DIS_HASH(buf, value) (((* (unsigned char *) (buf)) >> 5) % CGEN_DIS_HASH_SIZE)
#define CGEN_ASM_HASH_SIZE 127
-#define CGEN_ASM_HASH(insn) ms1_asm_hash (insn)
+#define CGEN_ASM_HASH(insn) mt_asm_hash (insn)
-extern unsigned int ms1_asm_hash (const char *);
+extern unsigned int mt_asm_hash (const char *);
-extern int ms1_cgen_insn_supported (CGEN_CPU_DESC, const CGEN_INSN *);
+extern int mt_cgen_insn_supported (CGEN_CPU_DESC, const CGEN_INSN *);
\f
/* -- opc.c */
-/* Enum declaration for ms1 instruction types. */
+/* Enum declaration for mt instruction types. */
typedef enum cgen_insn_type {
- MS1_INSN_INVALID, MS1_INSN_ADD, MS1_INSN_ADDU, MS1_INSN_ADDI
- , MS1_INSN_ADDUI, MS1_INSN_SUB, MS1_INSN_SUBU, MS1_INSN_SUBI
- , MS1_INSN_SUBUI, MS1_INSN_MUL, MS1_INSN_MULI, MS1_INSN_AND
- , MS1_INSN_ANDI, MS1_INSN_OR, MS1_INSN_NOP, MS1_INSN_ORI
- , MS1_INSN_XOR, MS1_INSN_XORI, MS1_INSN_NAND, MS1_INSN_NANDI
- , MS1_INSN_NOR, MS1_INSN_NORI, MS1_INSN_XNOR, MS1_INSN_XNORI
- , MS1_INSN_LDUI, MS1_INSN_LSL, MS1_INSN_LSLI, MS1_INSN_LSR
- , MS1_INSN_LSRI, MS1_INSN_ASR, MS1_INSN_ASRI, MS1_INSN_BRLT
- , MS1_INSN_BRLE, MS1_INSN_BREQ, MS1_INSN_BRNE, MS1_INSN_JMP
- , MS1_INSN_JAL, MS1_INSN_DBNZ, MS1_INSN_EI, MS1_INSN_DI
- , MS1_INSN_SI, MS1_INSN_RETI, MS1_INSN_LDW, MS1_INSN_STW
- , MS1_INSN_BREAK, MS1_INSN_IFLUSH, MS1_INSN_LDCTXT, MS1_INSN_LDFB
- , MS1_INSN_STFB, MS1_INSN_FBCB, MS1_INSN_MFBCB, MS1_INSN_FBCCI
- , MS1_INSN_FBRCI, MS1_INSN_FBCRI, MS1_INSN_FBRRI, MS1_INSN_MFBCCI
- , MS1_INSN_MFBRCI, MS1_INSN_MFBCRI, MS1_INSN_MFBRRI, MS1_INSN_FBCBDR
- , MS1_INSN_RCFBCB, MS1_INSN_MRCFBCB, MS1_INSN_CBCAST, MS1_INSN_DUPCBCAST
- , MS1_INSN_WFBI, MS1_INSN_WFB, MS1_INSN_RCRISC, MS1_INSN_FBCBINC
- , MS1_INSN_RCXMODE, MS1_INSN_INTERLEAVER, MS1_INSN_WFBINC, MS1_INSN_MWFBINC
- , MS1_INSN_WFBINCR, MS1_INSN_MWFBINCR, MS1_INSN_FBCBINCS, MS1_INSN_MFBCBINCS
- , MS1_INSN_FBCBINCRS, MS1_INSN_MFBCBINCRS, MS1_INSN_LOOP, MS1_INSN_LOOPI
- , MS1_INSN_DFBC, MS1_INSN_DWFB, MS1_INSN_FBWFB, MS1_INSN_DFBR
+ MT_INSN_INVALID, MT_INSN_ADD, MT_INSN_ADDU, MT_INSN_ADDI
+ , MT_INSN_ADDUI, MT_INSN_SUB, MT_INSN_SUBU, MT_INSN_SUBI
+ , MT_INSN_SUBUI, MT_INSN_MUL, MT_INSN_MULI, MT_INSN_AND
+ , MT_INSN_ANDI, MT_INSN_OR, MT_INSN_NOP, MT_INSN_ORI
+ , MT_INSN_XOR, MT_INSN_XORI, MT_INSN_NAND, MT_INSN_NANDI
+ , MT_INSN_NOR, MT_INSN_NORI, MT_INSN_XNOR, MT_INSN_XNORI
+ , MT_INSN_LDUI, MT_INSN_LSL, MT_INSN_LSLI, MT_INSN_LSR
+ , MT_INSN_LSRI, MT_INSN_ASR, MT_INSN_ASRI, MT_INSN_BRLT
+ , MT_INSN_BRLE, MT_INSN_BREQ, MT_INSN_BRNE, MT_INSN_JMP
+ , MT_INSN_JAL, MT_INSN_DBNZ, MT_INSN_EI, MT_INSN_DI
+ , MT_INSN_SI, MT_INSN_RETI, MT_INSN_LDW, MT_INSN_STW
+ , MT_INSN_BREAK, MT_INSN_IFLUSH, MT_INSN_LDCTXT, MT_INSN_LDFB
+ , MT_INSN_STFB, MT_INSN_FBCB, MT_INSN_MFBCB, MT_INSN_FBCCI
+ , MT_INSN_FBRCI, MT_INSN_FBCRI, MT_INSN_FBRRI, MT_INSN_MFBCCI
+ , MT_INSN_MFBRCI, MT_INSN_MFBCRI, MT_INSN_MFBRRI, MT_INSN_FBCBDR
+ , MT_INSN_RCFBCB, MT_INSN_MRCFBCB, MT_INSN_CBCAST, MT_INSN_DUPCBCAST
+ , MT_INSN_WFBI, MT_INSN_WFB, MT_INSN_RCRISC, MT_INSN_FBCBINC
+ , MT_INSN_RCXMODE, MT_INSN_INTERLEAVER, MT_INSN_WFBINC, MT_INSN_MWFBINC
+ , MT_INSN_WFBINCR, MT_INSN_MWFBINCR, MT_INSN_FBCBINCS, MT_INSN_MFBCBINCS
+ , MT_INSN_FBCBINCRS, MT_INSN_MFBCBINCRS, MT_INSN_LOOP, MT_INSN_LOOPI
+ , MT_INSN_DFBC, MT_INSN_DWFB, MT_INSN_FBWFB, MT_INSN_DFBR
} CGEN_INSN_TYPE;
/* Index of `invalid' insn place holder. */
-#define CGEN_INSN_INVALID MS1_INSN_INVALID
+#define CGEN_INSN_INVALID MT_INSN_INVALID
/* Total number of insns in table. */
-#define MAX_INSNS ((int) MS1_INSN_DFBR + 1)
+#define MAX_INSNS ((int) MT_INSN_DFBR + 1)
/* This struct records data prior to insertion or after extraction. */
struct cgen_fields
}
-#endif /* MS1_OPC_H */
+#endif /* MT_OPC_H */
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