[RISCV] Add M extension command lines to ctlz-cttz-ctpop.ll. NFC

ctpop and cttz default expansion both end up using a multiply. This
can either use a mul instruction or libcall. Make sure we test both
cases.

diff --git a/llvm/test/CodeGen/RISCV/ctlz-cttz-ctpop.ll b/llvm/test/CodeGen/RISCV/ctlz-cttz-ctpop.ll
index 1a97267..d58505d 100644 (file)
--- a/llvm/test/CodeGen/RISCV/ctlz-cttz-ctpop.ll
+++ b/llvm/test/CodeGen/RISCV/ctlz-cttz-ctpop.ll
@@ -1,8 +1,12 @@
 ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
 ; RUN: llc -mtriple=riscv32 -verify-machineinstrs < %s \
-; RUN:   | FileCheck %s -check-prefix=RV32I
+; RUN:   | FileCheck %s -check-prefixes=RV32_NOZBB,RV32I
 ; RUN: llc -mtriple=riscv64 -verify-machineinstrs < %s \
-; RUN:   | FileCheck %s -check-prefix=RV64I
+; RUN:   | FileCheck %s -check-prefixes=RV64NOZBB,RV64I
+; RUN: llc -mtriple=riscv32 -mattr=+m -verify-machineinstrs < %s \
+; RUN:   | FileCheck %s -check-prefixes=RV32_NOZBB,RV32M
+; RUN: llc -mtriple=riscv64 -mattr=+m -verify-machineinstrs < %s \
+; RUN:   | FileCheck %s -check-prefixes=RV64NOZBB,RV64M
 ; RUN: llc -mtriple=riscv32 -mattr=+zbb -verify-machineinstrs < %s \
 ; RUN:   | FileCheck %s -check-prefix=RV32ZBB
 ; RUN: llc -mtriple=riscv64 -mattr=+zbb -verify-machineinstrs < %s \
@@ -22,51 +26,51 @@ declare i32 @llvm.ctpop.i32(i32)
 declare i64 @llvm.ctpop.i64(i64)
 
 define i8 @test_cttz_i8(i8 %a) nounwind {
-; RV32I-LABEL: test_cttz_i8:
-; RV32I:       # %bb.0:
-; RV32I-NEXT:    andi a1, a0, 255
-; RV32I-NEXT:    beqz a1, .LBB0_2
-; RV32I-NEXT:  # %bb.1: # %cond.false
-; RV32I-NEXT:    addi a1, a0, -1
-; RV32I-NEXT:    not a0, a0
-; RV32I-NEXT:    and a0, a0, a1
-; RV32I-NEXT:    srli a1, a0, 1
-; RV32I-NEXT:    andi a1, a1, 85
-; RV32I-NEXT:    sub a0, a0, a1
-; RV32I-NEXT:    andi a1, a0, 51
-; RV32I-NEXT:    srli a0, a0, 2
-; RV32I-NEXT:    andi a0, a0, 51
-; RV32I-NEXT:    add a0, a1, a0
-; RV32I-NEXT:    srli a1, a0, 4
-; RV32I-NEXT:    add a0, a0, a1
-; RV32I-NEXT:    andi a0, a0, 15
-; RV32I-NEXT:    ret
-; RV32I-NEXT:  .LBB0_2:
-; RV32I-NEXT:    li a0, 8
-; RV32I-NEXT:    ret
-;
-; RV64I-LABEL: test_cttz_i8:
-; RV64I:       # %bb.0:
-; RV64I-NEXT:    andi a1, a0, 255
-; RV64I-NEXT:    beqz a1, .LBB0_2
-; RV64I-NEXT:  # %bb.1: # %cond.false
-; RV64I-NEXT:    addi a1, a0, -1
-; RV64I-NEXT:    not a0, a0
-; RV64I-NEXT:    and a0, a0, a1
-; RV64I-NEXT:    srli a1, a0, 1
-; RV64I-NEXT:    andi a1, a1, 85
-; RV64I-NEXT:    sub a0, a0, a1
-; RV64I-NEXT:    andi a1, a0, 51
-; RV64I-NEXT:    srli a0, a0, 2
-; RV64I-NEXT:    andi a0, a0, 51
-; RV64I-NEXT:    add a0, a1, a0
-; RV64I-NEXT:    srli a1, a0, 4
-; RV64I-NEXT:    addw a0, a0, a1
-; RV64I-NEXT:    andi a0, a0, 15
-; RV64I-NEXT:    ret
-; RV64I-NEXT:  .LBB0_2:
-; RV64I-NEXT:    li a0, 8
-; RV64I-NEXT:    ret
+; RV32_NOZBB-LABEL: test_cttz_i8:
+; RV32_NOZBB:       # %bb.0:
+; RV32_NOZBB-NEXT:    andi a1, a0, 255
+; RV32_NOZBB-NEXT:    beqz a1, .LBB0_2
+; RV32_NOZBB-NEXT:  # %bb.1: # %cond.false
+; RV32_NOZBB-NEXT:    addi a1, a0, -1
+; RV32_NOZBB-NEXT:    not a0, a0
+; RV32_NOZBB-NEXT:    and a0, a0, a1
+; RV32_NOZBB-NEXT:    srli a1, a0, 1
+; RV32_NOZBB-NEXT:    andi a1, a1, 85
+; RV32_NOZBB-NEXT:    sub a0, a0, a1
+; RV32_NOZBB-NEXT:    andi a1, a0, 51
+; RV32_NOZBB-NEXT:    srli a0, a0, 2
+; RV32_NOZBB-NEXT:    andi a0, a0, 51
+; RV32_NOZBB-NEXT:    add a0, a1, a0
+; RV32_NOZBB-NEXT:    srli a1, a0, 4
+; RV32_NOZBB-NEXT:    add a0, a0, a1
+; RV32_NOZBB-NEXT:    andi a0, a0, 15
+; RV32_NOZBB-NEXT:    ret
+; RV32_NOZBB-NEXT:  .LBB0_2:
+; RV32_NOZBB-NEXT:    li a0, 8
+; RV32_NOZBB-NEXT:    ret
+;
+; RV64NOZBB-LABEL: test_cttz_i8:
+; RV64NOZBB:       # %bb.0:
+; RV64NOZBB-NEXT:    andi a1, a0, 255
+; RV64NOZBB-NEXT:    beqz a1, .LBB0_2
+; RV64NOZBB-NEXT:  # %bb.1: # %cond.false
+; RV64NOZBB-NEXT:    addi a1, a0, -1
+; RV64NOZBB-NEXT:    not a0, a0
+; RV64NOZBB-NEXT:    and a0, a0, a1
+; RV64NOZBB-NEXT:    srli a1, a0, 1
+; RV64NOZBB-NEXT:    andi a1, a1, 85
+; RV64NOZBB-NEXT:    sub a0, a0, a1
+; RV64NOZBB-NEXT:    andi a1, a0, 51
+; RV64NOZBB-NEXT:    srli a0, a0, 2
+; RV64NOZBB-NEXT:    andi a0, a0, 51
+; RV64NOZBB-NEXT:    add a0, a1, a0
+; RV64NOZBB-NEXT:    srli a1, a0, 4
+; RV64NOZBB-NEXT:    addw a0, a0, a1
+; RV64NOZBB-NEXT:    andi a0, a0, 15
+; RV64NOZBB-NEXT:    ret
+; RV64NOZBB-NEXT:  .LBB0_2:
+; RV64NOZBB-NEXT:    li a0, 8
+; RV64NOZBB-NEXT:    ret
 ;
 ; RV32ZBB-LABEL: test_cttz_i8:
 ; RV32ZBB:       # %bb.0:
@@ -84,73 +88,73 @@ define i8 @test_cttz_i8(i8 %a) nounwind {
 }
 
 define i16 @test_cttz_i16(i16 %a) nounwind {
-; RV32I-LABEL: test_cttz_i16:
-; RV32I:       # %bb.0:
-; RV32I-NEXT:    slli a1, a0, 16
-; RV32I-NEXT:    srli a1, a1, 16
-; RV32I-NEXT:    beqz a1, .LBB1_2
-; RV32I-NEXT:  # %bb.1: # %cond.false
-; RV32I-NEXT:    addi a1, a0, -1
-; RV32I-NEXT:    not a0, a0
-; RV32I-NEXT:    and a0, a0, a1
-; RV32I-NEXT:    srli a1, a0, 1
-; RV32I-NEXT:    lui a2, 5
-; RV32I-NEXT:    addi a2, a2, 1365
-; RV32I-NEXT:    and a1, a1, a2
-; RV32I-NEXT:    sub a0, a0, a1
-; RV32I-NEXT:    lui a1, 3
-; RV32I-NEXT:    addi a1, a1, 819
-; RV32I-NEXT:    and a2, a0, a1
-; RV32I-NEXT:    srli a0, a0, 2
-; RV32I-NEXT:    and a0, a0, a1
-; RV32I-NEXT:    add a0, a2, a0
-; RV32I-NEXT:    srli a1, a0, 4
-; RV32I-NEXT:    add a0, a0, a1
-; RV32I-NEXT:    lui a1, 1
-; RV32I-NEXT:    addi a1, a1, -241
-; RV32I-NEXT:    and a0, a0, a1
-; RV32I-NEXT:    slli a1, a0, 8
-; RV32I-NEXT:    add a0, a1, a0
-; RV32I-NEXT:    slli a0, a0, 19
-; RV32I-NEXT:    srli a0, a0, 27
-; RV32I-NEXT:    ret
-; RV32I-NEXT:  .LBB1_2:
-; RV32I-NEXT:    li a0, 16
-; RV32I-NEXT:    ret
-;
-; RV64I-LABEL: test_cttz_i16:
-; RV64I:       # %bb.0:
-; RV64I-NEXT:    slli a1, a0, 48
-; RV64I-NEXT:    srli a1, a1, 48
-; RV64I-NEXT:    beqz a1, .LBB1_2
-; RV64I-NEXT:  # %bb.1: # %cond.false
-; RV64I-NEXT:    addi a1, a0, -1
-; RV64I-NEXT:    not a0, a0
-; RV64I-NEXT:    and a0, a0, a1
-; RV64I-NEXT:    srli a1, a0, 1
-; RV64I-NEXT:    lui a2, 5
-; RV64I-NEXT:    addiw a2, a2, 1365
-; RV64I-NEXT:    and a1, a1, a2
-; RV64I-NEXT:    sub a0, a0, a1
-; RV64I-NEXT:    lui a1, 3
-; RV64I-NEXT:    addiw a1, a1, 819
-; RV64I-NEXT:    and a2, a0, a1
-; RV64I-NEXT:    srli a0, a0, 2
-; RV64I-NEXT:    and a0, a0, a1
-; RV64I-NEXT:    add a0, a2, a0
-; RV64I-NEXT:    srli a1, a0, 4
-; RV64I-NEXT:    add a0, a0, a1
-; RV64I-NEXT:    lui a1, 1
-; RV64I-NEXT:    addiw a1, a1, -241
-; RV64I-NEXT:    and a0, a0, a1
-; RV64I-NEXT:    slliw a1, a0, 8
-; RV64I-NEXT:    addw a0, a1, a0
-; RV64I-NEXT:    slli a0, a0, 51
-; RV64I-NEXT:    srli a0, a0, 59
-; RV64I-NEXT:    ret
-; RV64I-NEXT:  .LBB1_2:
-; RV64I-NEXT:    li a0, 16
-; RV64I-NEXT:    ret
+; RV32_NOZBB-LABEL: test_cttz_i16:
+; RV32_NOZBB:       # %bb.0:
+; RV32_NOZBB-NEXT:    slli a1, a0, 16
+; RV32_NOZBB-NEXT:    srli a1, a1, 16
+; RV32_NOZBB-NEXT:    beqz a1, .LBB1_2
+; RV32_NOZBB-NEXT:  # %bb.1: # %cond.false
+; RV32_NOZBB-NEXT:    addi a1, a0, -1
+; RV32_NOZBB-NEXT:    not a0, a0
+; RV32_NOZBB-NEXT:    and a0, a0, a1
+; RV32_NOZBB-NEXT:    srli a1, a0, 1
+; RV32_NOZBB-NEXT:    lui a2, 5
+; RV32_NOZBB-NEXT:    addi a2, a2, 1365
+; RV32_NOZBB-NEXT:    and a1, a1, a2
+; RV32_NOZBB-NEXT:    sub a0, a0, a1
+; RV32_NOZBB-NEXT:    lui a1, 3
+; RV32_NOZBB-NEXT:    addi a1, a1, 819
+; RV32_NOZBB-NEXT:    and a2, a0, a1
+; RV32_NOZBB-NEXT:    srli a0, a0, 2
+; RV32_NOZBB-NEXT:    and a0, a0, a1
+; RV32_NOZBB-NEXT:    add a0, a2, a0
+; RV32_NOZBB-NEXT:    srli a1, a0, 4
+; RV32_NOZBB-NEXT:    add a0, a0, a1
+; RV32_NOZBB-NEXT:    lui a1, 1
+; RV32_NOZBB-NEXT:    addi a1, a1, -241
+; RV32_NOZBB-NEXT:    and a0, a0, a1
+; RV32_NOZBB-NEXT:    slli a1, a0, 8
+; RV32_NOZBB-NEXT:    add a0, a1, a0
+; RV32_NOZBB-NEXT:    slli a0, a0, 19
+; RV32_NOZBB-NEXT:    srli a0, a0, 27
+; RV32_NOZBB-NEXT:    ret
+; RV32_NOZBB-NEXT:  .LBB1_2:
+; RV32_NOZBB-NEXT:    li a0, 16
+; RV32_NOZBB-NEXT:    ret
+;
+; RV64NOZBB-LABEL: test_cttz_i16:
+; RV64NOZBB:       # %bb.0:
+; RV64NOZBB-NEXT:    slli a1, a0, 48
+; RV64NOZBB-NEXT:    srli a1, a1, 48
+; RV64NOZBB-NEXT:    beqz a1, .LBB1_2
+; RV64NOZBB-NEXT:  # %bb.1: # %cond.false
+; RV64NOZBB-NEXT:    addi a1, a0, -1
+; RV64NOZBB-NEXT:    not a0, a0
+; RV64NOZBB-NEXT:    and a0, a0, a1
+; RV64NOZBB-NEXT:    srli a1, a0, 1
+; RV64NOZBB-NEXT:    lui a2, 5
+; RV64NOZBB-NEXT:    addiw a2, a2, 1365
+; RV64NOZBB-NEXT:    and a1, a1, a2
+; RV64NOZBB-NEXT:    sub a0, a0, a1
+; RV64NOZBB-NEXT:    lui a1, 3
+; RV64NOZBB-NEXT:    addiw a1, a1, 819
+; RV64NOZBB-NEXT:    and a2, a0, a1
+; RV64NOZBB-NEXT:    srli a0, a0, 2
+; RV64NOZBB-NEXT:    and a0, a0, a1
+; RV64NOZBB-NEXT:    add a0, a2, a0
+; RV64NOZBB-NEXT:    srli a1, a0, 4
+; RV64NOZBB-NEXT:    add a0, a0, a1
+; RV64NOZBB-NEXT:    lui a1, 1
+; RV64NOZBB-NEXT:    addiw a1, a1, -241
+; RV64NOZBB-NEXT:    and a0, a0, a1
+; RV64NOZBB-NEXT:    slliw a1, a0, 8
+; RV64NOZBB-NEXT:    addw a0, a1, a0
+; RV64NOZBB-NEXT:    slli a0, a0, 51
+; RV64NOZBB-NEXT:    srli a0, a0, 59
+; RV64NOZBB-NEXT:    ret
+; RV64NOZBB-NEXT:  .LBB1_2:
+; RV64NOZBB-NEXT:    li a0, 16
+; RV64NOZBB-NEXT:    ret
 ;
 ; RV32ZBB-LABEL: test_cttz_i16:
 ; RV32ZBB:       # %bb.0:
@@ -245,6 +249,71 @@ define i32 @test_cttz_i32(i32 %a) nounwind {
 ; RV64I-NEXT:    addi sp, sp, 16
 ; RV64I-NEXT:    ret
 ;
+; RV32M-LABEL: test_cttz_i32:
+; RV32M:       # %bb.0:
+; RV32M-NEXT:    beqz a0, .LBB2_2
+; RV32M-NEXT:  # %bb.1: # %cond.false
+; RV32M-NEXT:    addi a1, a0, -1
+; RV32M-NEXT:    not a0, a0
+; RV32M-NEXT:    and a0, a0, a1
+; RV32M-NEXT:    srli a1, a0, 1
+; RV32M-NEXT:    lui a2, 349525
+; RV32M-NEXT:    addi a2, a2, 1365
+; RV32M-NEXT:    and a1, a1, a2
+; RV32M-NEXT:    sub a0, a0, a1
+; RV32M-NEXT:    lui a1, 209715
+; RV32M-NEXT:    addi a1, a1, 819
+; RV32M-NEXT:    and a2, a0, a1
+; RV32M-NEXT:    srli a0, a0, 2
+; RV32M-NEXT:    and a0, a0, a1
+; RV32M-NEXT:    add a0, a2, a0
+; RV32M-NEXT:    srli a1, a0, 4
+; RV32M-NEXT:    add a0, a0, a1
+; RV32M-NEXT:    lui a1, 61681
+; RV32M-NEXT:    addi a1, a1, -241
+; RV32M-NEXT:    and a0, a0, a1
+; RV32M-NEXT:    lui a1, 4112
+; RV32M-NEXT:    addi a1, a1, 257
+; RV32M-NEXT:    mul a0, a0, a1
+; RV32M-NEXT:    srli a0, a0, 24
+; RV32M-NEXT:    ret
+; RV32M-NEXT:  .LBB2_2:
+; RV32M-NEXT:    li a0, 32
+; RV32M-NEXT:    ret
+;
+; RV64M-LABEL: test_cttz_i32:
+; RV64M:       # %bb.0:
+; RV64M-NEXT:    sext.w a1, a0
+; RV64M-NEXT:    beqz a1, .LBB2_2
+; RV64M-NEXT:  # %bb.1: # %cond.false
+; RV64M-NEXT:    addiw a1, a0, -1
+; RV64M-NEXT:    not a0, a0
+; RV64M-NEXT:    and a0, a0, a1
+; RV64M-NEXT:    srli a1, a0, 1
+; RV64M-NEXT:    lui a2, 349525
+; RV64M-NEXT:    addiw a2, a2, 1365
+; RV64M-NEXT:    and a1, a1, a2
+; RV64M-NEXT:    subw a0, a0, a1
+; RV64M-NEXT:    lui a1, 209715
+; RV64M-NEXT:    addiw a1, a1, 819
+; RV64M-NEXT:    and a2, a0, a1
+; RV64M-NEXT:    srli a0, a0, 2
+; RV64M-NEXT:    and a0, a0, a1
+; RV64M-NEXT:    add a0, a2, a0
+; RV64M-NEXT:    srli a1, a0, 4
+; RV64M-NEXT:    add a0, a0, a1
+; RV64M-NEXT:    lui a1, 61681
+; RV64M-NEXT:    addiw a1, a1, -241
+; RV64M-NEXT:    and a0, a0, a1
+; RV64M-NEXT:    lui a1, 4112
+; RV64M-NEXT:    addiw a1, a1, 257
+; RV64M-NEXT:    mulw a0, a0, a1
+; RV64M-NEXT:    srliw a0, a0, 24
+; RV64M-NEXT:    ret
+; RV64M-NEXT:  .LBB2_2:
+; RV64M-NEXT:    li a0, 32
+; RV64M-NEXT:    ret
+;
 ; RV32ZBB-LABEL: test_cttz_i32:
 ; RV32ZBB:       # %bb.0:
 ; RV32ZBB-NEXT:    ctz a0, a0
@@ -368,6 +437,87 @@ define i64 @test_cttz_i64(i64 %a) nounwind {
 ; RV64I-NEXT:    addi sp, sp, 16
 ; RV64I-NEXT:    ret
 ;
+; RV32M-LABEL: test_cttz_i64:
+; RV32M:       # %bb.0:
+; RV32M-NEXT:    lui a2, 349525
+; RV32M-NEXT:    addi a5, a2, 1365
+; RV32M-NEXT:    lui a2, 209715
+; RV32M-NEXT:    addi a4, a2, 819
+; RV32M-NEXT:    lui a2, 61681
+; RV32M-NEXT:    addi a2, a2, -241
+; RV32M-NEXT:    lui a3, 4112
+; RV32M-NEXT:    addi a3, a3, 257
+; RV32M-NEXT:    bnez a0, .LBB3_2
+; RV32M-NEXT:  # %bb.1:
+; RV32M-NEXT:    addi a0, a1, -1
+; RV32M-NEXT:    not a1, a1
+; RV32M-NEXT:    and a0, a1, a0
+; RV32M-NEXT:    srli a1, a0, 1
+; RV32M-NEXT:    and a1, a1, a5
+; RV32M-NEXT:    sub a0, a0, a1
+; RV32M-NEXT:    and a1, a0, a4
+; RV32M-NEXT:    srli a0, a0, 2
+; RV32M-NEXT:    and a0, a0, a4
+; RV32M-NEXT:    add a0, a1, a0
+; RV32M-NEXT:    srli a1, a0, 4
+; RV32M-NEXT:    add a0, a0, a1
+; RV32M-NEXT:    and a0, a0, a2
+; RV32M-NEXT:    mul a0, a0, a3
+; RV32M-NEXT:    srli a0, a0, 24
+; RV32M-NEXT:    addi a0, a0, 32
+; RV32M-NEXT:    li a1, 0
+; RV32M-NEXT:    ret
+; RV32M-NEXT:  .LBB3_2:
+; RV32M-NEXT:    addi a1, a0, -1
+; RV32M-NEXT:    not a0, a0
+; RV32M-NEXT:    and a0, a0, a1
+; RV32M-NEXT:    srli a1, a0, 1
+; RV32M-NEXT:    and a1, a1, a5
+; RV32M-NEXT:    sub a0, a0, a1
+; RV32M-NEXT:    and a1, a0, a4
+; RV32M-NEXT:    srli a0, a0, 2
+; RV32M-NEXT:    and a0, a0, a4
+; RV32M-NEXT:    add a0, a1, a0
+; RV32M-NEXT:    srli a1, a0, 4
+; RV32M-NEXT:    add a0, a0, a1
+; RV32M-NEXT:    and a0, a0, a2
+; RV32M-NEXT:    mul a0, a0, a3
+; RV32M-NEXT:    srli a0, a0, 24
+; RV32M-NEXT:    li a1, 0
+; RV32M-NEXT:    ret
+;
+; RV64M-LABEL: test_cttz_i64:
+; RV64M:       # %bb.0:
+; RV64M-NEXT:    beqz a0, .LBB3_2
+; RV64M-NEXT:  # %bb.1: # %cond.false
+; RV64M-NEXT:    addi a1, a0, -1
+; RV64M-NEXT:    not a0, a0
+; RV64M-NEXT:    and a0, a0, a1
+; RV64M-NEXT:    lui a1, %hi(.LCPI3_0)
+; RV64M-NEXT:    ld a1, %lo(.LCPI3_0)(a1)
+; RV64M-NEXT:    lui a2, %hi(.LCPI3_1)
+; RV64M-NEXT:    ld a2, %lo(.LCPI3_1)(a2)
+; RV64M-NEXT:    srli a3, a0, 1
+; RV64M-NEXT:    and a1, a3, a1
+; RV64M-NEXT:    sub a0, a0, a1
+; RV64M-NEXT:    and a1, a0, a2
+; RV64M-NEXT:    srli a0, a0, 2
+; RV64M-NEXT:    and a0, a0, a2
+; RV64M-NEXT:    add a0, a1, a0
+; RV64M-NEXT:    lui a1, %hi(.LCPI3_2)
+; RV64M-NEXT:    ld a1, %lo(.LCPI3_2)(a1)
+; RV64M-NEXT:    lui a2, %hi(.LCPI3_3)
+; RV64M-NEXT:    ld a2, %lo(.LCPI3_3)(a2)
+; RV64M-NEXT:    srli a3, a0, 4
+; RV64M-NEXT:    add a0, a0, a3
+; RV64M-NEXT:    and a0, a0, a1
+; RV64M-NEXT:    mul a0, a0, a2
+; RV64M-NEXT:    srli a0, a0, 56
+; RV64M-NEXT:    ret
+; RV64M-NEXT:  .LBB3_2:
+; RV64M-NEXT:    li a0, 64
+; RV64M-NEXT:    ret
+;
 ; RV32ZBB-LABEL: test_cttz_i64:
 ; RV32ZBB:       # %bb.0:
 ; RV32ZBB-NEXT:    bnez a0, .LBB3_2
@@ -390,39 +540,39 @@ define i64 @test_cttz_i64(i64 %a) nounwind {
 }
 
 define i8 @test_cttz_i8_zero_undef(i8 %a) nounwind {
-; RV32I-LABEL: test_cttz_i8_zero_undef:
-; RV32I:       # %bb.0:
-; RV32I-NEXT:    addi a1, a0, -1
-; RV32I-NEXT:    not a0, a0
-; RV32I-NEXT:    and a0, a0, a1
-; RV32I-NEXT:    srli a1, a0, 1
-; RV32I-NEXT:    andi a1, a1, 85
-; RV32I-NEXT:    sub a0, a0, a1
-; RV32I-NEXT:    andi a1, a0, 51
-; RV32I-NEXT:    srli a0, a0, 2
-; RV32I-NEXT:    andi a0, a0, 51
-; RV32I-NEXT:    add a0, a1, a0
-; RV32I-NEXT:    srli a1, a0, 4
-; RV32I-NEXT:    add a0, a0, a1
-; RV32I-NEXT:    andi a0, a0, 15
-; RV32I-NEXT:    ret
-;
-; RV64I-LABEL: test_cttz_i8_zero_undef:
-; RV64I:       # %bb.0:
-; RV64I-NEXT:    addi a1, a0, -1
-; RV64I-NEXT:    not a0, a0
-; RV64I-NEXT:    and a0, a0, a1
-; RV64I-NEXT:    srli a1, a0, 1
-; RV64I-NEXT:    andi a1, a1, 85
-; RV64I-NEXT:    sub a0, a0, a1
-; RV64I-NEXT:    andi a1, a0, 51
-; RV64I-NEXT:    srli a0, a0, 2
-; RV64I-NEXT:    andi a0, a0, 51
-; RV64I-NEXT:    add a0, a1, a0
-; RV64I-NEXT:    srli a1, a0, 4
-; RV64I-NEXT:    addw a0, a0, a1
-; RV64I-NEXT:    andi a0, a0, 15
-; RV64I-NEXT:    ret
+; RV32_NOZBB-LABEL: test_cttz_i8_zero_undef:
+; RV32_NOZBB:       # %bb.0:
+; RV32_NOZBB-NEXT:    addi a1, a0, -1
+; RV32_NOZBB-NEXT:    not a0, a0
+; RV32_NOZBB-NEXT:    and a0, a0, a1
+; RV32_NOZBB-NEXT:    srli a1, a0, 1
+; RV32_NOZBB-NEXT:    andi a1, a1, 85
+; RV32_NOZBB-NEXT:    sub a0, a0, a1
+; RV32_NOZBB-NEXT:    andi a1, a0, 51
+; RV32_NOZBB-NEXT:    srli a0, a0, 2
+; RV32_NOZBB-NEXT:    andi a0, a0, 51
+; RV32_NOZBB-NEXT:    add a0, a1, a0
+; RV32_NOZBB-NEXT:    srli a1, a0, 4
+; RV32_NOZBB-NEXT:    add a0, a0, a1
+; RV32_NOZBB-NEXT:    andi a0, a0, 15
+; RV32_NOZBB-NEXT:    ret
+;
+; RV64NOZBB-LABEL: test_cttz_i8_zero_undef:
+; RV64NOZBB:       # %bb.0:
+; RV64NOZBB-NEXT:    addi a1, a0, -1
+; RV64NOZBB-NEXT:    not a0, a0
+; RV64NOZBB-NEXT:    and a0, a0, a1
+; RV64NOZBB-NEXT:    srli a1, a0, 1
+; RV64NOZBB-NEXT:    andi a1, a1, 85
+; RV64NOZBB-NEXT:    sub a0, a0, a1
+; RV64NOZBB-NEXT:    andi a1, a0, 51
+; RV64NOZBB-NEXT:    srli a0, a0, 2
+; RV64NOZBB-NEXT:    andi a0, a0, 51
+; RV64NOZBB-NEXT:    add a0, a1, a0
+; RV64NOZBB-NEXT:    srli a1, a0, 4
+; RV64NOZBB-NEXT:    addw a0, a0, a1
+; RV64NOZBB-NEXT:    andi a0, a0, 15
+; RV64NOZBB-NEXT:    ret
 ;
 ; RV32ZBB-LABEL: test_cttz_i8_zero_undef:
 ; RV32ZBB:       # %bb.0:
@@ -438,59 +588,59 @@ define i8 @test_cttz_i8_zero_undef(i8 %a) nounwind {
 }
 
 define i16 @test_cttz_i16_zero_undef(i16 %a) nounwind {
-; RV32I-LABEL: test_cttz_i16_zero_undef:
-; RV32I:       # %bb.0:
-; RV32I-NEXT:    addi a1, a0, -1
-; RV32I-NEXT:    not a0, a0
-; RV32I-NEXT:    and a0, a0, a1
-; RV32I-NEXT:    srli a1, a0, 1
-; RV32I-NEXT:    lui a2, 5
-; RV32I-NEXT:    addi a2, a2, 1365
-; RV32I-NEXT:    and a1, a1, a2
-; RV32I-NEXT:    sub a0, a0, a1
-; RV32I-NEXT:    lui a1, 3
-; RV32I-NEXT:    addi a1, a1, 819
-; RV32I-NEXT:    and a2, a0, a1
-; RV32I-NEXT:    srli a0, a0, 2
-; RV32I-NEXT:    and a0, a0, a1
-; RV32I-NEXT:    add a0, a2, a0
-; RV32I-NEXT:    srli a1, a0, 4
-; RV32I-NEXT:    add a0, a0, a1
-; RV32I-NEXT:    lui a1, 1
-; RV32I-NEXT:    addi a1, a1, -241
-; RV32I-NEXT:    and a0, a0, a1
-; RV32I-NEXT:    slli a1, a0, 8
-; RV32I-NEXT:    add a0, a1, a0
-; RV32I-NEXT:    slli a0, a0, 19
-; RV32I-NEXT:    srli a0, a0, 27
-; RV32I-NEXT:    ret
-;
-; RV64I-LABEL: test_cttz_i16_zero_undef:
-; RV64I:       # %bb.0:
-; RV64I-NEXT:    addi a1, a0, -1
-; RV64I-NEXT:    not a0, a0
-; RV64I-NEXT:    and a0, a0, a1
-; RV64I-NEXT:    srli a1, a0, 1
-; RV64I-NEXT:    lui a2, 5
-; RV64I-NEXT:    addiw a2, a2, 1365
-; RV64I-NEXT:    and a1, a1, a2
-; RV64I-NEXT:    sub a0, a0, a1
-; RV64I-NEXT:    lui a1, 3
-; RV64I-NEXT:    addiw a1, a1, 819
-; RV64I-NEXT:    and a2, a0, a1
-; RV64I-NEXT:    srli a0, a0, 2
-; RV64I-NEXT:    and a0, a0, a1
-; RV64I-NEXT:    add a0, a2, a0
-; RV64I-NEXT:    srli a1, a0, 4
-; RV64I-NEXT:    add a0, a0, a1
-; RV64I-NEXT:    lui a1, 1
-; RV64I-NEXT:    addiw a1, a1, -241
-; RV64I-NEXT:    and a0, a0, a1
-; RV64I-NEXT:    slliw a1, a0, 8
-; RV64I-NEXT:    addw a0, a1, a0
-; RV64I-NEXT:    slli a0, a0, 51
-; RV64I-NEXT:    srli a0, a0, 59
-; RV64I-NEXT:    ret
+; RV32_NOZBB-LABEL: test_cttz_i16_zero_undef:
+; RV32_NOZBB:       # %bb.0:
+; RV32_NOZBB-NEXT:    addi a1, a0, -1
+; RV32_NOZBB-NEXT:    not a0, a0
+; RV32_NOZBB-NEXT:    and a0, a0, a1
+; RV32_NOZBB-NEXT:    srli a1, a0, 1
+; RV32_NOZBB-NEXT:    lui a2, 5
+; RV32_NOZBB-NEXT:    addi a2, a2, 1365
+; RV32_NOZBB-NEXT:    and a1, a1, a2
+; RV32_NOZBB-NEXT:    sub a0, a0, a1
+; RV32_NOZBB-NEXT:    lui a1, 3
+; RV32_NOZBB-NEXT:    addi a1, a1, 819
+; RV32_NOZBB-NEXT:    and a2, a0, a1
+; RV32_NOZBB-NEXT:    srli a0, a0, 2
+; RV32_NOZBB-NEXT:    and a0, a0, a1
+; RV32_NOZBB-NEXT:    add a0, a2, a0
+; RV32_NOZBB-NEXT:    srli a1, a0, 4
+; RV32_NOZBB-NEXT:    add a0, a0, a1
+; RV32_NOZBB-NEXT:    lui a1, 1
+; RV32_NOZBB-NEXT:    addi a1, a1, -241
+; RV32_NOZBB-NEXT:    and a0, a0, a1
+; RV32_NOZBB-NEXT:    slli a1, a0, 8
+; RV32_NOZBB-NEXT:    add a0, a1, a0
+; RV32_NOZBB-NEXT:    slli a0, a0, 19
+; RV32_NOZBB-NEXT:    srli a0, a0, 27
+; RV32_NOZBB-NEXT:    ret
+;
+; RV64NOZBB-LABEL: test_cttz_i16_zero_undef:
+; RV64NOZBB:       # %bb.0:
+; RV64NOZBB-NEXT:    addi a1, a0, -1
+; RV64NOZBB-NEXT:    not a0, a0
+; RV64NOZBB-NEXT:    and a0, a0, a1
+; RV64NOZBB-NEXT:    srli a1, a0, 1
+; RV64NOZBB-NEXT:    lui a2, 5
+; RV64NOZBB-NEXT:    addiw a2, a2, 1365
+; RV64NOZBB-NEXT:    and a1, a1, a2
+; RV64NOZBB-NEXT:    sub a0, a0, a1
+; RV64NOZBB-NEXT:    lui a1, 3
+; RV64NOZBB-NEXT:    addiw a1, a1, 819
+; RV64NOZBB-NEXT:    and a2, a0, a1
+; RV64NOZBB-NEXT:    srli a0, a0, 2
+; RV64NOZBB-NEXT:    and a0, a0, a1
+; RV64NOZBB-NEXT:    add a0, a2, a0
+; RV64NOZBB-NEXT:    srli a1, a0, 4
+; RV64NOZBB-NEXT:    add a0, a0, a1
+; RV64NOZBB-NEXT:    lui a1, 1
+; RV64NOZBB-NEXT:    addiw a1, a1, -241
+; RV64NOZBB-NEXT:    and a0, a0, a1
+; RV64NOZBB-NEXT:    slliw a1, a0, 8
+; RV64NOZBB-NEXT:    addw a0, a1, a0
+; RV64NOZBB-NEXT:    slli a0, a0, 51
+; RV64NOZBB-NEXT:    srli a0, a0, 59
+; RV64NOZBB-NEXT:    ret
 ;
 ; RV32ZBB-LABEL: test_cttz_i16_zero_undef:
 ; RV32ZBB:       # %bb.0:
@@ -568,6 +718,60 @@ define i32 @test_cttz_i32_zero_undef(i32 %a) nounwind {
 ; RV64I-NEXT:    addi sp, sp, 16
 ; RV64I-NEXT:    ret
 ;
+; RV32M-LABEL: test_cttz_i32_zero_undef:
+; RV32M:       # %bb.0:
+; RV32M-NEXT:    addi a1, a0, -1
+; RV32M-NEXT:    not a0, a0
+; RV32M-NEXT:    and a0, a0, a1
+; RV32M-NEXT:    srli a1, a0, 1
+; RV32M-NEXT:    lui a2, 349525
+; RV32M-NEXT:    addi a2, a2, 1365
+; RV32M-NEXT:    and a1, a1, a2
+; RV32M-NEXT:    sub a0, a0, a1
+; RV32M-NEXT:    lui a1, 209715
+; RV32M-NEXT:    addi a1, a1, 819
+; RV32M-NEXT:    and a2, a0, a1
+; RV32M-NEXT:    srli a0, a0, 2
+; RV32M-NEXT:    and a0, a0, a1
+; RV32M-NEXT:    add a0, a2, a0
+; RV32M-NEXT:    srli a1, a0, 4
+; RV32M-NEXT:    add a0, a0, a1
+; RV32M-NEXT:    lui a1, 61681
+; RV32M-NEXT:    addi a1, a1, -241
+; RV32M-NEXT:    and a0, a0, a1
+; RV32M-NEXT:    lui a1, 4112
+; RV32M-NEXT:    addi a1, a1, 257
+; RV32M-NEXT:    mul a0, a0, a1
+; RV32M-NEXT:    srli a0, a0, 24
+; RV32M-NEXT:    ret
+;
+; RV64M-LABEL: test_cttz_i32_zero_undef:
+; RV64M:       # %bb.0:
+; RV64M-NEXT:    addiw a1, a0, -1
+; RV64M-NEXT:    not a0, a0
+; RV64M-NEXT:    and a0, a0, a1
+; RV64M-NEXT:    srli a1, a0, 1
+; RV64M-NEXT:    lui a2, 349525
+; RV64M-NEXT:    addiw a2, a2, 1365
+; RV64M-NEXT:    and a1, a1, a2
+; RV64M-NEXT:    subw a0, a0, a1
+; RV64M-NEXT:    lui a1, 209715
+; RV64M-NEXT:    addiw a1, a1, 819
+; RV64M-NEXT:    and a2, a0, a1
+; RV64M-NEXT:    srli a0, a0, 2
+; RV64M-NEXT:    and a0, a0, a1
+; RV64M-NEXT:    add a0, a2, a0
+; RV64M-NEXT:    srli a1, a0, 4
+; RV64M-NEXT:    add a0, a0, a1
+; RV64M-NEXT:    lui a1, 61681
+; RV64M-NEXT:    addiw a1, a1, -241
+; RV64M-NEXT:    and a0, a0, a1
+; RV64M-NEXT:    lui a1, 4112
+; RV64M-NEXT:    addiw a1, a1, 257
+; RV64M-NEXT:    mulw a0, a0, a1
+; RV64M-NEXT:    srliw a0, a0, 24
+; RV64M-NEXT:    ret
+;
 ; RV32ZBB-LABEL: test_cttz_i32_zero_undef:
 ; RV32ZBB:       # %bb.0:
 ; RV32ZBB-NEXT:    ctz a0, a0
@@ -685,6 +889,82 @@ define i64 @test_cttz_i64_zero_undef(i64 %a) nounwind {
 ; RV64I-NEXT:    addi sp, sp, 16
 ; RV64I-NEXT:    ret
 ;
+; RV32M-LABEL: test_cttz_i64_zero_undef:
+; RV32M:       # %bb.0:
+; RV32M-NEXT:    lui a2, 349525
+; RV32M-NEXT:    addi a5, a2, 1365
+; RV32M-NEXT:    lui a2, 209715
+; RV32M-NEXT:    addi a4, a2, 819
+; RV32M-NEXT:    lui a2, 61681
+; RV32M-NEXT:    addi a2, a2, -241
+; RV32M-NEXT:    lui a3, 4112
+; RV32M-NEXT:    addi a3, a3, 257
+; RV32M-NEXT:    bnez a0, .LBB7_2
+; RV32M-NEXT:  # %bb.1:
+; RV32M-NEXT:    addi a0, a1, -1
+; RV32M-NEXT:    not a1, a1
+; RV32M-NEXT:    and a0, a1, a0
+; RV32M-NEXT:    srli a1, a0, 1
+; RV32M-NEXT:    and a1, a1, a5
+; RV32M-NEXT:    sub a0, a0, a1
+; RV32M-NEXT:    and a1, a0, a4
+; RV32M-NEXT:    srli a0, a0, 2
+; RV32M-NEXT:    and a0, a0, a4
+; RV32M-NEXT:    add a0, a1, a0
+; RV32M-NEXT:    srli a1, a0, 4
+; RV32M-NEXT:    add a0, a0, a1
+; RV32M-NEXT:    and a0, a0, a2
+; RV32M-NEXT:    mul a0, a0, a3
+; RV32M-NEXT:    srli a0, a0, 24
+; RV32M-NEXT:    addi a0, a0, 32
+; RV32M-NEXT:    li a1, 0
+; RV32M-NEXT:    ret
+; RV32M-NEXT:  .LBB7_2:
+; RV32M-NEXT:    addi a1, a0, -1
+; RV32M-NEXT:    not a0, a0
+; RV32M-NEXT:    and a0, a0, a1
+; RV32M-NEXT:    srli a1, a0, 1
+; RV32M-NEXT:    and a1, a1, a5
+; RV32M-NEXT:    sub a0, a0, a1
+; RV32M-NEXT:    and a1, a0, a4
+; RV32M-NEXT:    srli a0, a0, 2
+; RV32M-NEXT:    and a0, a0, a4
+; RV32M-NEXT:    add a0, a1, a0
+; RV32M-NEXT:    srli a1, a0, 4
+; RV32M-NEXT:    add a0, a0, a1
+; RV32M-NEXT:    and a0, a0, a2
+; RV32M-NEXT:    mul a0, a0, a3
+; RV32M-NEXT:    srli a0, a0, 24
+; RV32M-NEXT:    li a1, 0
+; RV32M-NEXT:    ret
+;
+; RV64M-LABEL: test_cttz_i64_zero_undef:
+; RV64M:       # %bb.0:
+; RV64M-NEXT:    addi a1, a0, -1
+; RV64M-NEXT:    not a0, a0
+; RV64M-NEXT:    and a0, a0, a1
+; RV64M-NEXT:    lui a1, %hi(.LCPI7_0)
+; RV64M-NEXT:    ld a1, %lo(.LCPI7_0)(a1)
+; RV64M-NEXT:    lui a2, %hi(.LCPI7_1)
+; RV64M-NEXT:    ld a2, %lo(.LCPI7_1)(a2)
+; RV64M-NEXT:    srli a3, a0, 1
+; RV64M-NEXT:    and a1, a3, a1
+; RV64M-NEXT:    sub a0, a0, a1
+; RV64M-NEXT:    and a1, a0, a2
+; RV64M-NEXT:    srli a0, a0, 2
+; RV64M-NEXT:    and a0, a0, a2
+; RV64M-NEXT:    add a0, a1, a0
+; RV64M-NEXT:    lui a1, %hi(.LCPI7_2)
+; RV64M-NEXT:    ld a1, %lo(.LCPI7_2)(a1)
+; RV64M-NEXT:    lui a2, %hi(.LCPI7_3)
+; RV64M-NEXT:    ld a2, %lo(.LCPI7_3)(a2)
+; RV64M-NEXT:    srli a3, a0, 4
+; RV64M-NEXT:    add a0, a0, a3
+; RV64M-NEXT:    and a0, a0, a1
+; RV64M-NEXT:    mul a0, a0, a2
+; RV64M-NEXT:    srli a0, a0, 56
+; RV64M-NEXT:    ret
+;
 ; RV32ZBB-LABEL: test_cttz_i64_zero_undef:
 ; RV32ZBB:       # %bb.0:
 ; RV32ZBB-NEXT:    bnez a0, .LBB7_2
@@ -707,65 +987,65 @@ define i64 @test_cttz_i64_zero_undef(i64 %a) nounwind {
 }
 
 define i8 @test_ctlz_i8(i8 %a) nounwind {
-; RV32I-LABEL: test_ctlz_i8:
-; RV32I:       # %bb.0:
-; RV32I-NEXT:    andi a1, a0, 255
-; RV32I-NEXT:    beqz a1, .LBB8_2
-; RV32I-NEXT:  # %bb.1: # %cond.false
-; RV32I-NEXT:    slli a1, a0, 24
-; RV32I-NEXT:    srli a1, a1, 25
-; RV32I-NEXT:    or a0, a0, a1
-; RV32I-NEXT:    slli a1, a0, 24
-; RV32I-NEXT:    srli a1, a1, 26
-; RV32I-NEXT:    or a0, a0, a1
-; RV32I-NEXT:    slli a1, a0, 24
-; RV32I-NEXT:    srli a1, a1, 28
-; RV32I-NEXT:    or a0, a0, a1
-; RV32I-NEXT:    not a0, a0
-; RV32I-NEXT:    srli a1, a0, 1
-; RV32I-NEXT:    andi a1, a1, 85
-; RV32I-NEXT:    sub a0, a0, a1
-; RV32I-NEXT:    andi a1, a0, 51
-; RV32I-NEXT:    srli a0, a0, 2
-; RV32I-NEXT:    andi a0, a0, 51
-; RV32I-NEXT:    add a0, a1, a0
-; RV32I-NEXT:    srli a1, a0, 4
-; RV32I-NEXT:    add a0, a0, a1
-; RV32I-NEXT:    andi a0, a0, 15
-; RV32I-NEXT:    ret
-; RV32I-NEXT:  .LBB8_2:
-; RV32I-NEXT:    li a0, 8
-; RV32I-NEXT:    ret
-;
-; RV64I-LABEL: test_ctlz_i8:
-; RV64I:       # %bb.0:
-; RV64I-NEXT:    andi a1, a0, 255
-; RV64I-NEXT:    beqz a1, .LBB8_2
-; RV64I-NEXT:  # %bb.1: # %cond.false
-; RV64I-NEXT:    slli a1, a0, 56
-; RV64I-NEXT:    srli a1, a1, 57
-; RV64I-NEXT:    or a0, a0, a1
-; RV64I-NEXT:    slli a1, a0, 56
-; RV64I-NEXT:    srli a1, a1, 58
-; RV64I-NEXT:    or a0, a0, a1
-; RV64I-NEXT:    slli a1, a0, 56
-; RV64I-NEXT:    srli a1, a1, 60
-; RV64I-NEXT:    or a0, a0, a1
-; RV64I-NEXT:    not a0, a0
-; RV64I-NEXT:    srli a1, a0, 1
-; RV64I-NEXT:    andi a1, a1, 85
-; RV64I-NEXT:    sub a0, a0, a1
-; RV64I-NEXT:    andi a1, a0, 51
-; RV64I-NEXT:    srli a0, a0, 2
-; RV64I-NEXT:    andi a0, a0, 51
-; RV64I-NEXT:    add a0, a1, a0
-; RV64I-NEXT:    srli a1, a0, 4
-; RV64I-NEXT:    addw a0, a0, a1
-; RV64I-NEXT:    andi a0, a0, 15
-; RV64I-NEXT:    ret
-; RV64I-NEXT:  .LBB8_2:
-; RV64I-NEXT:    li a0, 8
-; RV64I-NEXT:    ret
+; RV32_NOZBB-LABEL: test_ctlz_i8:
+; RV32_NOZBB:       # %bb.0:
+; RV32_NOZBB-NEXT:    andi a1, a0, 255
+; RV32_NOZBB-NEXT:    beqz a1, .LBB8_2
+; RV32_NOZBB-NEXT:  # %bb.1: # %cond.false
+; RV32_NOZBB-NEXT:    slli a1, a0, 24
+; RV32_NOZBB-NEXT:    srli a1, a1, 25
+; RV32_NOZBB-NEXT:    or a0, a0, a1
+; RV32_NOZBB-NEXT:    slli a1, a0, 24
+; RV32_NOZBB-NEXT:    srli a1, a1, 26
+; RV32_NOZBB-NEXT:    or a0, a0, a1
+; RV32_NOZBB-NEXT:    slli a1, a0, 24
+; RV32_NOZBB-NEXT:    srli a1, a1, 28
+; RV32_NOZBB-NEXT:    or a0, a0, a1
+; RV32_NOZBB-NEXT:    not a0, a0
+; RV32_NOZBB-NEXT:    srli a1, a0, 1
+; RV32_NOZBB-NEXT:    andi a1, a1, 85
+; RV32_NOZBB-NEXT:    sub a0, a0, a1
+; RV32_NOZBB-NEXT:    andi a1, a0, 51
+; RV32_NOZBB-NEXT:    srli a0, a0, 2
+; RV32_NOZBB-NEXT:    andi a0, a0, 51
+; RV32_NOZBB-NEXT:    add a0, a1, a0
+; RV32_NOZBB-NEXT:    srli a1, a0, 4
+; RV32_NOZBB-NEXT:    add a0, a0, a1
+; RV32_NOZBB-NEXT:    andi a0, a0, 15
+; RV32_NOZBB-NEXT:    ret
+; RV32_NOZBB-NEXT:  .LBB8_2:
+; RV32_NOZBB-NEXT:    li a0, 8
+; RV32_NOZBB-NEXT:    ret
+;
+; RV64NOZBB-LABEL: test_ctlz_i8:
+; RV64NOZBB:       # %bb.0:
+; RV64NOZBB-NEXT:    andi a1, a0, 255
+; RV64NOZBB-NEXT:    beqz a1, .LBB8_2
+; RV64NOZBB-NEXT:  # %bb.1: # %cond.false
+; RV64NOZBB-NEXT:    slli a1, a0, 56
+; RV64NOZBB-NEXT:    srli a1, a1, 57
+; RV64NOZBB-NEXT:    or a0, a0, a1
+; RV64NOZBB-NEXT:    slli a1, a0, 56
+; RV64NOZBB-NEXT:    srli a1, a1, 58
+; RV64NOZBB-NEXT:    or a0, a0, a1
+; RV64NOZBB-NEXT:    slli a1, a0, 56
+; RV64NOZBB-NEXT:    srli a1, a1, 60
+; RV64NOZBB-NEXT:    or a0, a0, a1
+; RV64NOZBB-NEXT:    not a0, a0
+; RV64NOZBB-NEXT:    srli a1, a0, 1
+; RV64NOZBB-NEXT:    andi a1, a1, 85
+; RV64NOZBB-NEXT:    sub a0, a0, a1
+; RV64NOZBB-NEXT:    andi a1, a0, 51
+; RV64NOZBB-NEXT:    srli a0, a0, 2
+; RV64NOZBB-NEXT:    andi a0, a0, 51
+; RV64NOZBB-NEXT:    add a0, a1, a0
+; RV64NOZBB-NEXT:    srli a1, a0, 4
+; RV64NOZBB-NEXT:    addw a0, a0, a1
+; RV64NOZBB-NEXT:    andi a0, a0, 15
+; RV64NOZBB-NEXT:    ret
+; RV64NOZBB-NEXT:  .LBB8_2:
+; RV64NOZBB-NEXT:    li a0, 8
+; RV64NOZBB-NEXT:    ret
 ;
 ; RV32ZBB-LABEL: test_ctlz_i8:
 ; RV32ZBB:       # %bb.0:
@@ -785,91 +1065,91 @@ define i8 @test_ctlz_i8(i8 %a) nounwind {
 }
 
 define i16 @test_ctlz_i16(i16 %a) nounwind {
-; RV32I-LABEL: test_ctlz_i16:
-; RV32I:       # %bb.0:
-; RV32I-NEXT:    slli a1, a0, 16
-; RV32I-NEXT:    srli a2, a1, 16
-; RV32I-NEXT:    beqz a2, .LBB9_2
-; RV32I-NEXT:  # %bb.1: # %cond.false
-; RV32I-NEXT:    srli a1, a1, 17
-; RV32I-NEXT:    or a0, a0, a1
-; RV32I-NEXT:    slli a1, a0, 16
-; RV32I-NEXT:    srli a1, a1, 18
-; RV32I-NEXT:    or a0, a0, a1
-; RV32I-NEXT:    slli a1, a0, 16
-; RV32I-NEXT:    srli a1, a1, 20
-; RV32I-NEXT:    or a0, a0, a1
-; RV32I-NEXT:    slli a1, a0, 16
-; RV32I-NEXT:    srli a1, a1, 24
-; RV32I-NEXT:    or a0, a0, a1
-; RV32I-NEXT:    not a0, a0
-; RV32I-NEXT:    srli a1, a0, 1
-; RV32I-NEXT:    lui a2, 5
-; RV32I-NEXT:    addi a2, a2, 1365
-; RV32I-NEXT:    and a1, a1, a2
-; RV32I-NEXT:    sub a0, a0, a1
-; RV32I-NEXT:    lui a1, 3
-; RV32I-NEXT:    addi a1, a1, 819
-; RV32I-NEXT:    and a2, a0, a1
-; RV32I-NEXT:    srli a0, a0, 2
-; RV32I-NEXT:    and a0, a0, a1
-; RV32I-NEXT:    add a0, a2, a0
-; RV32I-NEXT:    srli a1, a0, 4
-; RV32I-NEXT:    add a0, a0, a1
-; RV32I-NEXT:    lui a1, 1
-; RV32I-NEXT:    addi a1, a1, -241
-; RV32I-NEXT:    and a0, a0, a1
-; RV32I-NEXT:    slli a1, a0, 8
-; RV32I-NEXT:    add a0, a1, a0
-; RV32I-NEXT:    slli a0, a0, 19
-; RV32I-NEXT:    srli a0, a0, 27
-; RV32I-NEXT:    ret
-; RV32I-NEXT:  .LBB9_2:
-; RV32I-NEXT:    li a0, 16
-; RV32I-NEXT:    ret
-;
-; RV64I-LABEL: test_ctlz_i16:
-; RV64I:       # %bb.0:
-; RV64I-NEXT:    slli a1, a0, 48
-; RV64I-NEXT:    srli a2, a1, 48
-; RV64I-NEXT:    beqz a2, .LBB9_2
-; RV64I-NEXT:  # %bb.1: # %cond.false
-; RV64I-NEXT:    srli a1, a1, 49
-; RV64I-NEXT:    or a0, a0, a1
-; RV64I-NEXT:    slli a1, a0, 48
-; RV64I-NEXT:    srli a1, a1, 50
-; RV64I-NEXT:    or a0, a0, a1
-; RV64I-NEXT:    slli a1, a0, 48
-; RV64I-NEXT:    srli a1, a1, 52
-; RV64I-NEXT:    or a0, a0, a1
-; RV64I-NEXT:    slli a1, a0, 48
-; RV64I-NEXT:    srli a1, a1, 56
-; RV64I-NEXT:    or a0, a0, a1
-; RV64I-NEXT:    not a0, a0
-; RV64I-NEXT:    srli a1, a0, 1
-; RV64I-NEXT:    lui a2, 5
-; RV64I-NEXT:    addiw a2, a2, 1365
-; RV64I-NEXT:    and a1, a1, a2
-; RV64I-NEXT:    sub a0, a0, a1
-; RV64I-NEXT:    lui a1, 3
-; RV64I-NEXT:    addiw a1, a1, 819
-; RV64I-NEXT:    and a2, a0, a1
-; RV64I-NEXT:    srli a0, a0, 2
-; RV64I-NEXT:    and a0, a0, a1
-; RV64I-NEXT:    add a0, a2, a0
-; RV64I-NEXT:    srli a1, a0, 4
-; RV64I-NEXT:    add a0, a0, a1
-; RV64I-NEXT:    lui a1, 1
-; RV64I-NEXT:    addiw a1, a1, -241
-; RV64I-NEXT:    and a0, a0, a1
-; RV64I-NEXT:    slliw a1, a0, 8
-; RV64I-NEXT:    addw a0, a1, a0
-; RV64I-NEXT:    slli a0, a0, 51
-; RV64I-NEXT:    srli a0, a0, 59
-; RV64I-NEXT:    ret
-; RV64I-NEXT:  .LBB9_2:
-; RV64I-NEXT:    li a0, 16
-; RV64I-NEXT:    ret
+; RV32_NOZBB-LABEL: test_ctlz_i16:
+; RV32_NOZBB:       # %bb.0:
+; RV32_NOZBB-NEXT:    slli a1, a0, 16
+; RV32_NOZBB-NEXT:    srli a2, a1, 16
+; RV32_NOZBB-NEXT:    beqz a2, .LBB9_2
+; RV32_NOZBB-NEXT:  # %bb.1: # %cond.false
+; RV32_NOZBB-NEXT:    srli a1, a1, 17
+; RV32_NOZBB-NEXT:    or a0, a0, a1
+; RV32_NOZBB-NEXT:    slli a1, a0, 16
+; RV32_NOZBB-NEXT:    srli a1, a1, 18
+; RV32_NOZBB-NEXT:    or a0, a0, a1
+; RV32_NOZBB-NEXT:    slli a1, a0, 16
+; RV32_NOZBB-NEXT:    srli a1, a1, 20
+; RV32_NOZBB-NEXT:    or a0, a0, a1
+; RV32_NOZBB-NEXT:    slli a1, a0, 16
+; RV32_NOZBB-NEXT:    srli a1, a1, 24
+; RV32_NOZBB-NEXT:    or a0, a0, a1
+; RV32_NOZBB-NEXT:    not a0, a0
+; RV32_NOZBB-NEXT:    srli a1, a0, 1
+; RV32_NOZBB-NEXT:    lui a2, 5
+; RV32_NOZBB-NEXT:    addi a2, a2, 1365
+; RV32_NOZBB-NEXT:    and a1, a1, a2
+; RV32_NOZBB-NEXT:    sub a0, a0, a1
+; RV32_NOZBB-NEXT:    lui a1, 3
+; RV32_NOZBB-NEXT:    addi a1, a1, 819
+; RV32_NOZBB-NEXT:    and a2, a0, a1
+; RV32_NOZBB-NEXT:    srli a0, a0, 2
+; RV32_NOZBB-NEXT:    and a0, a0, a1
+; RV32_NOZBB-NEXT:    add a0, a2, a0
+; RV32_NOZBB-NEXT:    srli a1, a0, 4
+; RV32_NOZBB-NEXT:    add a0, a0, a1
+; RV32_NOZBB-NEXT:    lui a1, 1
+; RV32_NOZBB-NEXT:    addi a1, a1, -241
+; RV32_NOZBB-NEXT:    and a0, a0, a1
+; RV32_NOZBB-NEXT:    slli a1, a0, 8
+; RV32_NOZBB-NEXT:    add a0, a1, a0
+; RV32_NOZBB-NEXT:    slli a0, a0, 19
+; RV32_NOZBB-NEXT:    srli a0, a0, 27
+; RV32_NOZBB-NEXT:    ret
+; RV32_NOZBB-NEXT:  .LBB9_2:
+; RV32_NOZBB-NEXT:    li a0, 16
+; RV32_NOZBB-NEXT:    ret
+;
+; RV64NOZBB-LABEL: test_ctlz_i16:
+; RV64NOZBB:       # %bb.0:
+; RV64NOZBB-NEXT:    slli a1, a0, 48
+; RV64NOZBB-NEXT:    srli a2, a1, 48
+; RV64NOZBB-NEXT:    beqz a2, .LBB9_2
+; RV64NOZBB-NEXT:  # %bb.1: # %cond.false
+; RV64NOZBB-NEXT:    srli a1, a1, 49
+; RV64NOZBB-NEXT:    or a0, a0, a1
+; RV64NOZBB-NEXT:    slli a1, a0, 48
+; RV64NOZBB-NEXT:    srli a1, a1, 50
+; RV64NOZBB-NEXT:    or a0, a0, a1
+; RV64NOZBB-NEXT:    slli a1, a0, 48
+; RV64NOZBB-NEXT:    srli a1, a1, 52
+; RV64NOZBB-NEXT:    or a0, a0, a1
+; RV64NOZBB-NEXT:    slli a1, a0, 48
+; RV64NOZBB-NEXT:    srli a1, a1, 56
+; RV64NOZBB-NEXT:    or a0, a0, a1
+; RV64NOZBB-NEXT:    not a0, a0
+; RV64NOZBB-NEXT:    srli a1, a0, 1
+; RV64NOZBB-NEXT:    lui a2, 5
+; RV64NOZBB-NEXT:    addiw a2, a2, 1365
+; RV64NOZBB-NEXT:    and a1, a1, a2
+; RV64NOZBB-NEXT:    sub a0, a0, a1
+; RV64NOZBB-NEXT:    lui a1, 3
+; RV64NOZBB-NEXT:    addiw a1, a1, 819
+; RV64NOZBB-NEXT:    and a2, a0, a1
+; RV64NOZBB-NEXT:    srli a0, a0, 2
+; RV64NOZBB-NEXT:    and a0, a0, a1
+; RV64NOZBB-NEXT:    add a0, a2, a0
+; RV64NOZBB-NEXT:    srli a1, a0, 4
+; RV64NOZBB-NEXT:    add a0, a0, a1
+; RV64NOZBB-NEXT:    lui a1, 1
+; RV64NOZBB-NEXT:    addiw a1, a1, -241
+; RV64NOZBB-NEXT:    and a0, a0, a1
+; RV64NOZBB-NEXT:    slliw a1, a0, 8
+; RV64NOZBB-NEXT:    addw a0, a1, a0
+; RV64NOZBB-NEXT:    slli a0, a0, 51
+; RV64NOZBB-NEXT:    srli a0, a0, 59
+; RV64NOZBB-NEXT:    ret
+; RV64NOZBB-NEXT:  .LBB9_2:
+; RV64NOZBB-NEXT:    li a0, 16
+; RV64NOZBB-NEXT:    ret
 ;
 ; RV32ZBB-LABEL: test_ctlz_i16:
 ; RV32ZBB:       # %bb.0:
@@ -980,6 +1260,87 @@ define i32 @test_ctlz_i32(i32 %a) nounwind {
 ; RV64I-NEXT:    addi sp, sp, 16
 ; RV64I-NEXT:    ret
 ;
+; RV32M-LABEL: test_ctlz_i32:
+; RV32M:       # %bb.0:
+; RV32M-NEXT:    beqz a0, .LBB10_2
+; RV32M-NEXT:  # %bb.1: # %cond.false
+; RV32M-NEXT:    srli a1, a0, 1
+; RV32M-NEXT:    or a0, a0, a1
+; RV32M-NEXT:    srli a1, a0, 2
+; RV32M-NEXT:    or a0, a0, a1
+; RV32M-NEXT:    srli a1, a0, 4
+; RV32M-NEXT:    or a0, a0, a1
+; RV32M-NEXT:    srli a1, a0, 8
+; RV32M-NEXT:    or a0, a0, a1
+; RV32M-NEXT:    srli a1, a0, 16
+; RV32M-NEXT:    or a0, a0, a1
+; RV32M-NEXT:    not a0, a0
+; RV32M-NEXT:    srli a1, a0, 1
+; RV32M-NEXT:    lui a2, 349525
+; RV32M-NEXT:    addi a2, a2, 1365
+; RV32M-NEXT:    and a1, a1, a2
+; RV32M-NEXT:    sub a0, a0, a1
+; RV32M-NEXT:    lui a1, 209715
+; RV32M-NEXT:    addi a1, a1, 819
+; RV32M-NEXT:    and a2, a0, a1
+; RV32M-NEXT:    srli a0, a0, 2
+; RV32M-NEXT:    and a0, a0, a1
+; RV32M-NEXT:    add a0, a2, a0
+; RV32M-NEXT:    srli a1, a0, 4
+; RV32M-NEXT:    add a0, a0, a1
+; RV32M-NEXT:    lui a1, 61681
+; RV32M-NEXT:    addi a1, a1, -241
+; RV32M-NEXT:    and a0, a0, a1
+; RV32M-NEXT:    lui a1, 4112
+; RV32M-NEXT:    addi a1, a1, 257
+; RV32M-NEXT:    mul a0, a0, a1
+; RV32M-NEXT:    srli a0, a0, 24
+; RV32M-NEXT:    ret
+; RV32M-NEXT:  .LBB10_2:
+; RV32M-NEXT:    li a0, 32
+; RV32M-NEXT:    ret
+;
+; RV64M-LABEL: test_ctlz_i32:
+; RV64M:       # %bb.0:
+; RV64M-NEXT:    sext.w a1, a0
+; RV64M-NEXT:    beqz a1, .LBB10_2
+; RV64M-NEXT:  # %bb.1: # %cond.false
+; RV64M-NEXT:    srliw a1, a0, 1
+; RV64M-NEXT:    or a0, a0, a1
+; RV64M-NEXT:    srliw a1, a0, 2
+; RV64M-NEXT:    or a0, a0, a1
+; RV64M-NEXT:    srliw a1, a0, 4
+; RV64M-NEXT:    or a0, a0, a1
+; RV64M-NEXT:    srliw a1, a0, 8
+; RV64M-NEXT:    or a0, a0, a1
+; RV64M-NEXT:    srliw a1, a0, 16
+; RV64M-NEXT:    or a0, a0, a1
+; RV64M-NEXT:    not a0, a0
+; RV64M-NEXT:    srli a1, a0, 1
+; RV64M-NEXT:    lui a2, 349525
+; RV64M-NEXT:    addiw a2, a2, 1365
+; RV64M-NEXT:    and a1, a1, a2
+; RV64M-NEXT:    subw a0, a0, a1
+; RV64M-NEXT:    lui a1, 209715
+; RV64M-NEXT:    addiw a1, a1, 819
+; RV64M-NEXT:    and a2, a0, a1
+; RV64M-NEXT:    srli a0, a0, 2
+; RV64M-NEXT:    and a0, a0, a1
+; RV64M-NEXT:    add a0, a2, a0
+; RV64M-NEXT:    srli a1, a0, 4
+; RV64M-NEXT:    add a0, a0, a1
+; RV64M-NEXT:    lui a1, 61681
+; RV64M-NEXT:    addiw a1, a1, -241
+; RV64M-NEXT:    and a0, a0, a1
+; RV64M-NEXT:    lui a1, 4112
+; RV64M-NEXT:    addiw a1, a1, 257
+; RV64M-NEXT:    mulw a0, a0, a1
+; RV64M-NEXT:    srliw a0, a0, 24
+; RV64M-NEXT:    ret
+; RV64M-NEXT:  .LBB10_2:
+; RV64M-NEXT:    li a0, 32
+; RV64M-NEXT:    ret
+;
 ; RV32ZBB-LABEL: test_ctlz_i32:
 ; RV32ZBB:       # %bb.0:
 ; RV32ZBB-NEXT:    clz a0, a0
@@ -1129,6 +1490,113 @@ define i64 @test_ctlz_i64(i64 %a) nounwind {
 ; RV64I-NEXT:    addi sp, sp, 16
 ; RV64I-NEXT:    ret
 ;
+; RV32M-LABEL: test_ctlz_i64:
+; RV32M:       # %bb.0:
+; RV32M-NEXT:    lui a2, 349525
+; RV32M-NEXT:    addi a5, a2, 1365
+; RV32M-NEXT:    lui a2, 209715
+; RV32M-NEXT:    addi a4, a2, 819
+; RV32M-NEXT:    lui a2, 61681
+; RV32M-NEXT:    addi a2, a2, -241
+; RV32M-NEXT:    lui a3, 4112
+; RV32M-NEXT:    addi a3, a3, 257
+; RV32M-NEXT:    bnez a1, .LBB11_2
+; RV32M-NEXT:  # %bb.1:
+; RV32M-NEXT:    srli a1, a0, 1
+; RV32M-NEXT:    or a0, a0, a1
+; RV32M-NEXT:    srli a1, a0, 2
+; RV32M-NEXT:    or a0, a0, a1
+; RV32M-NEXT:    srli a1, a0, 4
+; RV32M-NEXT:    or a0, a0, a1
+; RV32M-NEXT:    srli a1, a0, 8
+; RV32M-NEXT:    or a0, a0, a1
+; RV32M-NEXT:    srli a1, a0, 16
+; RV32M-NEXT:    or a0, a0, a1
+; RV32M-NEXT:    not a0, a0
+; RV32M-NEXT:    srli a1, a0, 1
+; RV32M-NEXT:    and a1, a1, a5
+; RV32M-NEXT:    sub a0, a0, a1
+; RV32M-NEXT:    and a1, a0, a4
+; RV32M-NEXT:    srli a0, a0, 2
+; RV32M-NEXT:    and a0, a0, a4
+; RV32M-NEXT:    add a0, a1, a0
+; RV32M-NEXT:    srli a1, a0, 4
+; RV32M-NEXT:    add a0, a0, a1
+; RV32M-NEXT:    and a0, a0, a2
+; RV32M-NEXT:    mul a0, a0, a3
+; RV32M-NEXT:    srli a0, a0, 24
+; RV32M-NEXT:    addi a0, a0, 32
+; RV32M-NEXT:    li a1, 0
+; RV32M-NEXT:    ret
+; RV32M-NEXT:  .LBB11_2:
+; RV32M-NEXT:    srli a0, a1, 1
+; RV32M-NEXT:    or a0, a1, a0
+; RV32M-NEXT:    srli a1, a0, 2
+; RV32M-NEXT:    or a0, a0, a1
+; RV32M-NEXT:    srli a1, a0, 4
+; RV32M-NEXT:    or a0, a0, a1
+; RV32M-NEXT:    srli a1, a0, 8
+; RV32M-NEXT:    or a0, a0, a1
+; RV32M-NEXT:    srli a1, a0, 16
+; RV32M-NEXT:    or a0, a0, a1
+; RV32M-NEXT:    not a0, a0
+; RV32M-NEXT:    srli a1, a0, 1
+; RV32M-NEXT:    and a1, a1, a5
+; RV32M-NEXT:    sub a0, a0, a1
+; RV32M-NEXT:    and a1, a0, a4
+; RV32M-NEXT:    srli a0, a0, 2
+; RV32M-NEXT:    and a0, a0, a4
+; RV32M-NEXT:    add a0, a1, a0
+; RV32M-NEXT:    srli a1, a0, 4
+; RV32M-NEXT:    add a0, a0, a1
+; RV32M-NEXT:    and a0, a0, a2
+; RV32M-NEXT:    mul a0, a0, a3
+; RV32M-NEXT:    srli a0, a0, 24
+; RV32M-NEXT:    li a1, 0
+; RV32M-NEXT:    ret
+;
+; RV64M-LABEL: test_ctlz_i64:
+; RV64M:       # %bb.0:
+; RV64M-NEXT:    beqz a0, .LBB11_2
+; RV64M-NEXT:  # %bb.1: # %cond.false
+; RV64M-NEXT:    srli a1, a0, 1
+; RV64M-NEXT:    or a0, a0, a1
+; RV64M-NEXT:    srli a1, a0, 2
+; RV64M-NEXT:    or a0, a0, a1
+; RV64M-NEXT:    srli a1, a0, 4
+; RV64M-NEXT:    or a0, a0, a1
+; RV64M-NEXT:    srli a1, a0, 8
+; RV64M-NEXT:    or a0, a0, a1
+; RV64M-NEXT:    srli a1, a0, 16
+; RV64M-NEXT:    or a0, a0, a1
+; RV64M-NEXT:    srli a1, a0, 32
+; RV64M-NEXT:    or a0, a0, a1
+; RV64M-NEXT:    not a0, a0
+; RV64M-NEXT:    lui a1, %hi(.LCPI11_0)
+; RV64M-NEXT:    ld a1, %lo(.LCPI11_0)(a1)
+; RV64M-NEXT:    lui a2, %hi(.LCPI11_1)
+; RV64M-NEXT:    ld a2, %lo(.LCPI11_1)(a2)
+; RV64M-NEXT:    srli a3, a0, 1
+; RV64M-NEXT:    and a1, a3, a1
+; RV64M-NEXT:    sub a0, a0, a1
+; RV64M-NEXT:    and a1, a0, a2
+; RV64M-NEXT:    srli a0, a0, 2
+; RV64M-NEXT:    and a0, a0, a2
+; RV64M-NEXT:    add a0, a1, a0
+; RV64M-NEXT:    lui a1, %hi(.LCPI11_2)
+; RV64M-NEXT:    ld a1, %lo(.LCPI11_2)(a1)
+; RV64M-NEXT:    lui a2, %hi(.LCPI11_3)
+; RV64M-NEXT:    ld a2, %lo(.LCPI11_3)(a2)
+; RV64M-NEXT:    srli a3, a0, 4
+; RV64M-NEXT:    add a0, a0, a3
+; RV64M-NEXT:    and a0, a0, a1
+; RV64M-NEXT:    mul a0, a0, a2
+; RV64M-NEXT:    srli a0, a0, 56
+; RV64M-NEXT:    ret
+; RV64M-NEXT:  .LBB11_2:
+; RV64M-NEXT:    li a0, 64
+; RV64M-NEXT:    ret
+;
 ; RV32ZBB-LABEL: test_ctlz_i64:
 ; RV32ZBB:       # %bb.0:
 ; RV32ZBB-NEXT:    bnez a1, .LBB11_2
@@ -1151,53 +1619,53 @@ define i64 @test_ctlz_i64(i64 %a) nounwind {
 }
 
 define i8 @test_ctlz_i8_zero_undef(i8 %a) nounwind {
-; RV32I-LABEL: test_ctlz_i8_zero_undef:
-; RV32I:       # %bb.0:
-; RV32I-NEXT:    slli a1, a0, 24
-; RV32I-NEXT:    srli a1, a1, 25
-; RV32I-NEXT:    or a0, a0, a1
-; RV32I-NEXT:    slli a1, a0, 24
-; RV32I-NEXT:    srli a1, a1, 26
-; RV32I-NEXT:    or a0, a0, a1
-; RV32I-NEXT:    slli a1, a0, 24
-; RV32I-NEXT:    srli a1, a1, 28
-; RV32I-NEXT:    or a0, a0, a1
-; RV32I-NEXT:    not a0, a0
-; RV32I-NEXT:    srli a1, a0, 1
-; RV32I-NEXT:    andi a1, a1, 85
-; RV32I-NEXT:    sub a0, a0, a1
-; RV32I-NEXT:    andi a1, a0, 51
-; RV32I-NEXT:    srli a0, a0, 2
-; RV32I-NEXT:    andi a0, a0, 51
-; RV32I-NEXT:    add a0, a1, a0
-; RV32I-NEXT:    srli a1, a0, 4
-; RV32I-NEXT:    add a0, a0, a1
-; RV32I-NEXT:    andi a0, a0, 15
-; RV32I-NEXT:    ret
-;
-; RV64I-LABEL: test_ctlz_i8_zero_undef:
-; RV64I:       # %bb.0:
-; RV64I-NEXT:    slli a1, a0, 56
-; RV64I-NEXT:    srli a1, a1, 57
-; RV64I-NEXT:    or a0, a0, a1
-; RV64I-NEXT:    slli a1, a0, 56
-; RV64I-NEXT:    srli a1, a1, 58
-; RV64I-NEXT:    or a0, a0, a1
-; RV64I-NEXT:    slli a1, a0, 56
-; RV64I-NEXT:    srli a1, a1, 60
-; RV64I-NEXT:    or a0, a0, a1
-; RV64I-NEXT:    not a0, a0
-; RV64I-NEXT:    srli a1, a0, 1
-; RV64I-NEXT:    andi a1, a1, 85
-; RV64I-NEXT:    sub a0, a0, a1
-; RV64I-NEXT:    andi a1, a0, 51
-; RV64I-NEXT:    srli a0, a0, 2
-; RV64I-NEXT:    andi a0, a0, 51
-; RV64I-NEXT:    add a0, a1, a0
-; RV64I-NEXT:    srli a1, a0, 4
-; RV64I-NEXT:    addw a0, a0, a1
-; RV64I-NEXT:    andi a0, a0, 15
-; RV64I-NEXT:    ret
+; RV32_NOZBB-LABEL: test_ctlz_i8_zero_undef:
+; RV32_NOZBB:       # %bb.0:
+; RV32_NOZBB-NEXT:    slli a1, a0, 24
+; RV32_NOZBB-NEXT:    srli a1, a1, 25
+; RV32_NOZBB-NEXT:    or a0, a0, a1
+; RV32_NOZBB-NEXT:    slli a1, a0, 24
+; RV32_NOZBB-NEXT:    srli a1, a1, 26
+; RV32_NOZBB-NEXT:    or a0, a0, a1
+; RV32_NOZBB-NEXT:    slli a1, a0, 24
+; RV32_NOZBB-NEXT:    srli a1, a1, 28
+; RV32_NOZBB-NEXT:    or a0, a0, a1
+; RV32_NOZBB-NEXT:    not a0, a0
+; RV32_NOZBB-NEXT:    srli a1, a0, 1
+; RV32_NOZBB-NEXT:    andi a1, a1, 85
+; RV32_NOZBB-NEXT:    sub a0, a0, a1
+; RV32_NOZBB-NEXT:    andi a1, a0, 51
+; RV32_NOZBB-NEXT:    srli a0, a0, 2
+; RV32_NOZBB-NEXT:    andi a0, a0, 51
+; RV32_NOZBB-NEXT:    add a0, a1, a0
+; RV32_NOZBB-NEXT:    srli a1, a0, 4
+; RV32_NOZBB-NEXT:    add a0, a0, a1
+; RV32_NOZBB-NEXT:    andi a0, a0, 15
+; RV32_NOZBB-NEXT:    ret
+;
+; RV64NOZBB-LABEL: test_ctlz_i8_zero_undef:
+; RV64NOZBB:       # %bb.0:
+; RV64NOZBB-NEXT:    slli a1, a0, 56
+; RV64NOZBB-NEXT:    srli a1, a1, 57
+; RV64NOZBB-NEXT:    or a0, a0, a1
+; RV64NOZBB-NEXT:    slli a1, a0, 56
+; RV64NOZBB-NEXT:    srli a1, a1, 58
+; RV64NOZBB-NEXT:    or a0, a0, a1
+; RV64NOZBB-NEXT:    slli a1, a0, 56
+; RV64NOZBB-NEXT:    srli a1, a1, 60
+; RV64NOZBB-NEXT:    or a0, a0, a1
+; RV64NOZBB-NEXT:    not a0, a0
+; RV64NOZBB-NEXT:    srli a1, a0, 1
+; RV64NOZBB-NEXT:    andi a1, a1, 85
+; RV64NOZBB-NEXT:    sub a0, a0, a1
+; RV64NOZBB-NEXT:    andi a1, a0, 51
+; RV64NOZBB-NEXT:    srli a0, a0, 2
+; RV64NOZBB-NEXT:    andi a0, a0, 51
+; RV64NOZBB-NEXT:    add a0, a1, a0
+; RV64NOZBB-NEXT:    srli a1, a0, 4
+; RV64NOZBB-NEXT:    addw a0, a0, a1
+; RV64NOZBB-NEXT:    andi a0, a0, 15
+; RV64NOZBB-NEXT:    ret
 ;
 ; RV32ZBB-LABEL: test_ctlz_i8_zero_undef:
 ; RV32ZBB:       # %bb.0:
@@ -1217,79 +1685,79 @@ define i8 @test_ctlz_i8_zero_undef(i8 %a) nounwind {
 }
 
 define i16 @test_ctlz_i16_zero_undef(i16 %a) nounwind {
-; RV32I-LABEL: test_ctlz_i16_zero_undef:
-; RV32I:       # %bb.0:
-; RV32I-NEXT:    slli a1, a0, 16
-; RV32I-NEXT:    srli a1, a1, 17
-; RV32I-NEXT:    or a0, a0, a1
-; RV32I-NEXT:    slli a1, a0, 16
-; RV32I-NEXT:    srli a1, a1, 18
-; RV32I-NEXT:    or a0, a0, a1
-; RV32I-NEXT:    slli a1, a0, 16
-; RV32I-NEXT:    srli a1, a1, 20
-; RV32I-NEXT:    or a0, a0, a1
-; RV32I-NEXT:    slli a1, a0, 16
-; RV32I-NEXT:    srli a1, a1, 24
-; RV32I-NEXT:    or a0, a0, a1
-; RV32I-NEXT:    not a0, a0
-; RV32I-NEXT:    srli a1, a0, 1
-; RV32I-NEXT:    lui a2, 5
-; RV32I-NEXT:    addi a2, a2, 1365
-; RV32I-NEXT:    and a1, a1, a2
-; RV32I-NEXT:    sub a0, a0, a1
-; RV32I-NEXT:    lui a1, 3
-; RV32I-NEXT:    addi a1, a1, 819
-; RV32I-NEXT:    and a2, a0, a1
-; RV32I-NEXT:    srli a0, a0, 2
-; RV32I-NEXT:    and a0, a0, a1
-; RV32I-NEXT:    add a0, a2, a0
-; RV32I-NEXT:    srli a1, a0, 4
-; RV32I-NEXT:    add a0, a0, a1
-; RV32I-NEXT:    lui a1, 1
-; RV32I-NEXT:    addi a1, a1, -241
-; RV32I-NEXT:    and a0, a0, a1
-; RV32I-NEXT:    slli a1, a0, 8
-; RV32I-NEXT:    add a0, a1, a0
-; RV32I-NEXT:    slli a0, a0, 19
-; RV32I-NEXT:    srli a0, a0, 27
-; RV32I-NEXT:    ret
-;
-; RV64I-LABEL: test_ctlz_i16_zero_undef:
-; RV64I:       # %bb.0:
-; RV64I-NEXT:    slli a1, a0, 48
-; RV64I-NEXT:    srli a1, a1, 49
-; RV64I-NEXT:    or a0, a0, a1
-; RV64I-NEXT:    slli a1, a0, 48
-; RV64I-NEXT:    srli a1, a1, 50
-; RV64I-NEXT:    or a0, a0, a1
-; RV64I-NEXT:    slli a1, a0, 48
-; RV64I-NEXT:    srli a1, a1, 52
-; RV64I-NEXT:    or a0, a0, a1
-; RV64I-NEXT:    slli a1, a0, 48
-; RV64I-NEXT:    srli a1, a1, 56
-; RV64I-NEXT:    or a0, a0, a1
-; RV64I-NEXT:    not a0, a0
-; RV64I-NEXT:    srli a1, a0, 1
-; RV64I-NEXT:    lui a2, 5
-; RV64I-NEXT:    addiw a2, a2, 1365
-; RV64I-NEXT:    and a1, a1, a2
-; RV64I-NEXT:    sub a0, a0, a1
-; RV64I-NEXT:    lui a1, 3
-; RV64I-NEXT:    addiw a1, a1, 819
-; RV64I-NEXT:    and a2, a0, a1
-; RV64I-NEXT:    srli a0, a0, 2
-; RV64I-NEXT:    and a0, a0, a1
-; RV64I-NEXT:    add a0, a2, a0
-; RV64I-NEXT:    srli a1, a0, 4
-; RV64I-NEXT:    add a0, a0, a1
-; RV64I-NEXT:    lui a1, 1
-; RV64I-NEXT:    addiw a1, a1, -241
-; RV64I-NEXT:    and a0, a0, a1
-; RV64I-NEXT:    slliw a1, a0, 8
-; RV64I-NEXT:    addw a0, a1, a0
-; RV64I-NEXT:    slli a0, a0, 51
-; RV64I-NEXT:    srli a0, a0, 59
-; RV64I-NEXT:    ret
+; RV32_NOZBB-LABEL: test_ctlz_i16_zero_undef:
+; RV32_NOZBB:       # %bb.0:
+; RV32_NOZBB-NEXT:    slli a1, a0, 16
+; RV32_NOZBB-NEXT:    srli a1, a1, 17
+; RV32_NOZBB-NEXT:    or a0, a0, a1
+; RV32_NOZBB-NEXT:    slli a1, a0, 16
+; RV32_NOZBB-NEXT:    srli a1, a1, 18
+; RV32_NOZBB-NEXT:    or a0, a0, a1
+; RV32_NOZBB-NEXT:    slli a1, a0, 16
+; RV32_NOZBB-NEXT:    srli a1, a1, 20
+; RV32_NOZBB-NEXT:    or a0, a0, a1
+; RV32_NOZBB-NEXT:    slli a1, a0, 16
+; RV32_NOZBB-NEXT:    srli a1, a1, 24
+; RV32_NOZBB-NEXT:    or a0, a0, a1
+; RV32_NOZBB-NEXT:    not a0, a0
+; RV32_NOZBB-NEXT:    srli a1, a0, 1
+; RV32_NOZBB-NEXT:    lui a2, 5
+; RV32_NOZBB-NEXT:    addi a2, a2, 1365
+; RV32_NOZBB-NEXT:    and a1, a1, a2
+; RV32_NOZBB-NEXT:    sub a0, a0, a1
+; RV32_NOZBB-NEXT:    lui a1, 3
+; RV32_NOZBB-NEXT:    addi a1, a1, 819
+; RV32_NOZBB-NEXT:    and a2, a0, a1
+; RV32_NOZBB-NEXT:    srli a0, a0, 2
+; RV32_NOZBB-NEXT:    and a0, a0, a1
+; RV32_NOZBB-NEXT:    add a0, a2, a0
+; RV32_NOZBB-NEXT:    srli a1, a0, 4
+; RV32_NOZBB-NEXT:    add a0, a0, a1
+; RV32_NOZBB-NEXT:    lui a1, 1
+; RV32_NOZBB-NEXT:    addi a1, a1, -241
+; RV32_NOZBB-NEXT:    and a0, a0, a1
+; RV32_NOZBB-NEXT:    slli a1, a0, 8
+; RV32_NOZBB-NEXT:    add a0, a1, a0
+; RV32_NOZBB-NEXT:    slli a0, a0, 19
+; RV32_NOZBB-NEXT:    srli a0, a0, 27
+; RV32_NOZBB-NEXT:    ret
+;
+; RV64NOZBB-LABEL: test_ctlz_i16_zero_undef:
+; RV64NOZBB:       # %bb.0:
+; RV64NOZBB-NEXT:    slli a1, a0, 48
+; RV64NOZBB-NEXT:    srli a1, a1, 49
+; RV64NOZBB-NEXT:    or a0, a0, a1
+; RV64NOZBB-NEXT:    slli a1, a0, 48
+; RV64NOZBB-NEXT:    srli a1, a1, 50
+; RV64NOZBB-NEXT:    or a0, a0, a1
+; RV64NOZBB-NEXT:    slli a1, a0, 48
+; RV64NOZBB-NEXT:    srli a1, a1, 52
+; RV64NOZBB-NEXT:    or a0, a0, a1
+; RV64NOZBB-NEXT:    slli a1, a0, 48
+; RV64NOZBB-NEXT:    srli a1, a1, 56
+; RV64NOZBB-NEXT:    or a0, a0, a1
+; RV64NOZBB-NEXT:    not a0, a0
+; RV64NOZBB-NEXT:    srli a1, a0, 1
+; RV64NOZBB-NEXT:    lui a2, 5
+; RV64NOZBB-NEXT:    addiw a2, a2, 1365
+; RV64NOZBB-NEXT:    and a1, a1, a2
+; RV64NOZBB-NEXT:    sub a0, a0, a1
+; RV64NOZBB-NEXT:    lui a1, 3
+; RV64NOZBB-NEXT:    addiw a1, a1, 819
+; RV64NOZBB-NEXT:    and a2, a0, a1
+; RV64NOZBB-NEXT:    srli a0, a0, 2
+; RV64NOZBB-NEXT:    and a0, a0, a1
+; RV64NOZBB-NEXT:    add a0, a2, a0
+; RV64NOZBB-NEXT:    srli a1, a0, 4
+; RV64NOZBB-NEXT:    add a0, a0, a1
+; RV64NOZBB-NEXT:    lui a1, 1
+; RV64NOZBB-NEXT:    addiw a1, a1, -241
+; RV64NOZBB-NEXT:    and a0, a0, a1
+; RV64NOZBB-NEXT:    slliw a1, a0, 8
+; RV64NOZBB-NEXT:    addw a0, a1, a0
+; RV64NOZBB-NEXT:    slli a0, a0, 51
+; RV64NOZBB-NEXT:    srli a0, a0, 59
+; RV64NOZBB-NEXT:    ret
 ;
 ; RV32ZBB-LABEL: test_ctlz_i16_zero_undef:
 ; RV32ZBB:       # %bb.0:
@@ -1387,6 +1855,76 @@ define i32 @test_ctlz_i32_zero_undef(i32 %a) nounwind {
 ; RV64I-NEXT:    addi sp, sp, 16
 ; RV64I-NEXT:    ret
 ;
+; RV32M-LABEL: test_ctlz_i32_zero_undef:
+; RV32M:       # %bb.0:
+; RV32M-NEXT:    srli a1, a0, 1
+; RV32M-NEXT:    or a0, a0, a1
+; RV32M-NEXT:    srli a1, a0, 2
+; RV32M-NEXT:    or a0, a0, a1
+; RV32M-NEXT:    srli a1, a0, 4
+; RV32M-NEXT:    or a0, a0, a1
+; RV32M-NEXT:    srli a1, a0, 8
+; RV32M-NEXT:    or a0, a0, a1
+; RV32M-NEXT:    srli a1, a0, 16
+; RV32M-NEXT:    or a0, a0, a1
+; RV32M-NEXT:    not a0, a0
+; RV32M-NEXT:    srli a1, a0, 1
+; RV32M-NEXT:    lui a2, 349525
+; RV32M-NEXT:    addi a2, a2, 1365
+; RV32M-NEXT:    and a1, a1, a2
+; RV32M-NEXT:    sub a0, a0, a1
+; RV32M-NEXT:    lui a1, 209715
+; RV32M-NEXT:    addi a1, a1, 819
+; RV32M-NEXT:    and a2, a0, a1
+; RV32M-NEXT:    srli a0, a0, 2
+; RV32M-NEXT:    and a0, a0, a1
+; RV32M-NEXT:    add a0, a2, a0
+; RV32M-NEXT:    srli a1, a0, 4
+; RV32M-NEXT:    add a0, a0, a1
+; RV32M-NEXT:    lui a1, 61681
+; RV32M-NEXT:    addi a1, a1, -241
+; RV32M-NEXT:    and a0, a0, a1
+; RV32M-NEXT:    lui a1, 4112
+; RV32M-NEXT:    addi a1, a1, 257
+; RV32M-NEXT:    mul a0, a0, a1
+; RV32M-NEXT:    srli a0, a0, 24
+; RV32M-NEXT:    ret
+;
+; RV64M-LABEL: test_ctlz_i32_zero_undef:
+; RV64M:       # %bb.0:
+; RV64M-NEXT:    srliw a1, a0, 1
+; RV64M-NEXT:    or a0, a0, a1
+; RV64M-NEXT:    srliw a1, a0, 2
+; RV64M-NEXT:    or a0, a0, a1
+; RV64M-NEXT:    srliw a1, a0, 4
+; RV64M-NEXT:    or a0, a0, a1
+; RV64M-NEXT:    srliw a1, a0, 8
+; RV64M-NEXT:    or a0, a0, a1
+; RV64M-NEXT:    srliw a1, a0, 16
+; RV64M-NEXT:    or a0, a0, a1
+; RV64M-NEXT:    not a0, a0
+; RV64M-NEXT:    srli a1, a0, 1
+; RV64M-NEXT:    lui a2, 349525
+; RV64M-NEXT:    addiw a2, a2, 1365
+; RV64M-NEXT:    and a1, a1, a2
+; RV64M-NEXT:    subw a0, a0, a1
+; RV64M-NEXT:    lui a1, 209715
+; RV64M-NEXT:    addiw a1, a1, 819
+; RV64M-NEXT:    and a2, a0, a1
+; RV64M-NEXT:    srli a0, a0, 2
+; RV64M-NEXT:    and a0, a0, a1
+; RV64M-NEXT:    add a0, a2, a0
+; RV64M-NEXT:    srli a1, a0, 4
+; RV64M-NEXT:    add a0, a0, a1
+; RV64M-NEXT:    lui a1, 61681
+; RV64M-NEXT:    addiw a1, a1, -241
+; RV64M-NEXT:    and a0, a0, a1
+; RV64M-NEXT:    lui a1, 4112
+; RV64M-NEXT:    addiw a1, a1, 257
+; RV64M-NEXT:    mulw a0, a0, a1
+; RV64M-NEXT:    srliw a0, a0, 24
+; RV64M-NEXT:    ret
+;
 ; RV32ZBB-LABEL: test_ctlz_i32_zero_undef:
 ; RV32ZBB:       # %bb.0:
 ; RV32ZBB-NEXT:    clz a0, a0
@@ -1530,6 +2068,108 @@ define i64 @test_ctlz_i64_zero_undef(i64 %a) nounwind {
 ; RV64I-NEXT:    addi sp, sp, 16
 ; RV64I-NEXT:    ret
 ;
+; RV32M-LABEL: test_ctlz_i64_zero_undef:
+; RV32M:       # %bb.0:
+; RV32M-NEXT:    lui a2, 349525
+; RV32M-NEXT:    addi a5, a2, 1365
+; RV32M-NEXT:    lui a2, 209715
+; RV32M-NEXT:    addi a4, a2, 819
+; RV32M-NEXT:    lui a2, 61681
+; RV32M-NEXT:    addi a2, a2, -241
+; RV32M-NEXT:    lui a3, 4112
+; RV32M-NEXT:    addi a3, a3, 257
+; RV32M-NEXT:    bnez a1, .LBB15_2
+; RV32M-NEXT:  # %bb.1:
+; RV32M-NEXT:    srli a1, a0, 1
+; RV32M-NEXT:    or a0, a0, a1
+; RV32M-NEXT:    srli a1, a0, 2
+; RV32M-NEXT:    or a0, a0, a1
+; RV32M-NEXT:    srli a1, a0, 4
+; RV32M-NEXT:    or a0, a0, a1
+; RV32M-NEXT:    srli a1, a0, 8
+; RV32M-NEXT:    or a0, a0, a1
+; RV32M-NEXT:    srli a1, a0, 16
+; RV32M-NEXT:    or a0, a0, a1
+; RV32M-NEXT:    not a0, a0
+; RV32M-NEXT:    srli a1, a0, 1
+; RV32M-NEXT:    and a1, a1, a5
+; RV32M-NEXT:    sub a0, a0, a1
+; RV32M-NEXT:    and a1, a0, a4
+; RV32M-NEXT:    srli a0, a0, 2
+; RV32M-NEXT:    and a0, a0, a4
+; RV32M-NEXT:    add a0, a1, a0
+; RV32M-NEXT:    srli a1, a0, 4
+; RV32M-NEXT:    add a0, a0, a1
+; RV32M-NEXT:    and a0, a0, a2
+; RV32M-NEXT:    mul a0, a0, a3
+; RV32M-NEXT:    srli a0, a0, 24
+; RV32M-NEXT:    addi a0, a0, 32
+; RV32M-NEXT:    li a1, 0
+; RV32M-NEXT:    ret
+; RV32M-NEXT:  .LBB15_2:
+; RV32M-NEXT:    srli a0, a1, 1
+; RV32M-NEXT:    or a0, a1, a0
+; RV32M-NEXT:    srli a1, a0, 2
+; RV32M-NEXT:    or a0, a0, a1
+; RV32M-NEXT:    srli a1, a0, 4
+; RV32M-NEXT:    or a0, a0, a1
+; RV32M-NEXT:    srli a1, a0, 8
+; RV32M-NEXT:    or a0, a0, a1
+; RV32M-NEXT:    srli a1, a0, 16
+; RV32M-NEXT:    or a0, a0, a1
+; RV32M-NEXT:    not a0, a0
+; RV32M-NEXT:    srli a1, a0, 1
+; RV32M-NEXT:    and a1, a1, a5
+; RV32M-NEXT:    sub a0, a0, a1
+; RV32M-NEXT:    and a1, a0, a4
+; RV32M-NEXT:    srli a0, a0, 2
+; RV32M-NEXT:    and a0, a0, a4
+; RV32M-NEXT:    add a0, a1, a0
+; RV32M-NEXT:    srli a1, a0, 4
+; RV32M-NEXT:    add a0, a0, a1
+; RV32M-NEXT:    and a0, a0, a2
+; RV32M-NEXT:    mul a0, a0, a3
+; RV32M-NEXT:    srli a0, a0, 24
+; RV32M-NEXT:    li a1, 0
+; RV32M-NEXT:    ret
+;
+; RV64M-LABEL: test_ctlz_i64_zero_undef:
+; RV64M:       # %bb.0:
+; RV64M-NEXT:    srli a1, a0, 1
+; RV64M-NEXT:    or a0, a0, a1
+; RV64M-NEXT:    srli a1, a0, 2
+; RV64M-NEXT:    or a0, a0, a1
+; RV64M-NEXT:    srli a1, a0, 4
+; RV64M-NEXT:    or a0, a0, a1
+; RV64M-NEXT:    srli a1, a0, 8
+; RV64M-NEXT:    or a0, a0, a1
+; RV64M-NEXT:    srli a1, a0, 16
+; RV64M-NEXT:    or a0, a0, a1
+; RV64M-NEXT:    srli a1, a0, 32
+; RV64M-NEXT:    or a0, a0, a1
+; RV64M-NEXT:    not a0, a0
+; RV64M-NEXT:    lui a1, %hi(.LCPI15_0)
+; RV64M-NEXT:    ld a1, %lo(.LCPI15_0)(a1)
+; RV64M-NEXT:    lui a2, %hi(.LCPI15_1)
+; RV64M-NEXT:    ld a2, %lo(.LCPI15_1)(a2)
+; RV64M-NEXT:    srli a3, a0, 1
+; RV64M-NEXT:    and a1, a3, a1
+; RV64M-NEXT:    sub a0, a0, a1
+; RV64M-NEXT:    and a1, a0, a2
+; RV64M-NEXT:    srli a0, a0, 2
+; RV64M-NEXT:    and a0, a0, a2
+; RV64M-NEXT:    add a0, a1, a0
+; RV64M-NEXT:    lui a1, %hi(.LCPI15_2)
+; RV64M-NEXT:    ld a1, %lo(.LCPI15_2)(a1)
+; RV64M-NEXT:    lui a2, %hi(.LCPI15_3)
+; RV64M-NEXT:    ld a2, %lo(.LCPI15_3)(a2)
+; RV64M-NEXT:    srli a3, a0, 4
+; RV64M-NEXT:    add a0, a0, a3
+; RV64M-NEXT:    and a0, a0, a1
+; RV64M-NEXT:    mul a0, a0, a2
+; RV64M-NEXT:    srli a0, a0, 56
+; RV64M-NEXT:    ret
+;
 ; RV32ZBB-LABEL: test_ctlz_i64_zero_undef:
 ; RV32ZBB:       # %bb.0:
 ; RV32ZBB-NEXT:    bnez a1, .LBB15_2
@@ -1552,33 +2192,33 @@ define i64 @test_ctlz_i64_zero_undef(i64 %a) nounwind {
 }
 
 define i8 @test_ctpop_i8(i8 %a) nounwind {
-; RV32I-LABEL: test_ctpop_i8:
-; RV32I:       # %bb.0:
-; RV32I-NEXT:    srli a1, a0, 1
-; RV32I-NEXT:    andi a1, a1, 85
-; RV32I-NEXT:    sub a0, a0, a1
-; RV32I-NEXT:    andi a1, a0, 51
-; RV32I-NEXT:    srli a0, a0, 2
-; RV32I-NEXT:    andi a0, a0, 51
-; RV32I-NEXT:    add a0, a1, a0
-; RV32I-NEXT:    srli a1, a0, 4
-; RV32I-NEXT:    add a0, a0, a1
-; RV32I-NEXT:    andi a0, a0, 15
-; RV32I-NEXT:    ret
-;
-; RV64I-LABEL: test_ctpop_i8:
-; RV64I:       # %bb.0:
-; RV64I-NEXT:    srli a1, a0, 1
-; RV64I-NEXT:    andi a1, a1, 85
-; RV64I-NEXT:    sub a0, a0, a1
-; RV64I-NEXT:    andi a1, a0, 51
-; RV64I-NEXT:    srli a0, a0, 2
-; RV64I-NEXT:    andi a0, a0, 51
-; RV64I-NEXT:    add a0, a1, a0
-; RV64I-NEXT:    srli a1, a0, 4
-; RV64I-NEXT:    addw a0, a0, a1
-; RV64I-NEXT:    andi a0, a0, 15
-; RV64I-NEXT:    ret
+; RV32_NOZBB-LABEL: test_ctpop_i8:
+; RV32_NOZBB:       # %bb.0:
+; RV32_NOZBB-NEXT:    srli a1, a0, 1
+; RV32_NOZBB-NEXT:    andi a1, a1, 85
+; RV32_NOZBB-NEXT:    sub a0, a0, a1
+; RV32_NOZBB-NEXT:    andi a1, a0, 51
+; RV32_NOZBB-NEXT:    srli a0, a0, 2
+; RV32_NOZBB-NEXT:    andi a0, a0, 51
+; RV32_NOZBB-NEXT:    add a0, a1, a0
+; RV32_NOZBB-NEXT:    srli a1, a0, 4
+; RV32_NOZBB-NEXT:    add a0, a0, a1
+; RV32_NOZBB-NEXT:    andi a0, a0, 15
+; RV32_NOZBB-NEXT:    ret
+;
+; RV64NOZBB-LABEL: test_ctpop_i8:
+; RV64NOZBB:       # %bb.0:
+; RV64NOZBB-NEXT:    srli a1, a0, 1
+; RV64NOZBB-NEXT:    andi a1, a1, 85
+; RV64NOZBB-NEXT:    sub a0, a0, a1
+; RV64NOZBB-NEXT:    andi a1, a0, 51
+; RV64NOZBB-NEXT:    srli a0, a0, 2
+; RV64NOZBB-NEXT:    andi a0, a0, 51
+; RV64NOZBB-NEXT:    add a0, a1, a0
+; RV64NOZBB-NEXT:    srli a1, a0, 4
+; RV64NOZBB-NEXT:    addw a0, a0, a1
+; RV64NOZBB-NEXT:    andi a0, a0, 15
+; RV64NOZBB-NEXT:    ret
 ;
 ; RV32ZBB-LABEL: test_ctpop_i8:
 ; RV32ZBB:       # %bb.0:
@@ -1596,53 +2236,53 @@ define i8 @test_ctpop_i8(i8 %a) nounwind {
 }
 
 define i16 @test_ctpop_i16(i16 %a) nounwind {
-; RV32I-LABEL: test_ctpop_i16:
-; RV32I:       # %bb.0:
-; RV32I-NEXT:    srli a1, a0, 1
-; RV32I-NEXT:    lui a2, 5
-; RV32I-NEXT:    addi a2, a2, 1365
-; RV32I-NEXT:    and a1, a1, a2
-; RV32I-NEXT:    sub a0, a0, a1
-; RV32I-NEXT:    lui a1, 3
-; RV32I-NEXT:    addi a1, a1, 819
-; RV32I-NEXT:    and a2, a0, a1
-; RV32I-NEXT:    srli a0, a0, 2
-; RV32I-NEXT:    and a0, a0, a1
-; RV32I-NEXT:    add a0, a2, a0
-; RV32I-NEXT:    srli a1, a0, 4
-; RV32I-NEXT:    add a0, a0, a1
-; RV32I-NEXT:    lui a1, 1
-; RV32I-NEXT:    addi a1, a1, -241
-; RV32I-NEXT:    and a0, a0, a1
-; RV32I-NEXT:    slli a1, a0, 8
-; RV32I-NEXT:    add a0, a1, a0
-; RV32I-NEXT:    slli a0, a0, 19
-; RV32I-NEXT:    srli a0, a0, 27
-; RV32I-NEXT:    ret
-;
-; RV64I-LABEL: test_ctpop_i16:
-; RV64I:       # %bb.0:
-; RV64I-NEXT:    srli a1, a0, 1
-; RV64I-NEXT:    lui a2, 5
-; RV64I-NEXT:    addiw a2, a2, 1365
-; RV64I-NEXT:    and a1, a1, a2
-; RV64I-NEXT:    sub a0, a0, a1
-; RV64I-NEXT:    lui a1, 3
-; RV64I-NEXT:    addiw a1, a1, 819
-; RV64I-NEXT:    and a2, a0, a1
-; RV64I-NEXT:    srli a0, a0, 2
-; RV64I-NEXT:    and a0, a0, a1
-; RV64I-NEXT:    add a0, a2, a0
-; RV64I-NEXT:    srli a1, a0, 4
-; RV64I-NEXT:    add a0, a0, a1
-; RV64I-NEXT:    lui a1, 1
-; RV64I-NEXT:    addiw a1, a1, -241
-; RV64I-NEXT:    and a0, a0, a1
-; RV64I-NEXT:    slliw a1, a0, 8
-; RV64I-NEXT:    addw a0, a1, a0
-; RV64I-NEXT:    slli a0, a0, 51
-; RV64I-NEXT:    srli a0, a0, 59
-; RV64I-NEXT:    ret
+; RV32_NOZBB-LABEL: test_ctpop_i16:
+; RV32_NOZBB:       # %bb.0:
+; RV32_NOZBB-NEXT:    srli a1, a0, 1
+; RV32_NOZBB-NEXT:    lui a2, 5
+; RV32_NOZBB-NEXT:    addi a2, a2, 1365
+; RV32_NOZBB-NEXT:    and a1, a1, a2
+; RV32_NOZBB-NEXT:    sub a0, a0, a1
+; RV32_NOZBB-NEXT:    lui a1, 3
+; RV32_NOZBB-NEXT:    addi a1, a1, 819
+; RV32_NOZBB-NEXT:    and a2, a0, a1
+; RV32_NOZBB-NEXT:    srli a0, a0, 2
+; RV32_NOZBB-NEXT:    and a0, a0, a1
+; RV32_NOZBB-NEXT:    add a0, a2, a0
+; RV32_NOZBB-NEXT:    srli a1, a0, 4
+; RV32_NOZBB-NEXT:    add a0, a0, a1
+; RV32_NOZBB-NEXT:    lui a1, 1
+; RV32_NOZBB-NEXT:    addi a1, a1, -241
+; RV32_NOZBB-NEXT:    and a0, a0, a1
+; RV32_NOZBB-NEXT:    slli a1, a0, 8
+; RV32_NOZBB-NEXT:    add a0, a1, a0
+; RV32_NOZBB-NEXT:    slli a0, a0, 19
+; RV32_NOZBB-NEXT:    srli a0, a0, 27
+; RV32_NOZBB-NEXT:    ret
+;
+; RV64NOZBB-LABEL: test_ctpop_i16:
+; RV64NOZBB:       # %bb.0:
+; RV64NOZBB-NEXT:    srli a1, a0, 1
+; RV64NOZBB-NEXT:    lui a2, 5
+; RV64NOZBB-NEXT:    addiw a2, a2, 1365
+; RV64NOZBB-NEXT:    and a1, a1, a2
+; RV64NOZBB-NEXT:    sub a0, a0, a1
+; RV64NOZBB-NEXT:    lui a1, 3
+; RV64NOZBB-NEXT:    addiw a1, a1, 819
+; RV64NOZBB-NEXT:    and a2, a0, a1
+; RV64NOZBB-NEXT:    srli a0, a0, 2
+; RV64NOZBB-NEXT:    and a0, a0, a1
+; RV64NOZBB-NEXT:    add a0, a2, a0
+; RV64NOZBB-NEXT:    srli a1, a0, 4
+; RV64NOZBB-NEXT:    add a0, a0, a1
+; RV64NOZBB-NEXT:    lui a1, 1
+; RV64NOZBB-NEXT:    addiw a1, a1, -241
+; RV64NOZBB-NEXT:    and a0, a0, a1
+; RV64NOZBB-NEXT:    slliw a1, a0, 8
+; RV64NOZBB-NEXT:    addw a0, a1, a0
+; RV64NOZBB-NEXT:    slli a0, a0, 51
+; RV64NOZBB-NEXT:    srli a0, a0, 59
+; RV64NOZBB-NEXT:    ret
 ;
 ; RV32ZBB-LABEL: test_ctpop_i16:
 ; RV32ZBB:       # %bb.0:
@@ -1716,6 +2356,54 @@ define i32 @test_ctpop_i32(i32 %a) nounwind {
 ; RV64I-NEXT:    addi sp, sp, 16
 ; RV64I-NEXT:    ret
 ;
+; RV32M-LABEL: test_ctpop_i32:
+; RV32M:       # %bb.0:
+; RV32M-NEXT:    srli a1, a0, 1
+; RV32M-NEXT:    lui a2, 349525
+; RV32M-NEXT:    addi a2, a2, 1365
+; RV32M-NEXT:    and a1, a1, a2
+; RV32M-NEXT:    sub a0, a0, a1
+; RV32M-NEXT:    lui a1, 209715
+; RV32M-NEXT:    addi a1, a1, 819
+; RV32M-NEXT:    and a2, a0, a1
+; RV32M-NEXT:    srli a0, a0, 2
+; RV32M-NEXT:    and a0, a0, a1
+; RV32M-NEXT:    add a0, a2, a0
+; RV32M-NEXT:    srli a1, a0, 4
+; RV32M-NEXT:    add a0, a0, a1
+; RV32M-NEXT:    lui a1, 61681
+; RV32M-NEXT:    addi a1, a1, -241
+; RV32M-NEXT:    and a0, a0, a1
+; RV32M-NEXT:    lui a1, 4112
+; RV32M-NEXT:    addi a1, a1, 257
+; RV32M-NEXT:    mul a0, a0, a1
+; RV32M-NEXT:    srli a0, a0, 24
+; RV32M-NEXT:    ret
+;
+; RV64M-LABEL: test_ctpop_i32:
+; RV64M:       # %bb.0:
+; RV64M-NEXT:    srli a1, a0, 1
+; RV64M-NEXT:    lui a2, 349525
+; RV64M-NEXT:    addiw a2, a2, 1365
+; RV64M-NEXT:    and a1, a1, a2
+; RV64M-NEXT:    subw a0, a0, a1
+; RV64M-NEXT:    lui a1, 209715
+; RV64M-NEXT:    addiw a1, a1, 819
+; RV64M-NEXT:    and a2, a0, a1
+; RV64M-NEXT:    srli a0, a0, 2
+; RV64M-NEXT:    and a0, a0, a1
+; RV64M-NEXT:    add a0, a2, a0
+; RV64M-NEXT:    srli a1, a0, 4
+; RV64M-NEXT:    add a0, a0, a1
+; RV64M-NEXT:    lui a1, 61681
+; RV64M-NEXT:    addiw a1, a1, -241
+; RV64M-NEXT:    and a0, a0, a1
+; RV64M-NEXT:    lui a1, 4112
+; RV64M-NEXT:    addiw a1, a1, 257
+; RV64M-NEXT:    mulw a0, a0, a1
+; RV64M-NEXT:    srliw a0, a0, 24
+; RV64M-NEXT:    ret
+;
 ; RV32ZBB-LABEL: test_ctpop_i32:
 ; RV32ZBB:       # %bb.0:
 ; RV32ZBB-NEXT:    cpop a0, a0
@@ -1815,6 +2503,68 @@ define i64 @test_ctpop_i64(i64 %a) nounwind {
 ; RV64I-NEXT:    addi sp, sp, 16
 ; RV64I-NEXT:    ret
 ;
+; RV32M-LABEL: test_ctpop_i64:
+; RV32M:       # %bb.0:
+; RV32M-NEXT:    srli a2, a1, 1
+; RV32M-NEXT:    lui a3, 349525
+; RV32M-NEXT:    addi a3, a3, 1365
+; RV32M-NEXT:    and a2, a2, a3
+; RV32M-NEXT:    sub a1, a1, a2
+; RV32M-NEXT:    lui a2, 209715
+; RV32M-NEXT:    addi a2, a2, 819
+; RV32M-NEXT:    and a4, a1, a2
+; RV32M-NEXT:    srli a1, a1, 2
+; RV32M-NEXT:    and a1, a1, a2
+; RV32M-NEXT:    add a1, a4, a1
+; RV32M-NEXT:    srli a4, a1, 4
+; RV32M-NEXT:    add a1, a1, a4
+; RV32M-NEXT:    lui a4, 61681
+; RV32M-NEXT:    addi a4, a4, -241
+; RV32M-NEXT:    and a1, a1, a4
+; RV32M-NEXT:    lui a5, 4112
+; RV32M-NEXT:    addi a5, a5, 257
+; RV32M-NEXT:    mul a1, a1, a5
+; RV32M-NEXT:    srli a1, a1, 24
+; RV32M-NEXT:    srli a6, a0, 1
+; RV32M-NEXT:    and a3, a6, a3
+; RV32M-NEXT:    sub a0, a0, a3
+; RV32M-NEXT:    and a3, a0, a2
+; RV32M-NEXT:    srli a0, a0, 2
+; RV32M-NEXT:    and a0, a0, a2
+; RV32M-NEXT:    add a0, a3, a0
+; RV32M-NEXT:    srli a2, a0, 4
+; RV32M-NEXT:    add a0, a0, a2
+; RV32M-NEXT:    and a0, a0, a4
+; RV32M-NEXT:    mul a0, a0, a5
+; RV32M-NEXT:    srli a0, a0, 24
+; RV32M-NEXT:    add a0, a0, a1
+; RV32M-NEXT:    li a1, 0
+; RV32M-NEXT:    ret
+;
+; RV64M-LABEL: test_ctpop_i64:
+; RV64M:       # %bb.0:
+; RV64M-NEXT:    lui a1, %hi(.LCPI19_0)
+; RV64M-NEXT:    ld a1, %lo(.LCPI19_0)(a1)
+; RV64M-NEXT:    lui a2, %hi(.LCPI19_1)
+; RV64M-NEXT:    ld a2, %lo(.LCPI19_1)(a2)
+; RV64M-NEXT:    srli a3, a0, 1
+; RV64M-NEXT:    and a1, a3, a1
+; RV64M-NEXT:    sub a0, a0, a1
+; RV64M-NEXT:    and a1, a0, a2
+; RV64M-NEXT:    srli a0, a0, 2
+; RV64M-NEXT:    and a0, a0, a2
+; RV64M-NEXT:    add a0, a1, a0
+; RV64M-NEXT:    lui a1, %hi(.LCPI19_2)
+; RV64M-NEXT:    ld a1, %lo(.LCPI19_2)(a1)
+; RV64M-NEXT:    lui a2, %hi(.LCPI19_3)
+; RV64M-NEXT:    ld a2, %lo(.LCPI19_3)(a2)
+; RV64M-NEXT:    srli a3, a0, 4
+; RV64M-NEXT:    add a0, a0, a3
+; RV64M-NEXT:    and a0, a0, a1
+; RV64M-NEXT:    mul a0, a0, a2
+; RV64M-NEXT:    srli a0, a0, 56
+; RV64M-NEXT:    ret
+;
 ; RV32ZBB-LABEL: test_ctpop_i64:
 ; RV32ZBB:       # %bb.0:
 ; RV32ZBB-NEXT:    cpop a1, a1
@@ -1832,29 +2582,29 @@ define i64 @test_ctpop_i64(i64 %a) nounwind {
 }
 
 define i8 @test_parity_i8(i8 %a) {
-; RV32I-LABEL: test_parity_i8:
-; RV32I:       # %bb.0:
-; RV32I-NEXT:    andi a0, a0, 255
-; RV32I-NEXT:    srli a1, a0, 4
-; RV32I-NEXT:    xor a0, a0, a1
-; RV32I-NEXT:    srli a1, a0, 2
-; RV32I-NEXT:    xor a0, a0, a1
-; RV32I-NEXT:    srli a1, a0, 1
-; RV32I-NEXT:    xor a0, a0, a1
-; RV32I-NEXT:    andi a0, a0, 1
-; RV32I-NEXT:    ret
-;
-; RV64I-LABEL: test_parity_i8:
-; RV64I:       # %bb.0:
-; RV64I-NEXT:    andi a0, a0, 255
-; RV64I-NEXT:    srli a1, a0, 4
-; RV64I-NEXT:    xor a0, a0, a1
-; RV64I-NEXT:    srli a1, a0, 2
-; RV64I-NEXT:    xor a0, a0, a1
-; RV64I-NEXT:    srli a1, a0, 1
-; RV64I-NEXT:    xor a0, a0, a1
-; RV64I-NEXT:    andi a0, a0, 1
-; RV64I-NEXT:    ret
+; RV32_NOZBB-LABEL: test_parity_i8:
+; RV32_NOZBB:       # %bb.0:
+; RV32_NOZBB-NEXT:    andi a0, a0, 255
+; RV32_NOZBB-NEXT:    srli a1, a0, 4
+; RV32_NOZBB-NEXT:    xor a0, a0, a1
+; RV32_NOZBB-NEXT:    srli a1, a0, 2
+; RV32_NOZBB-NEXT:    xor a0, a0, a1
+; RV32_NOZBB-NEXT:    srli a1, a0, 1
+; RV32_NOZBB-NEXT:    xor a0, a0, a1
+; RV32_NOZBB-NEXT:    andi a0, a0, 1
+; RV32_NOZBB-NEXT:    ret
+;
+; RV64NOZBB-LABEL: test_parity_i8:
+; RV64NOZBB:       # %bb.0:
+; RV64NOZBB-NEXT:    andi a0, a0, 255
+; RV64NOZBB-NEXT:    srli a1, a0, 4
+; RV64NOZBB-NEXT:    xor a0, a0, a1
+; RV64NOZBB-NEXT:    srli a1, a0, 2
+; RV64NOZBB-NEXT:    xor a0, a0, a1
+; RV64NOZBB-NEXT:    srli a1, a0, 1
+; RV64NOZBB-NEXT:    xor a0, a0, a1
+; RV64NOZBB-NEXT:    andi a0, a0, 1
+; RV64NOZBB-NEXT:    ret
 ;
 ; RV32ZBB-LABEL: test_parity_i8:
 ; RV32ZBB:       # %bb.0:
@@ -1875,35 +2625,35 @@ define i8 @test_parity_i8(i8 %a) {
 }
 
 define i16 @test_parity_i16(i16 %a) {
-; RV32I-LABEL: test_parity_i16:
-; RV32I:       # %bb.0:
-; RV32I-NEXT:    slli a0, a0, 16
-; RV32I-NEXT:    srli a0, a0, 16
-; RV32I-NEXT:    srli a1, a0, 8
-; RV32I-NEXT:    xor a0, a0, a1
-; RV32I-NEXT:    srli a1, a0, 4
-; RV32I-NEXT:    xor a0, a0, a1
-; RV32I-NEXT:    srli a1, a0, 2
-; RV32I-NEXT:    xor a0, a0, a1
-; RV32I-NEXT:    srli a1, a0, 1
-; RV32I-NEXT:    xor a0, a0, a1
-; RV32I-NEXT:    andi a0, a0, 1
-; RV32I-NEXT:    ret
-;
-; RV64I-LABEL: test_parity_i16:
-; RV64I:       # %bb.0:
-; RV64I-NEXT:    slli a0, a0, 48
-; RV64I-NEXT:    srli a0, a0, 48
-; RV64I-NEXT:    srli a1, a0, 8
-; RV64I-NEXT:    xor a0, a0, a1
-; RV64I-NEXT:    srli a1, a0, 4
-; RV64I-NEXT:    xor a0, a0, a1
-; RV64I-NEXT:    srli a1, a0, 2
-; RV64I-NEXT:    xor a0, a0, a1
-; RV64I-NEXT:    srli a1, a0, 1
-; RV64I-NEXT:    xor a0, a0, a1
-; RV64I-NEXT:    andi a0, a0, 1
-; RV64I-NEXT:    ret
+; RV32_NOZBB-LABEL: test_parity_i16:
+; RV32_NOZBB:       # %bb.0:
+; RV32_NOZBB-NEXT:    slli a0, a0, 16
+; RV32_NOZBB-NEXT:    srli a0, a0, 16
+; RV32_NOZBB-NEXT:    srli a1, a0, 8
+; RV32_NOZBB-NEXT:    xor a0, a0, a1
+; RV32_NOZBB-NEXT:    srli a1, a0, 4
+; RV32_NOZBB-NEXT:    xor a0, a0, a1
+; RV32_NOZBB-NEXT:    srli a1, a0, 2
+; RV32_NOZBB-NEXT:    xor a0, a0, a1
+; RV32_NOZBB-NEXT:    srli a1, a0, 1
+; RV32_NOZBB-NEXT:    xor a0, a0, a1
+; RV32_NOZBB-NEXT:    andi a0, a0, 1
+; RV32_NOZBB-NEXT:    ret
+;
+; RV64NOZBB-LABEL: test_parity_i16:
+; RV64NOZBB:       # %bb.0:
+; RV64NOZBB-NEXT:    slli a0, a0, 48
+; RV64NOZBB-NEXT:    srli a0, a0, 48
+; RV64NOZBB-NEXT:    srli a1, a0, 8
+; RV64NOZBB-NEXT:    xor a0, a0, a1
+; RV64NOZBB-NEXT:    srli a1, a0, 4
+; RV64NOZBB-NEXT:    xor a0, a0, a1
+; RV64NOZBB-NEXT:    srli a1, a0, 2
+; RV64NOZBB-NEXT:    xor a0, a0, a1
+; RV64NOZBB-NEXT:    srli a1, a0, 1
+; RV64NOZBB-NEXT:    xor a0, a0, a1
+; RV64NOZBB-NEXT:    andi a0, a0, 1
+; RV64NOZBB-NEXT:    ret
 ;
 ; RV32ZBB-LABEL: test_parity_i16:
 ; RV32ZBB:       # %bb.0:
@@ -1924,37 +2674,37 @@ define i16 @test_parity_i16(i16 %a) {
 }
 
 define i32 @test_parity_i32(i32 %a) {
-; RV32I-LABEL: test_parity_i32:
-; RV32I:       # %bb.0:
-; RV32I-NEXT:    srli a1, a0, 16
-; RV32I-NEXT:    xor a0, a0, a1
-; RV32I-NEXT:    srli a1, a0, 8
-; RV32I-NEXT:    xor a0, a0, a1
-; RV32I-NEXT:    srli a1, a0, 4
-; RV32I-NEXT:    xor a0, a0, a1
-; RV32I-NEXT:    srli a1, a0, 2
-; RV32I-NEXT:    xor a0, a0, a1
-; RV32I-NEXT:    srli a1, a0, 1
-; RV32I-NEXT:    xor a0, a0, a1
-; RV32I-NEXT:    andi a0, a0, 1
-; RV32I-NEXT:    ret
-;
-; RV64I-LABEL: test_parity_i32:
-; RV64I:       # %bb.0:
-; RV64I-NEXT:    slli a1, a0, 32
-; RV64I-NEXT:    srli a1, a1, 32
-; RV64I-NEXT:    srliw a0, a0, 16
-; RV64I-NEXT:    xor a0, a1, a0
-; RV64I-NEXT:    srli a1, a0, 8
-; RV64I-NEXT:    xor a0, a0, a1
-; RV64I-NEXT:    srli a1, a0, 4
-; RV64I-NEXT:    xor a0, a0, a1
-; RV64I-NEXT:    srli a1, a0, 2
-; RV64I-NEXT:    xor a0, a0, a1
-; RV64I-NEXT:    srli a1, a0, 1
-; RV64I-NEXT:    xor a0, a0, a1
-; RV64I-NEXT:    andi a0, a0, 1
-; RV64I-NEXT:    ret
+; RV32_NOZBB-LABEL: test_parity_i32:
+; RV32_NOZBB:       # %bb.0:
+; RV32_NOZBB-NEXT:    srli a1, a0, 16
+; RV32_NOZBB-NEXT:    xor a0, a0, a1
+; RV32_NOZBB-NEXT:    srli a1, a0, 8
+; RV32_NOZBB-NEXT:    xor a0, a0, a1
+; RV32_NOZBB-NEXT:    srli a1, a0, 4
+; RV32_NOZBB-NEXT:    xor a0, a0, a1
+; RV32_NOZBB-NEXT:    srli a1, a0, 2
+; RV32_NOZBB-NEXT:    xor a0, a0, a1
+; RV32_NOZBB-NEXT:    srli a1, a0, 1
+; RV32_NOZBB-NEXT:    xor a0, a0, a1
+; RV32_NOZBB-NEXT:    andi a0, a0, 1
+; RV32_NOZBB-NEXT:    ret
+;
+; RV64NOZBB-LABEL: test_parity_i32:
+; RV64NOZBB:       # %bb.0:
+; RV64NOZBB-NEXT:    slli a1, a0, 32
+; RV64NOZBB-NEXT:    srli a1, a1, 32
+; RV64NOZBB-NEXT:    srliw a0, a0, 16
+; RV64NOZBB-NEXT:    xor a0, a1, a0
+; RV64NOZBB-NEXT:    srli a1, a0, 8
+; RV64NOZBB-NEXT:    xor a0, a0, a1
+; RV64NOZBB-NEXT:    srli a1, a0, 4
+; RV64NOZBB-NEXT:    xor a0, a0, a1
+; RV64NOZBB-NEXT:    srli a1, a0, 2
+; RV64NOZBB-NEXT:    xor a0, a0, a1
+; RV64NOZBB-NEXT:    srli a1, a0, 1
+; RV64NOZBB-NEXT:    xor a0, a0, a1
+; RV64NOZBB-NEXT:    andi a0, a0, 1
+; RV64NOZBB-NEXT:    ret
 ;
 ; RV32ZBB-LABEL: test_parity_i32:
 ; RV32ZBB:       # %bb.0:
@@ -1973,39 +2723,39 @@ define i32 @test_parity_i32(i32 %a) {
 }
 
 define i64 @test_parity_i64(i64 %a) {
-; RV32I-LABEL: test_parity_i64:
-; RV32I:       # %bb.0:
-; RV32I-NEXT:    xor a0, a0, a1
-; RV32I-NEXT:    srli a1, a0, 16
-; RV32I-NEXT:    xor a0, a0, a1
-; RV32I-NEXT:    srli a1, a0, 8
-; RV32I-NEXT:    xor a0, a0, a1
-; RV32I-NEXT:    srli a1, a0, 4
-; RV32I-NEXT:    xor a0, a0, a1
-; RV32I-NEXT:    srli a1, a0, 2
-; RV32I-NEXT:    xor a0, a0, a1
-; RV32I-NEXT:    srli a1, a0, 1
-; RV32I-NEXT:    xor a0, a0, a1
-; RV32I-NEXT:    andi a0, a0, 1
-; RV32I-NEXT:    li a1, 0
-; RV32I-NEXT:    ret
-;
-; RV64I-LABEL: test_parity_i64:
-; RV64I:       # %bb.0:
-; RV64I-NEXT:    srli a1, a0, 32
-; RV64I-NEXT:    xor a0, a0, a1
-; RV64I-NEXT:    srli a1, a0, 16
-; RV64I-NEXT:    xor a0, a0, a1
-; RV64I-NEXT:    srli a1, a0, 8
-; RV64I-NEXT:    xor a0, a0, a1
-; RV64I-NEXT:    srli a1, a0, 4
-; RV64I-NEXT:    xor a0, a0, a1
-; RV64I-NEXT:    srli a1, a0, 2
-; RV64I-NEXT:    xor a0, a0, a1
-; RV64I-NEXT:    srli a1, a0, 1
-; RV64I-NEXT:    xor a0, a0, a1
-; RV64I-NEXT:    andi a0, a0, 1
-; RV64I-NEXT:    ret
+; RV32_NOZBB-LABEL: test_parity_i64:
+; RV32_NOZBB:       # %bb.0:
+; RV32_NOZBB-NEXT:    xor a0, a0, a1
+; RV32_NOZBB-NEXT:    srli a1, a0, 16
+; RV32_NOZBB-NEXT:    xor a0, a0, a1
+; RV32_NOZBB-NEXT:    srli a1, a0, 8
+; RV32_NOZBB-NEXT:    xor a0, a0, a1
+; RV32_NOZBB-NEXT:    srli a1, a0, 4
+; RV32_NOZBB-NEXT:    xor a0, a0, a1
+; RV32_NOZBB-NEXT:    srli a1, a0, 2
+; RV32_NOZBB-NEXT:    xor a0, a0, a1
+; RV32_NOZBB-NEXT:    srli a1, a0, 1
+; RV32_NOZBB-NEXT:    xor a0, a0, a1
+; RV32_NOZBB-NEXT:    andi a0, a0, 1
+; RV32_NOZBB-NEXT:    li a1, 0
+; RV32_NOZBB-NEXT:    ret
+;
+; RV64NOZBB-LABEL: test_parity_i64:
+; RV64NOZBB:       # %bb.0:
+; RV64NOZBB-NEXT:    srli a1, a0, 32
+; RV64NOZBB-NEXT:    xor a0, a0, a1
+; RV64NOZBB-NEXT:    srli a1, a0, 16
+; RV64NOZBB-NEXT:    xor a0, a0, a1
+; RV64NOZBB-NEXT:    srli a1, a0, 8
+; RV64NOZBB-NEXT:    xor a0, a0, a1
+; RV64NOZBB-NEXT:    srli a1, a0, 4
+; RV64NOZBB-NEXT:    xor a0, a0, a1
+; RV64NOZBB-NEXT:    srli a1, a0, 2
+; RV64NOZBB-NEXT:    xor a0, a0, a1
+; RV64NOZBB-NEXT:    srli a1, a0, 1
+; RV64NOZBB-NEXT:    xor a0, a0, a1
+; RV64NOZBB-NEXT:    andi a0, a0, 1
+; RV64NOZBB-NEXT:    ret
 ;
 ; RV32ZBB-LABEL: test_parity_i64:
 ; RV32ZBB:       # %bb.0: