drm/amdgpu: enable DPG mode for VCN3.0
authorBoyuan Zhang <boyuan.zhang@amd.com>
Thu, 2 Apr 2020 17:28:07 +0000 (13:28 -0400)
committerAlex Deucher <alexander.deucher@amd.com>
Wed, 1 Jul 2020 05:59:12 +0000 (01:59 -0400)
Enable DPG mode for VCN3.0 by updating related flag.

V2: update description.

Signed-off-by: Boyuan Zhang <boyuan.zhang@amd.com>
Reviewed-by: James Zhu <james.zhu@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
drivers/gpu/drm/amd/amdgpu/nv.c
drivers/gpu/drm/amd/amdgpu/vcn_v3_0.c

index 936950f..ef3f07d 100644 (file)
@@ -726,6 +726,7 @@ static int nv_common_early_init(void *handle)
                        AMD_CG_SUPPORT_IH_CG |
                        AMD_CG_SUPPORT_MC_LS;
                adev->pg_flags = AMD_PG_SUPPORT_VCN |
+                       AMD_PG_SUPPORT_VCN_DPG |
                        AMD_PG_SUPPORT_JPEG |
                        AMD_PG_SUPPORT_ATHUB;
                adev->external_rev_id = adev->rev_id + 0x28;
index 98ba6dd..875bdc8 100644 (file)
@@ -254,7 +254,8 @@ static int vcn_v3_0_hw_init(void *handle)
 
 done:
        if (!r)
-               DRM_INFO("VCN decode and encode initialized successfully.\n");
+               DRM_INFO("VCN decode and encode initialized successfully(under %s).\n",
+                       (adev->pg_flags & AMD_PG_SUPPORT_VCN_DPG)?"DPG Mode":"SPG Mode");
 
        return r;
 }
@@ -278,7 +279,9 @@ static int vcn_v3_0_hw_fini(void *handle)
 
                ring = &adev->vcn.inst[i].ring_dec;
 
-               if (RREG32_SOC15(VCN, i, mmUVD_STATUS))
+               if ((adev->pg_flags & AMD_PG_SUPPORT_VCN_DPG) ||
+                       (adev->vcn.cur_state != AMD_PG_STATE_GATE &&
+                       RREG32_SOC15(VCN, i, mmUVD_STATUS)))
                        vcn_v3_0_set_powergating_state(adev, AMD_PG_STATE_GATE);
 
                ring->sched.ready = false;