spi: cadence_qspi: Call read_setup for STIG_READ
authorAshok Reddy Soma <ashok.reddy.soma@xilinx.com>
Wed, 24 Aug 2022 11:38:46 +0000 (05:38 -0600)
committerMichal Simek <michal.simek@amd.com>
Tue, 13 Sep 2022 09:32:48 +0000 (11:32 +0200)
In cadence_spi_read_id we are using STIG mode to read flash id's.
Call cadence_qspi_apb_command_read_setup() to setup cmd, addr and data
bus width properly before cadence_qspi_apb_command_read().

Signed-off-by: Ashok Reddy Soma <ashok.reddy.soma@xilinx.com>
Link: https://lore.kernel.org/r/20220824113847.7482-3-ashok.reddy.soma@xilinx.com
Signed-off-by: Michal Simek <michal.simek@amd.com>
drivers/spi/cadence_qspi.c

index 907f5da..6e50b94 100644 (file)
@@ -59,12 +59,17 @@ static int cadence_spi_write_speed(struct udevice *bus, uint hz)
 static int cadence_spi_read_id(struct cadence_spi_plat *plat, u8 len,
                               u8 *idcode)
 {
+       int err;
        struct spi_mem_op op = SPI_MEM_OP(SPI_MEM_OP_CMD(0x9F, 1),
                                          SPI_MEM_OP_NO_ADDR,
                                          SPI_MEM_OP_NO_DUMMY,
                                          SPI_MEM_OP_DATA_IN(len, idcode, 1));
 
-       return cadence_qspi_apb_command_read(plat, &op);
+       err = cadence_qspi_apb_command_read_setup(plat, &op);
+       if (!err)
+               err = cadence_qspi_apb_command_read(plat, &op);
+
+       return err;
 }
 
 /* Calibration sequence to determine the read data capture delay register */