drm/i915: PSR: Remove wrong LINK_DISABLE.
authorRodrigo Vivi <rodrigo.vivi@intel.com>
Fri, 10 Apr 2015 18:15:07 +0000 (11:15 -0700)
committerDaniel Vetter <daniel.vetter@ffwll.ch>
Tue, 14 Apr 2015 17:14:53 +0000 (19:14 +0200)
This wrong logic and useless define came from first versions and
came along with all rework. Just now I notice how ugly, wrong and
useless this is.

val is already defined as 0 anyway and logic is completelly wrong
and useless. So let's starting the link_standby fix with this
cleaning.

Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
Reviewed-by: Durgadoss R <durgadoss.r@intel.com>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
drivers/gpu/drm/i915/i915_reg.h
drivers/gpu/drm/i915/intel_psr.c

index 4b53b20..077cb90 100644 (file)
@@ -2688,7 +2688,6 @@ enum skl_disp_power_wells {
 #define EDP_PSR_CTL(dev)                       (EDP_PSR_BASE(dev) + 0)
 #define   EDP_PSR_ENABLE                       (1<<31)
 #define   BDW_PSR_SINGLE_FRAME                 (1<<30)
-#define   EDP_PSR_LINK_DISABLE                 (0<<27)
 #define   EDP_PSR_LINK_STANDBY                 (1<<27)
 #define   EDP_PSR_MIN_LINK_ENTRY_TIME_MASK     (3<<25)
 #define   EDP_PSR_MIN_LINK_ENTRY_TIME_8_LINES  (0<<25)
index 27608ce..db95b39 100644 (file)
@@ -269,8 +269,7 @@ static void hsw_psr_enable_source(struct intel_dp *intel_dp)
                val |= EDP_PSR_TP2_TP3_TIME_0us;
                val |= EDP_PSR_TP1_TIME_0us;
                val |= EDP_PSR_SKIP_AUX_EXIT;
-       } else
-               val |= EDP_PSR_LINK_DISABLE;
+       }
 
        I915_WRITE(EDP_PSR_CTL(dev), val |
                   (IS_BROADWELL(dev) ? 0 : link_entry_time) |