Remove MARU ARM board template from maru_board.c, it doesn't makes sense to take
an approach like this because x86 maru machine and arm maru machine are compiled for
different executables.
Drop leftovers of maru_board.c from maru_arm_board.c. Actually honour user-specified
RAM size for maru arm board, set bottom limit to 512 MB.
Do not initialize G3D MALI400 device in maru ARM SoC, we only need gles device from it
and we can initialize it explicitly.
Also bugs fixed:
- not registering ROM memory regions for migration during maru ARM SoC initialization;
- wrong chipid_and_omr array size;
- missleading initialization of ROM memory region alias.
Signed-off-by: Igor Mitsyanko <i.mitsyanko@samsung.com>
obj-i386-y += maru_overlay.o
obj-i386-y += maru_pm.o
obj-i386-y += maru_vga.o
-obj-arm-y += maru_arm.o
+obj-arm-y += maru_arm_soc.o
obj-arm-y += maru_arm_board.o
obj-arm-y += maru_arm_vpci.o
obj-arm-y += maru_arm_pmu.o
+++ /dev/null
-/*
- * Samsung Maru ARM SoC emulation
- *
- * Based on exynos4210.c
- *
- * Copyright (c) 2011 Samsung Electronics Co., Ltd.
- * Maksim Kozlov <m.kozlov@samsung.com>
- * Evgeny Voevodin <e.voevodin@samsung.com>
- * Igor Mitsyanko <i.mitsyanko@samsung.com>
- *
- * This program is free software; you can redistribute it and/or modify it
- * under the terms of the GNU General Public License as published by the
- * Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful, but WITHOUT
- * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
- * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
- * for more details.
- *
- * You should have received a copy of the GNU General Public License along
- * with this program; if not, see <http://www.gnu.org/licenses/>.
- *
- */
-
-#include "boards.h"
-#include "arm-misc.h"
-#include "sysbus.h"
-#include "pci.h"
-#include "maru_arm.h"
-#include "i2c.h"
-#include "exec-memory.h"
-
-#include "loader.h"
-#include "virtio-transport.h"
-#include "exynos4210_i2s.h"
-
-#define EXYNOS4210_CHIPID_ADDR 0x10000000
-
-/* CMUs */
-#define EXYNOS4210_CMU_LEFTBUS_BASE_ADDR 0x10034000
-#define EXYNOS4210_CMU_RIGHTBUS_BASE_ADDR 0x10038000
-#define EXYNOS4210_CMU_TOP_BASE_ADDR 0x1003C000
-#define EXYNOS4210_CMU_DMC_BASE_ADDR 0x10040000
-#define EXYNOS4210_CMU_CPU_BASE_ADDR 0x10044000
-
-/* PWM */
-#define EXYNOS4210_PWM_BASE_ADDR 0x139D0000
-
-/* RTC */
-#define EXYNOS4210_RTC_BASE_ADDR 0x10070000
-
-/* MCT */
-#define EXYNOS4210_MCT_BASE_ADDR 0x10050000
-
-/* DMA */
-#define EXYNOS4210_DMAMEM_BASE_ADDR 0x12840000
-#define EXYNOS4210_DMAPERI0_BASE_ADDR 0x12680000
-#define EXYNOS4210_DMAPERI1_BASE_ADDR 0x12690000
-
-/* I2C */
-#define EXYNOS4210_I2C_SHIFT 0x00010000
-#define EXYNOS4210_I2C_BASE_ADDR 0x13860000
-/* Interrupt Group of External Interrupt Combiner for I2C */
-#define EXYNOS4210_I2C_INTG 27
-#define EXYNOS4210_HDMI_INTG 16
-
-/* There are two set of touch screen interfaces, which share one ADC */
-#define EXYNOS4210_TS0_BASE_ADDR 0x13910000
-#define EXYNOS4210_TS1_BASE_ADDR 0x13911000
-#define EXYNOS4210_TS_INTG 19
-
-/* UART's definitions */
-#define EXYNOS4210_UART0_BASE_ADDR 0x13800000
-#define EXYNOS4210_UART1_BASE_ADDR 0x13810000
-#define EXYNOS4210_UART2_BASE_ADDR 0x13820000
-#define EXYNOS4210_UART3_BASE_ADDR 0x13830000
-#define EXYNOS4210_UART0_FIFO_SIZE 256
-#define EXYNOS4210_UART1_FIFO_SIZE 64
-#define EXYNOS4210_UART2_FIFO_SIZE 16
-#define EXYNOS4210_UART3_FIFO_SIZE 16
-/* Interrupt Group of External Interrupt Combiner for UART */
-#define EXYNOS4210_UART_INT_GRP 26
-
-/* External GIC */
-#define EXYNOS4210_EXT_GIC_CPU_BASE_ADDR 0x10480000
-#define EXYNOS4210_EXT_GIC_DIST_BASE_ADDR 0x10490000
-
-/* Combiner */
-#define EXYNOS4210_EXT_COMBINER_BASE_ADDR 0x10440000
-#define EXYNOS4210_INT_COMBINER_BASE_ADDR 0x10448000
-
-/* SD/MMC host controllers SFR base addresses */
-#define EXYNOS4210_SDHC0_BASE_ADDR 0x12510000
-#define EXYNOS4210_SDHC1_BASE_ADDR 0x12520000
-#define EXYNOS4210_SDHC2_BASE_ADDR 0x12530000
-#define EXYNOS4210_SDHC3_BASE_ADDR 0x12540000
-
-/* PMU SFR base address */
-#define EXYNOS4210_PMU_BASE_ADDR 0x10020000
-
-/* Display controllers (FIMD) */
-#define EXYNOS4210_FIMD0_BASE_ADDR 0x11C00000
-#define EXYNOS4210_FIMD1_BASE_ADDR 0x12000000
-
-/* MALI400 (G3D) */
-#define EXYNOS4210_G3D_BASE_ADDR 0x13000000
-#define EXYNOS4210_G3D_PIXEL_PROC_0_IRQ 0
-#define EXYNOS4210_G3D_PIXEL_PROC_1_IRQ 1
-#define EXYNOS4210_G3D_PIXEL_PROC_2_IRQ 2
-#define EXYNOS4210_G3D_PIXEL_PROC_3_IRQ 3
-#define EXYNOS4210_G3D_GEOM_PROC_IRQ 4
-#define EXYNOS4210_G3D_PMU_IRQ 5
-#define EXYNOS4210_G3D_PPMMU0_IRQ 0
-#define EXYNOS4210_G3D_PPMMU1_IRQ 1
-#define EXYNOS4210_G3D_PPMMU2_IRQ 2
-#define EXYNOS4210_G3D_PPMMU3_IRQ 3
-#define EXYNOS4210_G3D_GPMMU_IRQ 4
-
-/* PPMU */
-#define EXYNOS4210_PPMU_CPU_BASE_ADDR 0x106C0000
-/* DMC */
-#define EXYNOS4210_DMC0_BASE_ADDR 0x10400000
-#define EXYNOS4210_DMC1_BASE_ADDR 0x10410000
-
-/* I2S */
-#define EXYNOS4210_I2S0_BASE_ADDR 0x03830000
-
-/* VirtIO BLK */
-#define EXYNOS4210_VIRTIO_BLK_BASE_ADDR 0x10AD0000
-/* VirtIO NET */
-#define EXYNOS4210_VIRTIO_NET_BASE_ADDR 0x10AC0000
-
-/* pl050 ps/2 interface */
-#define EXYNOS4210_PL050_BASE_ADDR 0x12E30000
-
-static uint8_t chipid_and_omr[] = { 0x11, 0x02, 0x21, 0x43,
- 0x09, 0x00, 0x00, 0x00 };
-
-void maru_arm_write_secondary(CPUARMState *env,
- const struct arm_boot_info *info)
-{
- int n;
- uint32_t smpboot[] = {
- 0xe59f3024, /* ldr r3, External gic_cpu_if */
- 0xe59f2024, /* ldr r2, Internal gic_cpu_if */
- 0xe59f0024, /* ldr r0, startaddr */
- 0xe3a01001, /* mov r1, #1 */
- 0xe5821000, /* str r1, [r2] */
- 0xe5831000, /* str r1, [r3] */
- 0xe320f003, /* wfi */
- 0xe5901000, /* ldr r1, [r0] */
- 0xe1110001, /* tst r1, r1 */
- 0x0afffffb, /* beq <wfi> */
- 0xe12fff11, /* bx r1 */
- EXYNOS4210_EXT_GIC_CPU_BASE_ADDR,
- 0, /* gic_cpu_if: base address of Internal GIC CPU interface */
- 0 /* bootreg: Boot register address is held here */
- };
- smpboot[ARRAY_SIZE(smpboot) - 1] = info->smp_bootreg_addr;
- smpboot[ARRAY_SIZE(smpboot) - 2] = info->gic_cpu_if_addr;
- for (n = 0; n < ARRAY_SIZE(smpboot); n++) {
- smpboot[n] = tswap32(smpboot[n]);
- }
- rom_add_blob_fixed("smpboot", smpboot, sizeof(smpboot),
- info->smp_loader_start);
-}
-
-Exynos4210State *maru_arm_init(MemoryRegion *system_mem,
- unsigned long ram_size)
-{
- qemu_irq cpu_irq[4];
- int n;
- Exynos4210State *s = g_new(Exynos4210State, 1);
- qemu_irq *irqp;
- qemu_irq gate_irq[EXYNOS4210_IRQ_GATE_NINPUTS];
- unsigned long mem_size;
- DeviceState *dev;
- SysBusDevice *busdev;
-
- for (n = 0; n < EXYNOS4210_NCPUS; n++) {
- s->env[n] = cpu_init("cortex-a9");
- if (!s->env[n]) {
- fprintf(stderr, "Unable to find CPU %d definition\n", n);
- exit(1);
- }
- /* Create PIC controller for each processor instance */
- irqp = arm_pic_init_cpu(s->env[n]);
-
- /*
- * Get GICs gpio_in cpu_irq to connect a combiner to them later.
- * Use only IRQ for a while.
- */
- cpu_irq[n] = irqp[ARM_PIC_CPU_IRQ];
- }
-
- /*** IRQs ***/
-
- s->irq_table = exynos4210_init_irq(&s->irqs);
-
- /* IRQ Gate */
- dev = qdev_create(NULL, "exynos4210.irq_gate");
- qdev_prop_set_uint32(dev, "n_out", EXYNOS4210_NCPUS);
- qdev_prop_set_uint32(dev, "n_in", EXYNOS4210_IRQ_GATE_NINPUTS);
- qdev_init_nofail(dev);
- /* Get IRQ Gate input in gate_irq */
- for (n = 0; n < EXYNOS4210_IRQ_GATE_NINPUTS; n++) {
- gate_irq[n] = qdev_get_gpio_in(dev, n);
- }
- busdev = sysbus_from_qdev(dev);
- /* Connect IRQ Gate output to cpu_irq */
- for (n = 0; n < EXYNOS4210_NCPUS; n++) {
- sysbus_connect_irq(busdev, n, cpu_irq[n]);
- }
-
- /* Private memory region and Internal GIC */
- dev = qdev_create(NULL, "a9mpcore_priv");
- qdev_prop_set_uint32(dev, "num-cpu", EXYNOS4210_NCPUS);
- qdev_init_nofail(dev);
- busdev = sysbus_from_qdev(dev);
- sysbus_mmio_map(busdev, 0, EXYNOS4210_SMP_PRIVATE_BASE_ADDR);
- for (n = 0; n < EXYNOS4210_NCPUS; n++) {
- sysbus_connect_irq(busdev, n, gate_irq[n * 4]);
- }
- for (n = 0; n < EXYNOS4210_INT_GIC_NIRQ; n++) {
- s->irqs.int_gic_irq[n] = qdev_get_gpio_in(dev, n);
- }
-
- /* Cache controller */
- sysbus_create_simple("l2x0", EXYNOS4210_L2X0_BASE_ADDR, NULL);
-
- /* External GIC */
- dev = qdev_create(NULL, "exynos4210.gic");
- qdev_prop_set_uint32(dev, "num-cpu", EXYNOS4210_NCPUS);
- qdev_init_nofail(dev);
- busdev = sysbus_from_qdev(dev);
- /* Map CPU interface */
- sysbus_mmio_map(busdev, 0, EXYNOS4210_EXT_GIC_CPU_BASE_ADDR);
- /* Map Distributer interface */
- sysbus_mmio_map(busdev, 1, EXYNOS4210_EXT_GIC_DIST_BASE_ADDR);
- for (n = 0; n < EXYNOS4210_NCPUS; n++) {
- sysbus_connect_irq(busdev, n, gate_irq[n * 4 + 1]);
- }
- for (n = 0; n < EXYNOS4210_EXT_GIC_NIRQ; n++) {
- s->irqs.ext_gic_irq[n] = qdev_get_gpio_in(dev, n);
- }
-
- /* Internal Interrupt Combiner */
- dev = qdev_create(NULL, "exynos4210.combiner");
- qdev_init_nofail(dev);
- busdev = sysbus_from_qdev(dev);
- for (n = 0; n < EXYNOS4210_MAX_INT_COMBINER_OUT_IRQ; n++) {
- sysbus_connect_irq(busdev, n, s->irqs.int_gic_irq[n]);
- }
- exynos4210_combiner_get_gpioin(&s->irqs, dev, 0);
- sysbus_mmio_map(busdev, 0, EXYNOS4210_INT_COMBINER_BASE_ADDR);
-
- /* External Interrupt Combiner */
- dev = qdev_create(NULL, "exynos4210.combiner");
- qdev_prop_set_uint32(dev, "external", 1);
- qdev_init_nofail(dev);
- busdev = sysbus_from_qdev(dev);
- for (n = 0; n < EXYNOS4210_MAX_INT_COMBINER_OUT_IRQ; n++) {
- sysbus_connect_irq(busdev, n, s->irqs.ext_gic_irq[n]);
- }
- exynos4210_combiner_get_gpioin(&s->irqs, dev, 1);
- sysbus_mmio_map(busdev, 0, EXYNOS4210_EXT_COMBINER_BASE_ADDR);
-
- /* Initialize board IRQs. */
- exynos4210_init_board_irqs(&s->irqs);
-
- /*** Memory ***/
-
- /* Chip-ID and OMR */
- memory_region_init_ram_ptr(&s->chipid_mem, "exynos4210.chipid",
- sizeof(chipid_and_omr), chipid_and_omr);
- memory_region_set_readonly(&s->chipid_mem, true);
- memory_region_add_subregion(system_mem, EXYNOS4210_CHIPID_ADDR,
- &s->chipid_mem);
-
- /* Internal ROM */
- memory_region_init_ram(&s->irom_mem, "exynos4210.irom",
- EXYNOS4210_IROM_SIZE);
- memory_region_set_readonly(&s->irom_mem, true);
- memory_region_add_subregion(system_mem, EXYNOS4210_IROM_BASE_ADDR,
- &s->irom_mem);
- /* mirror of iROM */
- memory_region_init_alias(&s->irom_alias_mem, "exynos4210.irom_alias",
- &s->irom_mem,
- EXYNOS4210_IROM_BASE_ADDR,
- EXYNOS4210_IROM_SIZE);
- memory_region_set_readonly(&s->irom_alias_mem, true);
- memory_region_add_subregion(system_mem, EXYNOS4210_IROM_MIRROR_BASE_ADDR,
- &s->irom_alias_mem);
-
- /* Internal RAM */
- memory_region_init_ram(&s->iram_mem, "exynos4210.iram",
- EXYNOS4210_IRAM_SIZE);
- vmstate_register_ram_global(&s->iram_mem);
- memory_region_add_subregion(system_mem, EXYNOS4210_IRAM_BASE_ADDR,
- &s->iram_mem);
-
- /* DRAM */
- mem_size = ram_size;
- if (mem_size > EXYNOS4210_DRAM_MAX_SIZE) {
- memory_region_init_ram(&s->dram1_mem, "exynos4210.dram1",
- mem_size - EXYNOS4210_DRAM_MAX_SIZE);
- vmstate_register_ram_global(&s->dram1_mem);
- memory_region_add_subregion(system_mem, EXYNOS4210_DRAM1_BASE_ADDR,
- &s->dram1_mem);
- mem_size = EXYNOS4210_DRAM_MAX_SIZE;
- }
- memory_region_init_ram(&s->dram0_mem, "exynos4210.dram0", mem_size);
- vmstate_register_ram_global(&s->dram0_mem);
- memory_region_add_subregion(system_mem, EXYNOS4210_DRAM0_BASE_ADDR,
- &s->dram0_mem);
-
- /* Audio Subsystem Internal Memory */
- memory_region_init_ram(&s->audss_intmem, "exynos4210.audss",
- EXYNOS4210_AUDSS_INTMEM_SIZE);
- vmstate_register_ram_global(&s->audss_intmem);
- memory_region_add_subregion(system_mem, EXYNOS4210_AUDSS_INTMEM_BASE_ADDR,
- &s->audss_intmem);
-
- /*** Clock devices ***/
-
- /* PMU. Must be initialized before CMU.
- * The only reason of existence at the moment is that secondary CPU boot
- * loader uses PMU INFORM5 register as a holding pen.
- */
- sysbus_create_simple("maru_arm.pmu", EXYNOS4210_PMU_BASE_ADDR, NULL);
-
- /* CMUs */
- exynos4210_cmu_create(EXYNOS4210_CMU_LEFTBUS_BASE_ADDR,
- EXYNOS4210_CMU_LEFTBUS);
- exynos4210_cmu_create(EXYNOS4210_CMU_RIGHTBUS_BASE_ADDR,
- EXYNOS4210_CMU_RIGHTBUS);
- exynos4210_cmu_create(EXYNOS4210_CMU_TOP_BASE_ADDR, EXYNOS4210_CMU_TOP);
- exynos4210_cmu_create(EXYNOS4210_CMU_DMC_BASE_ADDR, EXYNOS4210_CMU_DMC);
- exynos4210_cmu_create(EXYNOS4210_CMU_CPU_BASE_ADDR, EXYNOS4210_CMU_CPU);
-
- /* PWM */
- sysbus_create_varargs("exynos4210.pwm", EXYNOS4210_PWM_BASE_ADDR,
- s->irq_table[exynos4210_get_irq(22, 0)],
- s->irq_table[exynos4210_get_irq(22, 1)],
- s->irq_table[exynos4210_get_irq(22, 2)],
- s->irq_table[exynos4210_get_irq(22, 3)],
- s->irq_table[exynos4210_get_irq(22, 4)],
- NULL);
-
- /* RTC */
- sysbus_create_varargs("exynos4210.rtc", EXYNOS4210_RTC_BASE_ADDR,
- s->irq_table[exynos4210_get_irq(23, 0)],
- s->irq_table[exynos4210_get_irq(23, 1)],
- NULL);
-
- /* Multi Core Timer */
- dev = qdev_create(NULL, "exynos4210.mct");
- qdev_init_nofail(dev);
- busdev = sysbus_from_qdev(dev);
- for (n = 0; n < 4; n++) {
- /* Connect global timer interrupts to Combiner gpio_in */
- sysbus_connect_irq(busdev, n,
- s->irq_table[exynos4210_get_irq(1, 4 + n)]);
- }
- /* Connect local timer interrupts to Combiner gpio_in */
- sysbus_connect_irq(busdev, 4,
- s->irq_table[exynos4210_get_irq(51, 0)]);
- sysbus_connect_irq(busdev, 5,
- s->irq_table[exynos4210_get_irq(35, 3)]);
- sysbus_mmio_map(busdev, 0, EXYNOS4210_MCT_BASE_ADDR);
-
- /*** I2C ***/
- for (n = 0; n < EXYNOS4210_I2C_NUMBER; n++) {
- uint32_t addr = EXYNOS4210_I2C_BASE_ADDR + EXYNOS4210_I2C_SHIFT * n;
- qemu_irq i2c_irq;
-
- if (n < 8) {
- i2c_irq = s->irq_table[exynos4210_get_irq(EXYNOS4210_I2C_INTG, n)];
- } else {
- i2c_irq = s->irq_table[exynos4210_get_irq(EXYNOS4210_HDMI_INTG, 1)];
- }
-
- dev = qdev_create(NULL, "exynos4210.i2c");
- qdev_init_nofail(dev);
- busdev = sysbus_from_qdev(dev);
- sysbus_connect_irq(busdev, 0, i2c_irq);
- sysbus_mmio_map(busdev, 0, addr);
- s->i2c_if[n] = (i2c_bus *)qdev_get_child_bus(dev, "i2c");
- }
-
- /*** UARTs ***/
- exynos4210_uart_create(EXYNOS4210_UART0_BASE_ADDR,
- EXYNOS4210_UART0_FIFO_SIZE, 0, NULL,
- s->irq_table[exynos4210_get_irq(EXYNOS4210_UART_INT_GRP, 0)]);
-
- exynos4210_uart_create(EXYNOS4210_UART1_BASE_ADDR,
- EXYNOS4210_UART1_FIFO_SIZE, 1, NULL,
- s->irq_table[exynos4210_get_irq(EXYNOS4210_UART_INT_GRP, 1)]);
-
- exynos4210_uart_create(EXYNOS4210_UART2_BASE_ADDR,
- EXYNOS4210_UART2_FIFO_SIZE, 2, NULL,
- s->irq_table[exynos4210_get_irq(EXYNOS4210_UART_INT_GRP, 2)]);
-
- exynos4210_uart_create(EXYNOS4210_UART3_BASE_ADDR,
- EXYNOS4210_UART3_FIFO_SIZE, 3, NULL,
- s->irq_table[exynos4210_get_irq(EXYNOS4210_UART_INT_GRP, 3)]);
-
-
- /*** Display controller (FIMD) ***/
- sysbus_create_varargs("exynos4210.fimd", EXYNOS4210_FIMD0_BASE_ADDR,
- s->irq_table[exynos4210_get_irq(11, 0)],
- s->irq_table[exynos4210_get_irq(11, 1)],
- s->irq_table[exynos4210_get_irq(11, 2)],
- NULL);
-
- /*** GPU MALI400 (G3D) ***/
- sysbus_create_varargs("exynos4210.g3d", EXYNOS4210_G3D_BASE_ADDR,
- s->irq_table[exynos4210_get_irq(14, EXYNOS4210_G3D_PIXEL_PROC_0_IRQ)],
- s->irq_table[exynos4210_get_irq(14, EXYNOS4210_G3D_PIXEL_PROC_1_IRQ)],
- s->irq_table[exynos4210_get_irq(14, EXYNOS4210_G3D_PIXEL_PROC_2_IRQ)],
- s->irq_table[exynos4210_get_irq(14, EXYNOS4210_G3D_PIXEL_PROC_3_IRQ)],
- s->irq_table[exynos4210_get_irq(14, EXYNOS4210_G3D_GEOM_PROC_IRQ)],
- s->irq_table[exynos4210_get_irq(14, EXYNOS4210_G3D_PMU_IRQ)],
- s->irq_table[exynos4210_get_irq(13, EXYNOS4210_G3D_PPMMU0_IRQ)],
- s->irq_table[exynos4210_get_irq(13, EXYNOS4210_G3D_PPMMU1_IRQ)],
- s->irq_table[exynos4210_get_irq(13, EXYNOS4210_G3D_PPMMU2_IRQ)],
- s->irq_table[exynos4210_get_irq(13, EXYNOS4210_G3D_PPMMU3_IRQ)],
- s->irq_table[exynos4210_get_irq(13, EXYNOS4210_G3D_GPMMU_IRQ)],
- NULL);
-
- /* I2S0 */
- s->i2s_bus[0] = exynos4210_i2s_bus_new("exynos4210.i2s",
- EXYNOS4210_I2S0_BASE_ADDR,
- s->irqs.ext_gic_irq[97]);
-
- sysbus_create_simple(VIRTIO_MMIO_TRANSPORT, EXYNOS4210_VIRTIO_BLK_BASE_ADDR,
- s->irq_table[exynos4210_get_irq(37, 3)]);
- sysbus_create_simple(VIRTIO_MMIO_TRANSPORT, EXYNOS4210_VIRTIO_NET_BASE_ADDR,
- s->irq_table[exynos4210_get_irq(37, 2)]);
-
- /* PL050 PS/2 if keyboard */
- sysbus_create_simple("pl050_keyboard", EXYNOS4210_PL050_BASE_ADDR,
- s->irq_table[exynos4210_get_irq(28, 2)]);
-
- return s;
-}
void maru_arm_write_secondary(CPUARMState *env,
const struct arm_boot_info *info);
-Exynos4210State *maru_arm_init(MemoryRegion *system_mem,
+Exynos4210State *maru_arm_soc_init(MemoryRegion *system_mem,
unsigned long ram_size);
+int codec_init(PCIBus *bus);
+int maru_camera_pci_init(PCIBus *bus);
+
#endif /* MARU_ARM_H_ */
#endif
#ifndef DEBUG_LOG_PATH
-#define DEBUG_LOG_PATH "./debug.log"
+#define DEBUG_LOG_PATH "./debug.log"
#endif
-#define EXYNOS4210_WM8994_ADDR 0x1A
-
-int codec_init(PCIBus *bus);
-int maru_camera_pci_init(PCIBus *bus);
-
-static int maru_arm_board_id = 0xF3B;
-static int maru_arm_board_smp_bootreg_addr = EXYNOS4210_SECOND_CPU_BOOTREG;
-static unsigned long maru_arm_board_ram_size = 0x40000000;
+#define EXYNOS4210_WM8994_ADDR 0x1A
+#define MARU_ARM_BOARD_ID 0xF3B
+#define MARU_ARM_BOARD_SMP_BOOTREG_ADDR EXYNOS4210_SECOND_CPU_BOOTREG
+#define MARU_ARM_BOARD_RAMSIZE_MIN 0x20000000
+#define MARU_ARM_BOARD_RAMSIZE_DEFAULT 0x40000000
static struct arm_boot_info maru_arm_board_binfo = {
.loader_start = EXYNOS4210_BASE_BOOT_ADDR,
.write_secondary_boot = maru_arm_write_secondary,
};
-static Exynos4210State *maru_arm_board_init_common(
- const char *kernel_filename,
- const char *kernel_cmdline,
- const char *initrd_filename)
+static void maru_arm_machine_init(ram_addr_t ram_size,
+ const char *boot_device,
+ const char *kernel_filename,
+ const char *kernel_cmdline,
+ const char *initrd_filename,
+ const char *cpu_model)
{
- maru_arm_board_binfo.ram_size = maru_arm_board_ram_size;
- maru_arm_board_binfo.board_id = maru_arm_board_id;
- maru_arm_board_binfo.smp_bootreg_addr = maru_arm_board_smp_bootreg_addr;
+ Exynos4210State *s;
+ DeviceState *dev, *i2c_dev;
+ PCIBus *pci_bus;
+
+ if (ram_size < MARU_ARM_BOARD_RAMSIZE_MIN) {
+ ram_size = MARU_ARM_BOARD_RAMSIZE_DEFAULT;
+ fprintf(stderr, "RAM size is too small, setting to default value 0x%lx",
+ (long unsigned int)ram_size);
+ }
+
+ maru_arm_board_binfo.ram_size = ram_size;
+ maru_arm_board_binfo.board_id = MARU_ARM_BOARD_ID;
+ maru_arm_board_binfo.smp_bootreg_addr = MARU_ARM_BOARD_SMP_BOOTREG_ADDR;
maru_arm_board_binfo.kernel_filename = kernel_filename;
maru_arm_board_binfo.initrd_filename = initrd_filename;
maru_arm_board_binfo.kernel_cmdline = kernel_cmdline;
" kernel_filename: %s\n"
" kernel_cmdline: %s\n"
" initrd_filename: %s\n",
- exynos4_board_ram_size[board_type] / 1048576,
- exynos4_board_ram_size[board_type],
+ (long unsigned int)ram_size / 1048576,
+ (long unsigned int)ram_size,
kernel_filename,
kernel_cmdline,
initrd_filename);
-
- return maru_arm_init(get_system_memory(), maru_arm_board_ram_size);
-}
-
-static void maru_arm_machine_init(ram_addr_t ram_size,
- const char *boot_device,
- const char *kernel_filename,
- const char *kernel_cmdline,
- const char *initrd_filename,
- const char *cpu_model)
-{
- Exynos4210State *s;
- DeviceState *dev, *i2c_dev;
- PCIBus *pci_bus;
-
- s = maru_arm_board_init_common(kernel_filename,
- kernel_cmdline, initrd_filename);
+ s = maru_arm_soc_init(get_system_memory(), ram_size);
/* WM8994 */
i2c_dev = i2c_create_slave(s->i2c_if[1], "wm8994", EXYNOS4210_WM8994_ADDR);
arm_load_kernel(first_cpu, &maru_arm_board_binfo);
}
-static void maru_common_init(ram_addr_t ram_size,
- const char *boot_device,
- const char *kernel_filename,
- const char *kernel_cmdline,
- const char *initrd_filename,
- const char *cpu_model)
-{
-// prepare for universal virtual board...
-#if defined(TARGET_I386)
-#elif defined(TARGET_ARM)
-#endif
-}
-static void maru_arm_board_init(ram_addr_t ram_size,
- const char *boot_device,
- const char *kernel_filename,
- const char *kernel_cmdline,
- const char *initrd_filename,
- const char *cpu_model)
-{
- maru_arm_machine_init(ram_size, boot_device, kernel_filename,
- kernel_cmdline, initrd_filename, cpu_model);
- maru_common_init(ram_size, boot_device, kernel_filename,
- kernel_cmdline, initrd_filename, cpu_model);
-}
-
static QEMUMachine maru_arm_machine = {
.name = "maru-arm-machine",
.desc = "maru board(ARM)",
- .init = maru_arm_board_init,
+ .init = maru_arm_machine_init,
.max_cpus = 255,
};
static void maru_machine_init(void)
{
-#if defined(TARGET_ARM)
qemu_register_machine(&maru_arm_machine);
-#else
-#error
-#endif
}
machine_init(maru_machine_init);
--- /dev/null
+/*
+ * Samsung Maru ARM SoC emulation
+ *
+ * Based on exynos4210.c
+ *
+ * Copyright (c) 2011 Samsung Electronics Co., Ltd.
+ * Maksim Kozlov <m.kozlov@samsung.com>
+ * Evgeny Voevodin <e.voevodin@samsung.com>
+ * Igor Mitsyanko <i.mitsyanko@samsung.com>
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License as published by the
+ * Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
+ * for more details.
+ *
+ * You should have received a copy of the GNU General Public License along
+ * with this program; if not, see <http://www.gnu.org/licenses/>.
+ *
+ */
+
+#include "boards.h"
+#include "arm-misc.h"
+#include "sysbus.h"
+#include "pci.h"
+#include "maru_arm.h"
+#include "i2c.h"
+#include "exec-memory.h"
+#ifdef CONFIG_BUILD_GLES
+#include "gles2.h"
+#endif
+
+#include "loader.h"
+#include "virtio-transport.h"
+#include "exynos4210_i2s.h"
+
+#define EXYNOS4210_CHIPID_ADDR 0x10000000
+
+/* CMUs */
+#define EXYNOS4210_CMU_LEFTBUS_BASE_ADDR 0x10034000
+#define EXYNOS4210_CMU_RIGHTBUS_BASE_ADDR 0x10038000
+#define EXYNOS4210_CMU_TOP_BASE_ADDR 0x1003C000
+#define EXYNOS4210_CMU_DMC_BASE_ADDR 0x10040000
+#define EXYNOS4210_CMU_CPU_BASE_ADDR 0x10044000
+
+/* PWM */
+#define EXYNOS4210_PWM_BASE_ADDR 0x139D0000
+
+/* RTC */
+#define EXYNOS4210_RTC_BASE_ADDR 0x10070000
+
+/* MCT */
+#define EXYNOS4210_MCT_BASE_ADDR 0x10050000
+
+/* DMA */
+#define EXYNOS4210_DMAMEM_BASE_ADDR 0x12840000
+#define EXYNOS4210_DMAPERI0_BASE_ADDR 0x12680000
+#define EXYNOS4210_DMAPERI1_BASE_ADDR 0x12690000
+
+/* I2C */
+#define EXYNOS4210_I2C_SHIFT 0x00010000
+#define EXYNOS4210_I2C_BASE_ADDR 0x13860000
+/* Interrupt Group of External Interrupt Combiner for I2C */
+#define EXYNOS4210_I2C_INTG 27
+#define EXYNOS4210_HDMI_INTG 16
+
+/* There are two set of touch screen interfaces, which share one ADC */
+#define EXYNOS4210_TS0_BASE_ADDR 0x13910000
+#define EXYNOS4210_TS1_BASE_ADDR 0x13911000
+#define EXYNOS4210_TS_INTG 19
+
+/* UART's definitions */
+#define EXYNOS4210_UART0_BASE_ADDR 0x13800000
+#define EXYNOS4210_UART1_BASE_ADDR 0x13810000
+#define EXYNOS4210_UART2_BASE_ADDR 0x13820000
+#define EXYNOS4210_UART3_BASE_ADDR 0x13830000
+#define EXYNOS4210_UART0_FIFO_SIZE 256
+#define EXYNOS4210_UART1_FIFO_SIZE 64
+#define EXYNOS4210_UART2_FIFO_SIZE 16
+#define EXYNOS4210_UART3_FIFO_SIZE 16
+/* Interrupt Group of External Interrupt Combiner for UART */
+#define EXYNOS4210_UART_INT_GRP 26
+
+/* External GIC */
+#define EXYNOS4210_EXT_GIC_CPU_BASE_ADDR 0x10480000
+#define EXYNOS4210_EXT_GIC_DIST_BASE_ADDR 0x10490000
+
+/* Combiner */
+#define EXYNOS4210_EXT_COMBINER_BASE_ADDR 0x10440000
+#define EXYNOS4210_INT_COMBINER_BASE_ADDR 0x10448000
+
+/* SD/MMC host controllers SFR base addresses */
+#define EXYNOS4210_SDHC0_BASE_ADDR 0x12510000
+#define EXYNOS4210_SDHC1_BASE_ADDR 0x12520000
+#define EXYNOS4210_SDHC2_BASE_ADDR 0x12530000
+#define EXYNOS4210_SDHC3_BASE_ADDR 0x12540000
+
+/* PMU SFR base address */
+#define EXYNOS4210_PMU_BASE_ADDR 0x10020000
+
+/* Display controllers (FIMD) */
+#define EXYNOS4210_FIMD0_BASE_ADDR 0x11C00000
+#define EXYNOS4210_FIMD1_BASE_ADDR 0x12000000
+
+/* MALI400 (G3D) */
+#define EXYNOS4210_G3D_BASE_ADDR 0x13000000
+#define EXYNOS4210_G3D_PIXEL_PROC_0_IRQ 0
+#define EXYNOS4210_G3D_PIXEL_PROC_1_IRQ 1
+#define EXYNOS4210_G3D_PIXEL_PROC_2_IRQ 2
+#define EXYNOS4210_G3D_PIXEL_PROC_3_IRQ 3
+#define EXYNOS4210_G3D_GEOM_PROC_IRQ 4
+#define EXYNOS4210_G3D_PMU_IRQ 5
+#define EXYNOS4210_G3D_PPMMU0_IRQ 0
+#define EXYNOS4210_G3D_PPMMU1_IRQ 1
+#define EXYNOS4210_G3D_PPMMU2_IRQ 2
+#define EXYNOS4210_G3D_PPMMU3_IRQ 3
+#define EXYNOS4210_G3D_GPMMU_IRQ 4
+
+/* PPMU */
+#define EXYNOS4210_PPMU_CPU_BASE_ADDR 0x106C0000
+/* DMC */
+#define EXYNOS4210_DMC0_BASE_ADDR 0x10400000
+#define EXYNOS4210_DMC1_BASE_ADDR 0x10410000
+
+/* I2S */
+#define EXYNOS4210_I2S0_BASE_ADDR 0x03830000
+
+/* VirtIO BLK */
+#define EXYNOS4210_VIRTIO_BLK_BASE_ADDR 0x10AD0000
+/* VirtIO NET */
+#define EXYNOS4210_VIRTIO_NET_BASE_ADDR 0x10AC0000
+
+/* pl050 ps/2 interface */
+#define EXYNOS4210_PL050_BASE_ADDR 0x12E30000
+
+static uint8_t chipid_and_omr[TARGET_PAGE_SIZE] = { 0x11, 0x02, 0x21, 0x43,
+ 0x09, 0x00, 0x00, 0x00 };
+
+void maru_arm_write_secondary(CPUARMState *env,
+ const struct arm_boot_info *info)
+{
+ int n;
+ uint32_t smpboot[] = {
+ 0xe59f3024, /* ldr r3, External gic_cpu_if */
+ 0xe59f2024, /* ldr r2, Internal gic_cpu_if */
+ 0xe59f0024, /* ldr r0, startaddr */
+ 0xe3a01001, /* mov r1, #1 */
+ 0xe5821000, /* str r1, [r2] */
+ 0xe5831000, /* str r1, [r3] */
+ 0xe320f003, /* wfi */
+ 0xe5901000, /* ldr r1, [r0] */
+ 0xe1110001, /* tst r1, r1 */
+ 0x0afffffb, /* beq <wfi> */
+ 0xe12fff11, /* bx r1 */
+ EXYNOS4210_EXT_GIC_CPU_BASE_ADDR,
+ 0, /* gic_cpu_if: base address of Internal GIC CPU interface */
+ 0 /* bootreg: Boot register address is held here */
+ };
+ smpboot[ARRAY_SIZE(smpboot) - 1] = info->smp_bootreg_addr;
+ smpboot[ARRAY_SIZE(smpboot) - 2] = info->gic_cpu_if_addr;
+ for (n = 0; n < ARRAY_SIZE(smpboot); n++) {
+ smpboot[n] = tswap32(smpboot[n]);
+ }
+ rom_add_blob_fixed("smpboot", smpboot, sizeof(smpboot),
+ info->smp_loader_start);
+}
+
+Exynos4210State *maru_arm_soc_init(MemoryRegion *system_mem,
+ unsigned long ram_size)
+{
+ qemu_irq cpu_irq[4];
+ int n;
+ Exynos4210State *s = g_new(Exynos4210State, 1);
+ qemu_irq *irqp;
+ qemu_irq gate_irq[EXYNOS4210_IRQ_GATE_NINPUTS];
+ unsigned long mem_size;
+ DeviceState *dev;
+ SysBusDevice *busdev;
+
+ for (n = 0; n < EXYNOS4210_NCPUS; n++) {
+ s->env[n] = cpu_init("cortex-a9");
+ if (!s->env[n]) {
+ fprintf(stderr, "Unable to find CPU %d definition\n", n);
+ exit(1);
+ }
+ /* Create PIC controller for each processor instance */
+ irqp = arm_pic_init_cpu(s->env[n]);
+
+ /*
+ * Get GICs gpio_in cpu_irq to connect a combiner to them later.
+ * Use only IRQ for a while.
+ */
+ cpu_irq[n] = irqp[ARM_PIC_CPU_IRQ];
+ }
+
+ /*** IRQs ***/
+
+ s->irq_table = exynos4210_init_irq(&s->irqs);
+
+ /* IRQ Gate */
+ dev = qdev_create(NULL, "exynos4210.irq_gate");
+ qdev_prop_set_uint32(dev, "n_out", EXYNOS4210_NCPUS);
+ qdev_prop_set_uint32(dev, "n_in", EXYNOS4210_IRQ_GATE_NINPUTS);
+ qdev_init_nofail(dev);
+ /* Get IRQ Gate input in gate_irq */
+ for (n = 0; n < EXYNOS4210_IRQ_GATE_NINPUTS; n++) {
+ gate_irq[n] = qdev_get_gpio_in(dev, n);
+ }
+ busdev = sysbus_from_qdev(dev);
+ /* Connect IRQ Gate output to cpu_irq */
+ for (n = 0; n < EXYNOS4210_NCPUS; n++) {
+ sysbus_connect_irq(busdev, n, cpu_irq[n]);
+ }
+
+ /* Private memory region and Internal GIC */
+ dev = qdev_create(NULL, "a9mpcore_priv");
+ qdev_prop_set_uint32(dev, "num-cpu", EXYNOS4210_NCPUS);
+ qdev_init_nofail(dev);
+ busdev = sysbus_from_qdev(dev);
+ sysbus_mmio_map(busdev, 0, EXYNOS4210_SMP_PRIVATE_BASE_ADDR);
+ for (n = 0; n < EXYNOS4210_NCPUS; n++) {
+ sysbus_connect_irq(busdev, n, gate_irq[n * 4]);
+ }
+ for (n = 0; n < EXYNOS4210_INT_GIC_NIRQ; n++) {
+ s->irqs.int_gic_irq[n] = qdev_get_gpio_in(dev, n);
+ }
+
+ /* Cache controller */
+ sysbus_create_simple("l2x0", EXYNOS4210_L2X0_BASE_ADDR, NULL);
+
+ /* External GIC */
+ dev = qdev_create(NULL, "exynos4210.gic");
+ qdev_prop_set_uint32(dev, "num-cpu", EXYNOS4210_NCPUS);
+ qdev_init_nofail(dev);
+ busdev = sysbus_from_qdev(dev);
+ /* Map CPU interface */
+ sysbus_mmio_map(busdev, 0, EXYNOS4210_EXT_GIC_CPU_BASE_ADDR);
+ /* Map Distributer interface */
+ sysbus_mmio_map(busdev, 1, EXYNOS4210_EXT_GIC_DIST_BASE_ADDR);
+ for (n = 0; n < EXYNOS4210_NCPUS; n++) {
+ sysbus_connect_irq(busdev, n, gate_irq[n * 4 + 1]);
+ }
+ for (n = 0; n < EXYNOS4210_EXT_GIC_NIRQ; n++) {
+ s->irqs.ext_gic_irq[n] = qdev_get_gpio_in(dev, n);
+ }
+
+ /* Internal Interrupt Combiner */
+ dev = qdev_create(NULL, "exynos4210.combiner");
+ qdev_init_nofail(dev);
+ busdev = sysbus_from_qdev(dev);
+ for (n = 0; n < EXYNOS4210_MAX_INT_COMBINER_OUT_IRQ; n++) {
+ sysbus_connect_irq(busdev, n, s->irqs.int_gic_irq[n]);
+ }
+ exynos4210_combiner_get_gpioin(&s->irqs, dev, 0);
+ sysbus_mmio_map(busdev, 0, EXYNOS4210_INT_COMBINER_BASE_ADDR);
+
+ /* External Interrupt Combiner */
+ dev = qdev_create(NULL, "exynos4210.combiner");
+ qdev_prop_set_uint32(dev, "external", 1);
+ qdev_init_nofail(dev);
+ busdev = sysbus_from_qdev(dev);
+ for (n = 0; n < EXYNOS4210_MAX_INT_COMBINER_OUT_IRQ; n++) {
+ sysbus_connect_irq(busdev, n, s->irqs.ext_gic_irq[n]);
+ }
+ exynos4210_combiner_get_gpioin(&s->irqs, dev, 1);
+ sysbus_mmio_map(busdev, 0, EXYNOS4210_EXT_COMBINER_BASE_ADDR);
+
+ /* Initialize board IRQs. */
+ exynos4210_init_board_irqs(&s->irqs);
+
+ /*** Memory ***/
+
+ /* Chip-ID and OMR */
+ memory_region_init_ram_ptr(&s->chipid_mem, "exynos4210.chipid",
+ sizeof(chipid_and_omr), chipid_and_omr);
+ memory_region_set_readonly(&s->chipid_mem, true);
+ vmstate_register_ram_global(&s->chipid_mem);
+ memory_region_add_subregion(system_mem, EXYNOS4210_CHIPID_ADDR,
+ &s->chipid_mem);
+
+ /* Internal ROM */
+ memory_region_init_ram(&s->irom_mem, "exynos4210.irom",
+ EXYNOS4210_IROM_SIZE);
+ memory_region_set_readonly(&s->irom_mem, true);
+ vmstate_register_ram_global(&s->irom_mem);
+ memory_region_add_subregion(system_mem, EXYNOS4210_IROM_BASE_ADDR,
+ &s->irom_mem);
+ /* mirror of iROM */
+ memory_region_init_alias(&s->irom_alias_mem, "exynos4210.irom_alias",
+ &s->irom_mem,
+ 0,
+ EXYNOS4210_IROM_SIZE);
+ memory_region_set_readonly(&s->irom_alias_mem, true);
+ memory_region_add_subregion(system_mem, EXYNOS4210_IROM_MIRROR_BASE_ADDR,
+ &s->irom_alias_mem);
+
+ /* Internal RAM */
+ memory_region_init_ram(&s->iram_mem, "exynos4210.iram",
+ EXYNOS4210_IRAM_SIZE);
+ vmstate_register_ram_global(&s->iram_mem);
+ memory_region_add_subregion(system_mem, EXYNOS4210_IRAM_BASE_ADDR,
+ &s->iram_mem);
+
+ /* DRAM */
+ mem_size = ram_size;
+ if (mem_size > EXYNOS4210_DRAM_MAX_SIZE) {
+ memory_region_init_ram(&s->dram1_mem, "exynos4210.dram1",
+ mem_size - EXYNOS4210_DRAM_MAX_SIZE);
+ vmstate_register_ram_global(&s->dram1_mem);
+ memory_region_add_subregion(system_mem, EXYNOS4210_DRAM1_BASE_ADDR,
+ &s->dram1_mem);
+ mem_size = EXYNOS4210_DRAM_MAX_SIZE;
+ }
+ memory_region_init_ram(&s->dram0_mem, "exynos4210.dram0", mem_size);
+ vmstate_register_ram_global(&s->dram0_mem);
+ memory_region_add_subregion(system_mem, EXYNOS4210_DRAM0_BASE_ADDR,
+ &s->dram0_mem);
+
+ /* Audio Subsystem Internal Memory */
+ memory_region_init_ram(&s->audss_intmem, "exynos4210.audss",
+ EXYNOS4210_AUDSS_INTMEM_SIZE);
+ vmstate_register_ram_global(&s->audss_intmem);
+ memory_region_add_subregion(system_mem, EXYNOS4210_AUDSS_INTMEM_BASE_ADDR,
+ &s->audss_intmem);
+
+ /*** Clock devices ***/
+
+ /* PMU. Must be initialized before CMU.
+ * The only reason of existence at the moment is that secondary CPU boot
+ * loader uses PMU INFORM5 register as a holding pen.
+ */
+ sysbus_create_simple("maru_arm.pmu", EXYNOS4210_PMU_BASE_ADDR, NULL);
+
+ /* CMUs */
+ exynos4210_cmu_create(EXYNOS4210_CMU_LEFTBUS_BASE_ADDR,
+ EXYNOS4210_CMU_LEFTBUS);
+ exynos4210_cmu_create(EXYNOS4210_CMU_RIGHTBUS_BASE_ADDR,
+ EXYNOS4210_CMU_RIGHTBUS);
+ exynos4210_cmu_create(EXYNOS4210_CMU_TOP_BASE_ADDR, EXYNOS4210_CMU_TOP);
+ exynos4210_cmu_create(EXYNOS4210_CMU_DMC_BASE_ADDR, EXYNOS4210_CMU_DMC);
+ exynos4210_cmu_create(EXYNOS4210_CMU_CPU_BASE_ADDR, EXYNOS4210_CMU_CPU);
+
+ /* PWM */
+ sysbus_create_varargs("exynos4210.pwm", EXYNOS4210_PWM_BASE_ADDR,
+ s->irq_table[exynos4210_get_irq(22, 0)],
+ s->irq_table[exynos4210_get_irq(22, 1)],
+ s->irq_table[exynos4210_get_irq(22, 2)],
+ s->irq_table[exynos4210_get_irq(22, 3)],
+ s->irq_table[exynos4210_get_irq(22, 4)],
+ NULL);
+
+ /* RTC */
+ sysbus_create_varargs("exynos4210.rtc", EXYNOS4210_RTC_BASE_ADDR,
+ s->irq_table[exynos4210_get_irq(23, 0)],
+ s->irq_table[exynos4210_get_irq(23, 1)],
+ NULL);
+
+ /* Multi Core Timer */
+ dev = qdev_create(NULL, "exynos4210.mct");
+ qdev_init_nofail(dev);
+ busdev = sysbus_from_qdev(dev);
+ for (n = 0; n < 4; n++) {
+ /* Connect global timer interrupts to Combiner gpio_in */
+ sysbus_connect_irq(busdev, n,
+ s->irq_table[exynos4210_get_irq(1, 4 + n)]);
+ }
+ /* Connect local timer interrupts to Combiner gpio_in */
+ sysbus_connect_irq(busdev, 4,
+ s->irq_table[exynos4210_get_irq(51, 0)]);
+ sysbus_connect_irq(busdev, 5,
+ s->irq_table[exynos4210_get_irq(35, 3)]);
+ sysbus_mmio_map(busdev, 0, EXYNOS4210_MCT_BASE_ADDR);
+
+ /*** I2C ***/
+ for (n = 0; n < EXYNOS4210_I2C_NUMBER; n++) {
+ uint32_t addr = EXYNOS4210_I2C_BASE_ADDR + EXYNOS4210_I2C_SHIFT * n;
+ qemu_irq i2c_irq;
+
+ if (n < 8) {
+ i2c_irq = s->irq_table[exynos4210_get_irq(EXYNOS4210_I2C_INTG, n)];
+ } else {
+ i2c_irq = s->irq_table[exynos4210_get_irq(EXYNOS4210_HDMI_INTG, 1)];
+ }
+
+ dev = qdev_create(NULL, "exynos4210.i2c");
+ qdev_init_nofail(dev);
+ busdev = sysbus_from_qdev(dev);
+ sysbus_connect_irq(busdev, 0, i2c_irq);
+ sysbus_mmio_map(busdev, 0, addr);
+ s->i2c_if[n] = (i2c_bus *)qdev_get_child_bus(dev, "i2c");
+ }
+
+ /*** UARTs ***/
+ exynos4210_uart_create(EXYNOS4210_UART0_BASE_ADDR,
+ EXYNOS4210_UART0_FIFO_SIZE, 0, NULL,
+ s->irq_table[exynos4210_get_irq(EXYNOS4210_UART_INT_GRP, 0)]);
+
+ exynos4210_uart_create(EXYNOS4210_UART1_BASE_ADDR,
+ EXYNOS4210_UART1_FIFO_SIZE, 1, NULL,
+ s->irq_table[exynos4210_get_irq(EXYNOS4210_UART_INT_GRP, 1)]);
+
+ exynos4210_uart_create(EXYNOS4210_UART2_BASE_ADDR,
+ EXYNOS4210_UART2_FIFO_SIZE, 2, NULL,
+ s->irq_table[exynos4210_get_irq(EXYNOS4210_UART_INT_GRP, 2)]);
+
+ exynos4210_uart_create(EXYNOS4210_UART3_BASE_ADDR,
+ EXYNOS4210_UART3_FIFO_SIZE, 3, NULL,
+ s->irq_table[exynos4210_get_irq(EXYNOS4210_UART_INT_GRP, 3)]);
+
+
+ /*** Display controller (FIMD) ***/
+ sysbus_create_varargs("exynos4210.fimd", EXYNOS4210_FIMD0_BASE_ADDR,
+ s->irq_table[exynos4210_get_irq(11, 0)],
+ s->irq_table[exynos4210_get_irq(11, 1)],
+ s->irq_table[exynos4210_get_irq(11, 2)],
+ NULL);
+
+ /*** GPU openGLES passthrough device ***/
+#ifdef CONFIG_BUILD_GLES
+ gles2_init(first_cpu);
+#endif
+
+ /* I2S0 */
+ s->i2s_bus[0] = exynos4210_i2s_bus_new("exynos4210.i2s",
+ EXYNOS4210_I2S0_BASE_ADDR,
+ s->irqs.ext_gic_irq[97]);
+
+ sysbus_create_simple(VIRTIO_MMIO_TRANSPORT, EXYNOS4210_VIRTIO_BLK_BASE_ADDR,
+ s->irq_table[exynos4210_get_irq(37, 3)]);
+ sysbus_create_simple(VIRTIO_MMIO_TRANSPORT, EXYNOS4210_VIRTIO_NET_BASE_ADDR,
+ s->irq_table[exynos4210_get_irq(37, 2)]);
+
+ /* PL050 PS/2 if keyboard */
+ sysbus_create_simple("pl050_keyboard", EXYNOS4210_PL050_BASE_ADDR,
+ s->irq_table[exynos4210_get_irq(28, 2)]);
+
+ return s;
+}
}
}
-static void maru_arm_machine_init(ram_addr_t ram_size,
- const char *boot_device,
- const char *kernel_filename,
- const char *kernel_cmdline,
- const char *initrd_filename,
- const char *cpu_model)
-{
-}
-
-static void maru_common_init(ram_addr_t ram_size,
- const char *boot_device,
- const char *kernel_filename,
- const char *kernel_cmdline,
- const char *initrd_filename,
- const char *cpu_model)
-{
-// prepare for universal virtual board...
-#if defined(TARGET_I386)
-#elif defined(TARGET_ARM)
-#endif
-}
-
static void maru_x86_board_init(ram_addr_t ram_size,
const char *boot_device,
const char *kernel_filename,
ram_size, boot_device,
kernel_filename, kernel_cmdline,
initrd_filename, cpu_model, 1, 1);
- maru_common_init(ram_size, boot_device, kernel_filename,
- kernel_cmdline, initrd_filename, cpu_model);
-}
-static void maru_arm_board_init(ram_addr_t ram_size,
- const char *boot_device,
- const char *kernel_filename,
- const char *kernel_cmdline,
- const char *initrd_filename,
- const char *cpu_model)
-{
- maru_arm_machine_init(ram_size, boot_device, kernel_filename,
- kernel_cmdline, initrd_filename, cpu_model);
- maru_common_init(ram_size, boot_device, kernel_filename,
- kernel_cmdline, initrd_filename, cpu_model);
}
static QEMUMachine maru_x86_machine = {
.max_cpus = 255,
};
-static QEMUMachine maru_arm_machine = {
- .name = "maru-arm-machine",
- .desc = "maru board(ARM)",
- .init = maru_arm_board_init,
- .max_cpus = 255,
-};
-
static void maru_machine_init(void)
{
-#if defined(TARGET_I386)
qemu_register_machine(&maru_x86_machine);
-#elif defined(TARGET_ARM)
- qemu_register_machine(&maru_arm_machine);
-#else
-#error
-#endif
}
machine_init(maru_machine_init);
projects / sdk / emulator / qemu.git / commitdiff