crypto: qat - set COMPRESSION capability for QAT GEN2

Enhance the device capability detection for QAT GEN2 devices to detect if
a device supports the compression service.

This is done by checking both the fuse and the strap registers for c62x
and c3xxx and only the fuse register for dh895xcc.

Signed-off-by: Giovanni Cabiddu <giovanni.cabiddu@intel.com>
Signed-off-by: Marco Chiappero <marco.chiappero@intel.com>
Reviewed-by: Fiona Trahe <fiona.trahe@intel.com>
Reviewed-by: Marco Chiappero <marco.chiappero@intel.com>
Signed-off-by: Herbert Xu <herbert@gondor.apana.org.au>

diff --git a/drivers/crypto/qat/qat_common/adf_gen2_hw_data.c b/drivers/crypto/qat/qat_common/adf_gen2_hw_data.c
index 3ea26f2..688dd6f 100644 (file)
--- a/drivers/crypto/qat/qat_common/adf_gen2_hw_data.c
+++ b/drivers/crypto/qat/qat_common/adf_gen2_hw_data.c
@@ -212,7 +212,8 @@ u32 adf_gen2_get_accel_cap(struct adf_accel_dev *accel_dev)
        u32 capabilities = ICP_ACCEL_CAPABILITIES_CRYPTO_SYMMETRIC |
                           ICP_ACCEL_CAPABILITIES_CRYPTO_ASYMMETRIC |
                           ICP_ACCEL_CAPABILITIES_AUTHENTICATION |
-                          ICP_ACCEL_CAPABILITIES_CIPHER;
+                          ICP_ACCEL_CAPABILITIES_CIPHER |
+                          ICP_ACCEL_CAPABILITIES_COMPRESSION;
 
        /* Read accelerator capabilities mask */
        pci_read_config_dword(pdev, ADF_DEVICE_LEGFUSE_OFFSET, &legfuses);
@@ -228,10 +229,15 @@ u32 adf_gen2_get_accel_cap(struct adf_accel_dev *accel_dev)
                capabilities &= ~ICP_ACCEL_CAPABILITIES_AUTHENTICATION;
                capabilities &= ~ICP_ACCEL_CAPABILITIES_CIPHER;
        }
+       if (legfuses & ICP_ACCEL_MASK_COMPRESS_SLICE)
+               capabilities &= ~ICP_ACCEL_CAPABILITIES_COMPRESSION;
 
        if ((straps | fuses) & ADF_POWERGATE_PKE)
                capabilities &= ~ICP_ACCEL_CAPABILITIES_CRYPTO_ASYMMETRIC;
 
+       if ((straps | fuses) & ADF_POWERGATE_DC)
+               capabilities &= ~ICP_ACCEL_CAPABILITIES_COMPRESSION;
+
        return capabilities;
 }
 EXPORT_SYMBOL_GPL(adf_gen2_get_accel_cap);

diff --git a/drivers/crypto/qat/qat_common/adf_gen2_hw_data.h b/drivers/crypto/qat/qat_common/adf_gen2_hw_data.h
index 448c97f..7c2c173 100644 (file)
--- a/drivers/crypto/qat/qat_common/adf_gen2_hw_data.h
+++ b/drivers/crypto/qat/qat_common/adf_gen2_hw_data.h
@@ -113,6 +113,7 @@ do { \
        (ADF_ARB_REG_SLOT * (index)), value)
 
 /* Power gating */
+#define ADF_POWERGATE_DC               BIT(23)
 #define ADF_POWERGATE_PKE              BIT(24)
 
 /* WDT timers

diff --git a/drivers/crypto/qat/qat_dh895xcc/adf_dh895xcc_hw_data.c b/drivers/crypto/qat/qat_dh895xcc/adf_dh895xcc_hw_data.c
index 27d4cab..2d18279 100644 (file)
--- a/drivers/crypto/qat/qat_dh895xcc/adf_dh895xcc_hw_data.c
+++ b/drivers/crypto/qat/qat_dh895xcc/adf_dh895xcc_hw_data.c
@@ -69,6 +69,8 @@ static u32 get_accel_cap(struct adf_accel_dev *accel_dev)
                capabilities &= ~ICP_ACCEL_CAPABILITIES_CRYPTO_ASYMMETRIC;
        if (legfuses & ICP_ACCEL_MASK_AUTH_SLICE)
                capabilities &= ~ICP_ACCEL_CAPABILITIES_AUTHENTICATION;
+       if (legfuses & ICP_ACCEL_MASK_COMPRESS_SLICE)
+               capabilities &= ~ICP_ACCEL_CAPABILITIES_COMPRESSION;
 
        return capabilities;
 }