ARM: dts: socfpga: Move sdmmc-ecc node to Arria 10 dts
authorPaweł Anikiel <pan@semihalf.com>
Fri, 3 Jun 2022 09:23:51 +0000 (11:23 +0200)
committerDinh Nguyen <dinguyen@kernel.org>
Tue, 14 Jun 2022 15:44:59 +0000 (10:44 -0500)
The ecc manager is a part of the Arria 10 SoC, move it to the correct
dts.

Signed-off-by: Paweł Anikiel <pan@semihalf.com>
Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Signed-off-by: Dinh Nguyen <dinguyen@kernel.org>
arch/arm/boot/dts/socfpga_arria10.dtsi
arch/arm/boot/dts/socfpga_arria10_mercury_aa1.dtsi

index 26bda25..4370e3c 100644 (file)
                                             <37 IRQ_TYPE_LEVEL_HIGH>;
                        };
 
+                       sdmmca-ecc@ff8c2c00 {
+                               compatible = "altr,socfpga-sdmmc-ecc";
+                               reg = <0xff8c2c00 0x400>;
+                               altr,ecc-parent = <&mmc>;
+                               interrupts = <15 IRQ_TYPE_LEVEL_HIGH>,
+                                            <47 IRQ_TYPE_LEVEL_HIGH>,
+                                            <16 IRQ_TYPE_LEVEL_HIGH>,
+                                            <48 IRQ_TYPE_LEVEL_HIGH>;
+                       };
+
                        dma-ecc@ff8c8000 {
                                compatible = "altr,socfpga-dma-ecc";
                                reg = <0xff8c8000 0x400>;
index 4b21351..b0d2010 100644 (file)
        };
 };
 
-&eccmgr {
-       sdmmca-ecc@ff8c2c00 {
-               compatible = "altr,socfpga-sdmmc-ecc";
-               reg = <0xff8c2c00 0x400>;
-               altr,ecc-parent = <&mmc>;
-               interrupts = <15 IRQ_TYPE_LEVEL_HIGH>,
-                            <47 IRQ_TYPE_LEVEL_HIGH>,
-                            <16 IRQ_TYPE_LEVEL_HIGH>,
-                            <48 IRQ_TYPE_LEVEL_HIGH>;
-       };
-};
-
 &gmac0 {
        phy-mode = "rgmii";
        phy-addr = <0xffffffff>; /* probe for phy addr */