class FoldingSetNodeID;
class MDNode;
-class MIRFormatter;
class raw_ostream;
class MachineFunction;
class ModuleSlotTracker;
/// @{
void print(raw_ostream &OS, ModuleSlotTracker &MST,
SmallVectorImpl<StringRef> &SSNs, const LLVMContext &Context,
- const MachineFrameInfo *MFI, const TargetInstrInfo *TII,
- const MIRFormatter *MIRF) const;
+ const MachineFrameInfo *MFI, const TargetInstrInfo *TII) const;
/// @}
friend bool operator==(const MachineMemOperand &LHS,
virtual Optional<ParamLoadedValue> describeLoadedValue(const MachineInstr &MI,
Register Reg) const;
+ /// Return MIR formatter to format/parse MIR operands. Target can override
+ /// this virtual function and return target specific MIR formatter.
+ virtual const MIRFormatter *getMIRFormatter() const {
+ if (!Formatter.get())
+ Formatter = std::make_unique<MIRFormatter>();
+ return Formatter.get();
+ }
+
private:
mutable std::unique_ptr<MIRFormatter> Formatter;
unsigned CallFrameSetupOpcode, CallFrameDestroyOpcode;
class MCRegisterInfo;
class MCSubtargetInfo;
class MCSymbol;
-class MIRFormatter;
class raw_pwrite_stream;
class PassManagerBuilder;
struct PerFunctionMIParsingState;
std::unique_ptr<const MCRegisterInfo> MRI;
std::unique_ptr<const MCInstrInfo> MII;
std::unique_ptr<const MCSubtargetInfo> STI;
- std::unique_ptr<const MIRFormatter> MIRF;
unsigned RequireStructuredCFG : 1;
unsigned O0WantsFastISel : 1;
return nullptr;
}
- /// Return MIR formatter to format/parse MIR operands. Target can override
- /// this virtual function and return target specific MIR formatter.
- virtual const MIRFormatter *getMIRFormatter() const { return MIRF.get(); }
-
bool requiresStructuredCFG() const { return RequireStructuredCFG; }
void setRequiresStructuredCFG(bool Value) { RequireStructuredCFG = Value; }
} else
return parseTypedImmediateOperand(Dest);
case MIToken::dot: {
- if (const auto *Formatter = MF.getTarget().getMIRFormatter()) {
+ const auto *TII = MF.getSubtarget().getInstrInfo();
+ if (const auto *Formatter = TII->getMIRFormatter()) {
return parseTargetImmMnemonic(OpCode, OpIdx, Dest, *Formatter);
}
LLVM_FALLTHROUGH;
break;
case MIToken::kw_custom: {
lex();
- if (const auto *Formatter = MF.getTarget().getMIRFormatter()) {
+ const auto *TII = MF.getSubtarget().getInstrInfo();
+ if (const auto *Formatter = TII->getMIRFormatter()) {
if (Formatter->parseCustomPseudoSourceValue(
Token.stringValue(), MF, PFS, PSV,
[this](StringRef::iterator Loc, const Twine &Msg) -> bool {
const auto *TRI = SubTarget.getRegisterInfo();
assert(TRI && "Expected target register info");
const auto *TII = SubTarget.getInstrInfo();
- const auto *MIRF = MF->getTarget().getMIRFormatter();
assert(TII && "Expected target instruction info");
if (MI.isCFIInstruction())
assert(MI.getNumOperands() == 1 && "Expected 1 operand in CFI instruction");
for (const auto *Op : MI.memoperands()) {
if (NeedComma)
OS << ", ";
- Op->print(OS, MST, SSNs, Context, &MFI, TII, MIRF);
+ Op->print(OS, MST, SSNs, Context, &MFI, TII);
NeedComma = true;
}
}
const TargetRegisterInfo *&TRI,
const MachineRegisterInfo *&MRI,
const TargetIntrinsicInfo *&IntrinsicInfo,
- const TargetInstrInfo *&TII,
- const MIRFormatter *&MIRF) {
+ const TargetInstrInfo *&TII) {
if (const MachineFunction *MF = getMFIfAvailable(MI)) {
TRI = MF->getSubtarget().getRegisterInfo();
MRI = &MF->getRegInfo();
IntrinsicInfo = MF->getTarget().getIntrinsicInfo();
TII = MF->getSubtarget().getInstrInfo();
- MIRF = MF->getTarget().getMIRFormatter();
}
}
const TargetRegisterInfo *TRI = nullptr;
const MachineRegisterInfo *MRI = nullptr;
const TargetIntrinsicInfo *IntrinsicInfo = nullptr;
- const MIRFormatter *MIRF = nullptr;
- tryToGetTargetInfo(*this, TRI, MRI, IntrinsicInfo, TII, MIRF);
+ tryToGetTargetInfo(*this, TRI, MRI, IntrinsicInfo, TII);
if (isCFIInstruction())
assert(getNumOperands() == 1 && "Expected 1 operand in CFI instruction");
for (const MachineMemOperand *Op : memoperands()) {
if (NeedComma)
OS << ", ";
- Op->print(OS, MST, SSNs, *Context, MFI, TII, MIRF);
+ Op->print(OS, MST, SSNs, *Context, MFI, TII);
NeedComma = true;
}
}
}
case MachineOperand::MO_Immediate: {
const MIRFormatter *Formatter = nullptr;
- if (const MachineFunction *MF = getMFIfAvailable(*this))
- Formatter = MF->getTarget().getMIRFormatter();
+ if (const MachineFunction *MF = getMFIfAvailable(*this)) {
+ const auto *TII = MF->getSubtarget().getInstrInfo();
+ assert(TII && "expected instruction info");
+ Formatter = TII->getMIRFormatter();
+ }
if (Formatter)
Formatter->printImm(OS, *getParent(), OpIdx, getImm());
else
SmallVectorImpl<StringRef> &SSNs,
const LLVMContext &Context,
const MachineFrameInfo *MFI,
- const TargetInstrInfo *TII,
- const MIRFormatter* MIRF) const {
+ const TargetInstrInfo *TII) const {
OS << '(';
if (isVolatile())
OS << "volatile ";
OS, cast<ExternalSymbolPseudoSourceValue>(PVal)->getSymbol());
break;
default: {
+ const MIRFormatter *Formatter = TII->getMIRFormatter();
// FIXME: This is not necessarily the correct MIR serialization format for
// a custom pseudo source value, but at least it allows
// -print-machineinstrs to work on a target with custom pseudo source
// values.
OS << "custom \"";
- if (MIRF)
- MIRF->printCustomPseudoSourceValue(OS, MST, *PVal);
- else
- PVal->printCustom(OS);
+ Formatter->printCustomPseudoSourceValue(OS, MST, *PVal);
OS << '\"';
break;
}
if (MF)
MST.incorporateFunction(MF->getFunction());
SmallVector<StringRef, 0> SSNs;
- MMO.print(OS, MST, SSNs, Ctx, MFI, TII,
- MF ? MF->getTarget().getMIRFormatter() : nullptr);
+ MMO.print(OS, MST, SSNs, Ctx, MFI, TII);
}
static void printMemOperand(raw_ostream &OS, const MachineMemOperand &MMO,
#include "llvm/Target/TargetMachine.h"
#include "llvm/Analysis/TargetTransformInfo.h"
-#include "llvm/CodeGen/MIRFormatter.h"
#include "llvm/IR/Function.h"
#include "llvm/IR/GlobalAlias.h"
#include "llvm/IR/GlobalValue.h"
: TheTarget(T), DL(DataLayoutString), TargetTriple(TT), TargetCPU(CPU),
TargetFS(FS), AsmInfo(nullptr), MRI(nullptr), MII(nullptr), STI(nullptr),
RequireStructuredCFG(false), O0WantsFastISel(false),
- DefaultOptions(Options), Options(Options) {
- MIRF = std::make_unique<MIRFormatter>();
-}
+ DefaultOptions(Options), Options(Options) {}
TargetMachine::~TargetMachine() = default;