drm/amdgpu: add pause DPG mode for VCN3.0

Add vcn_v3_0_pause_dpg_mode to pause/unpause DPG mode for VCN3.0

V2: update description.

Signed-off-by: Boyuan Zhang <boyuan.zhang@amd.com>
Reviewed-by: James Zhu <james.zhu@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>

diff --git a/drivers/gpu/drm/amd/amdgpu/vcn_v3_0.c b/drivers/gpu/drm/amd/amdgpu/vcn_v3_0.c
index c1aaa94..f47136d 100644 (file)
--- a/drivers/gpu/drm/amd/amdgpu/vcn_v3_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/vcn_v3_0.c
@@ -53,6 +53,8 @@ static void vcn_v3_0_set_enc_ring_funcs(struct amdgpu_device *adev);
 static void vcn_v3_0_set_irq_funcs(struct amdgpu_device *adev);
 static int vcn_v3_0_set_powergating_state(void *handle,
                        enum amd_powergating_state state);
+static int vcn_v3_0_pause_dpg_mode(struct amdgpu_device *adev,
+                       int inst_idx, struct dpg_pause_state *new_state);
 
 static int amdgpu_ih_clientid_vcns[] = {
        SOC15_IH_CLIENTID_VCN,
@@ -189,6 +191,9 @@ static int vcn_v3_0_sw_init(void *handle)
                }
        }
 
+       if (adev->pg_flags & AMD_PG_SUPPORT_VCN_DPG)
+               adev->vcn.pause_dpg_mode = vcn_v3_0_pause_dpg_mode;
+
        return 0;
 }
 
@@ -1232,6 +1237,67 @@ static int vcn_v3_0_stop(struct amdgpu_device *adev)
        return 0;
 }
 
+static int vcn_v3_0_pause_dpg_mode(struct amdgpu_device *adev,
+                  int inst_idx, struct dpg_pause_state *new_state)
+{
+       struct amdgpu_ring *ring;
+       uint32_t reg_data = 0;
+       int ret_code;
+
+       /* pause/unpause if state is changed */
+       if (adev->vcn.inst[inst_idx].pause_state.fw_based != new_state->fw_based) {
+               DRM_DEBUG("dpg pause state changed %d -> %d",
+                       adev->vcn.inst[inst_idx].pause_state.fw_based,  new_state->fw_based);
+               reg_data = RREG32_SOC15(VCN, inst_idx, mmUVD_DPG_PAUSE) &
+                       (~UVD_DPG_PAUSE__NJ_PAUSE_DPG_ACK_MASK);
+
+               if (new_state->fw_based == VCN_DPG_STATE__PAUSE) {
+                       ret_code = 0;
+                       SOC15_WAIT_ON_RREG(VCN, inst_idx, mmUVD_POWER_STATUS, 0x1,
+                               UVD_POWER_STATUS__UVD_POWER_STATUS_MASK, ret_code);
+
+                       if (!ret_code) {
+                               /* pause DPG */
+                               reg_data |= UVD_DPG_PAUSE__NJ_PAUSE_DPG_REQ_MASK;
+                               WREG32_SOC15(VCN, inst_idx, mmUVD_DPG_PAUSE, reg_data);
+
+                               /* wait for ACK */
+                               SOC15_WAIT_ON_RREG(VCN, inst_idx, mmUVD_DPG_PAUSE,
+                                       UVD_DPG_PAUSE__NJ_PAUSE_DPG_ACK_MASK,
+                                       UVD_DPG_PAUSE__NJ_PAUSE_DPG_ACK_MASK, ret_code);
+
+                               /* Restore */
+                               ring = &adev->vcn.inst[inst_idx].ring_enc[0];
+                               WREG32_SOC15(VCN, inst_idx, mmUVD_RB_BASE_LO, ring->gpu_addr);
+                               WREG32_SOC15(VCN, inst_idx, mmUVD_RB_BASE_HI, upper_32_bits(ring->gpu_addr));
+                               WREG32_SOC15(VCN, inst_idx, mmUVD_RB_SIZE, ring->ring_size / 4);
+                               WREG32_SOC15(VCN, inst_idx, mmUVD_RB_RPTR, lower_32_bits(ring->wptr));
+                               WREG32_SOC15(VCN, inst_idx, mmUVD_RB_WPTR, lower_32_bits(ring->wptr));
+
+                               ring = &adev->vcn.inst[inst_idx].ring_enc[1];
+                               WREG32_SOC15(VCN, inst_idx, mmUVD_RB_BASE_LO2, ring->gpu_addr);
+                               WREG32_SOC15(VCN, inst_idx, mmUVD_RB_BASE_HI2, upper_32_bits(ring->gpu_addr));
+                               WREG32_SOC15(VCN, inst_idx, mmUVD_RB_SIZE2, ring->ring_size / 4);
+                               WREG32_SOC15(VCN, inst_idx, mmUVD_RB_RPTR2, lower_32_bits(ring->wptr));
+                               WREG32_SOC15(VCN, inst_idx, mmUVD_RB_WPTR2, lower_32_bits(ring->wptr));
+
+                               WREG32_SOC15(VCN, inst_idx, mmUVD_RBC_RB_WPTR,
+                                       RREG32_SOC15(VCN, inst_idx, mmUVD_SCRATCH2) & 0x7FFFFFFF);
+
+                               SOC15_WAIT_ON_RREG(VCN, inst_idx, mmUVD_POWER_STATUS,
+                                       UVD_PGFSM_CONFIG__UVDM_UVDU_PWR_ON, UVD_POWER_STATUS__UVD_POWER_STATUS_MASK, ret_code);
+                       }
+               } else {
+                       /* unpause dpg, no need to wait */
+                       reg_data &= ~UVD_DPG_PAUSE__NJ_PAUSE_DPG_REQ_MASK;
+                       WREG32_SOC15(VCN, inst_idx, mmUVD_DPG_PAUSE, reg_data);
+               }
+               adev->vcn.inst[inst_idx].pause_state.fw_based = new_state->fw_based;
+       }
+
+       return 0;
+}
+
 /**
  * vcn_v3_0_dec_ring_get_rptr - get read pointer
  *