drm/amd/pm: fulfill the missing enablement for vega12/vega20 L2H and H2L interrupts

The feature mask bit was not correctly cleared. Without that, the L2H
and H2L interrupts cannot be enabled.

Signed-off-by: Evan Quan <evan.quan@amd.com>
Acked-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>

diff --git a/drivers/gpu/drm/amd/pm/powerplay/hwmgr/vega12_thermal.c b/drivers/gpu/drm/amd/pm/powerplay/hwmgr/vega12_thermal.c
index ed3dff0..ae342c5 100644 (file)
--- a/drivers/gpu/drm/amd/pm/powerplay/hwmgr/vega12_thermal.c
+++ b/drivers/gpu/drm/amd/pm/powerplay/hwmgr/vega12_thermal.c
@@ -192,7 +192,9 @@ static int vega12_thermal_set_temperature_range(struct pp_hwmgr *hwmgr,
        val = REG_SET_FIELD(val, THM_THERMAL_INT_CTRL, THERM_IH_HW_ENA, 1);
        val = REG_SET_FIELD(val, THM_THERMAL_INT_CTRL, DIG_THERM_INTH, high);
        val = REG_SET_FIELD(val, THM_THERMAL_INT_CTRL, DIG_THERM_INTL, low);
-       val = val & (~THM_THERMAL_INT_CTRL__THERM_TRIGGER_MASK_MASK);
+       val &= ~THM_THERMAL_INT_CTRL__THERM_TRIGGER_MASK_MASK;
+       val &= ~THM_THERMAL_INT_CTRL__THERM_INTH_MASK_MASK;
+       val &= ~THM_THERMAL_INT_CTRL__THERM_INTL_MASK_MASK;
 
        WREG32_SOC15(THM, 0, mmTHM_THERMAL_INT_CTRL, val);
 

diff --git a/drivers/gpu/drm/amd/pm/powerplay/hwmgr/vega20_thermal.c b/drivers/gpu/drm/amd/pm/powerplay/hwmgr/vega20_thermal.c
index f4f4efd..e9737ca 100644 (file)
--- a/drivers/gpu/drm/amd/pm/powerplay/hwmgr/vega20_thermal.c
+++ b/drivers/gpu/drm/amd/pm/powerplay/hwmgr/vega20_thermal.c
@@ -263,7 +263,9 @@ static int vega20_thermal_set_temperature_range(struct pp_hwmgr *hwmgr,
        val = CGS_REG_SET_FIELD(val, THM_THERMAL_INT_CTRL, THERM_IH_HW_ENA, 1);
        val = CGS_REG_SET_FIELD(val, THM_THERMAL_INT_CTRL, DIG_THERM_INTH, high);
        val = CGS_REG_SET_FIELD(val, THM_THERMAL_INT_CTRL, DIG_THERM_INTL, low);
-       val = val & (~THM_THERMAL_INT_CTRL__THERM_TRIGGER_MASK_MASK);
+       val &= ~THM_THERMAL_INT_CTRL__THERM_TRIGGER_MASK_MASK;
+       val &= ~THM_THERMAL_INT_CTRL__THERM_INTH_MASK_MASK;
+       val &= ~THM_THERMAL_INT_CTRL__THERM_INTL_MASK_MASK;
 
        WREG32_SOC15(THM, 0, mmTHM_THERMAL_INT_CTRL, val);