arm64: dts: k3-am6: Add PCIe Root Complex DT node

Add PCIe Root Complex DT node.

Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com>
Signed-off-by: Tero Kristo <t-kristo@ti.com>

diff --git a/arch/arm64/boot/dts/ti/k3-am65-main.dtsi b/arch/arm64/boot/dts/ti/k3-am65-main.dtsi
index 3a6a97c..a7a3938 100644 (file)
--- a/arch/arm64/boot/dts/ti/k3-am65-main.dtsi
+++ b/arch/arm64/boot/dts/ti/k3-am65-main.dtsi
@@ -265,6 +265,21 @@
                #size-cells = <1>;
                ranges = <0x0 0x0 0x00100000 0x1c000>;
 
+               pcie0_mode: pcie-mode@4060 {
+                       compatible = "syscon";
+                       reg = <0x00004060 0x4>;
+               };
+
+               pcie1_mode: pcie-mode@4070 {
+                       compatible = "syscon";
+                       reg = <0x00004070 0x4>;
+               };
+
+               pcie_devid: pcie-devid@210 {
+                       compatible = "syscon";
+                       reg = <0x00000210 0x4>;
+               };
+
                serdes0_clk: serdes_clk@4080 {
                        compatible = "syscon";
                        reg = <0x00004080 0x4>;
@@ -431,4 +446,42 @@
                clocks = <&k3_clks 58 0>;
                clock-names = "gpio";
        };
+
+       pcie0_rc: pcie@5500000 {
+               compatible = "ti,am654-pcie-rc";
+               reg =  <0x0 0x5500000 0x0 0x1000>, <0x0 0x5501000 0x0 0x1000>, <0x0 0x10000000 0x0 0x2000>, <0x0 0x5506000 0x0 0x1000>;
+               reg-names = "app", "dbics", "config", "atu";
+               power-domains = <&k3_pds 120>;
+               #address-cells = <3>;
+               #size-cells = <2>;
+               ranges = <0x81000000 0 0          0x0 0x10020000 0 0x00010000
+                         0x82000000 0 0x10030000 0x0 0x10030000 0 0x07FD0000>;
+               ti,syscon-pcie-id = <&pcie_devid>;
+               ti,syscon-pcie-mode = <&pcie0_mode>;
+               bus-range = <0x0 0xff>;
+               num-viewport = <16>;
+               max-link-speed = <3>;
+               dma-coherent;
+               interrupts = <GIC_SPI 340 IRQ_TYPE_EDGE_RISING>;
+               msi-map = <0x0 &gic_its 0x0 0x10000>;
+       };
+
+       pcie1_rc: pcie@5600000 {
+               compatible = "ti,am654-pcie-rc";
+               reg =  <0x0 0x5600000 0x0 0x1000>, <0x0 0x5601000 0x0 0x1000>, <0x0 0x18000000 0x0 0x2000>, <0x0 0x5606000 0x0 0x1000>;
+               reg-names = "app", "dbics", "config", "atu";
+               power-domains = <&k3_pds 121>;
+               #address-cells = <3>;
+               #size-cells = <2>;
+               ranges = <0x81000000 0 0          0x0   0x18020000 0 0x00010000
+                         0x82000000 0 0x18030000 0x0   0x18030000 0 0x07FD0000>;
+               ti,syscon-pcie-id = <&pcie_devid>;
+               ti,syscon-pcie-mode = <&pcie1_mode>;
+               bus-range = <0x0 0xff>;
+               num-viewport = <16>;
+               max-link-speed = <3>;
+               dma-coherent;
+               interrupts = <GIC_SPI 355 IRQ_TYPE_EDGE_RISING>;
+               msi-map = <0x0 &gic_its 0x10000 0x10000>;
+       };
 };

diff --git a/arch/arm64/boot/dts/ti/k3-am65.dtsi b/arch/arm64/boot/dts/ti/k3-am65.dtsi
index f71c8f5..82edf10 100644 (file)
--- a/arch/arm64/boot/dts/ti/k3-am65.dtsi
+++ b/arch/arm64/boot/dts/ti/k3-am65.dtsi
@@ -69,6 +69,7 @@
                         <0x00 0x01000000 0x00 0x01000000 0x00 0x0af02400>, /* Most peripherals */
                         <0x00 0x30800000 0x00 0x30800000 0x00 0x0bc00000>, /* MAIN NAVSS */
                         <0x00 0x70000000 0x00 0x70000000 0x00 0x00200000>, /* MSMC SRAM */
+                        <0x00 0x10000000 0x00 0x10000000 0x00 0x10000000>, /* PCIe DAT */
                         /* MCUSS Range */
                         <0x00 0x28380000 0x00 0x28380000 0x00 0x03880000>,
                         <0x00 0x40200000 0x00 0x40200000 0x00 0x00900100>,