arm64/sysreg: Convert ID_AA64MMFR2_EL1 to automatic generation

Convert ID_AA64MMFR2_EL1 defines to automatic generation as per DDI0487H.a,
no functional changes.

Signed-off-by: Mark Brown <broonie@kernel.org>
Reviewed-by: Kristina Martsenko <kristina.martsenko@arm.com>
Link: https://lore.kernel.org/r/20220905225425.1871461-24-broonie@kernel.org
Signed-off-by: Catalin Marinas <catalin.marinas@arm.com>

diff --git a/arch/arm64/include/asm/sysreg.h b/arch/arm64/include/asm/sysreg.h
index 5dcd8df..62c5c59 100644 (file)
--- a/arch/arm64/include/asm/sysreg.h
+++ b/arch/arm64/include/asm/sysreg.h
@@ -199,8 +199,6 @@
 #define SYS_ID_AA64AFR0_EL1            sys_reg(3, 0, 0, 5, 4)
 #define SYS_ID_AA64AFR1_EL1            sys_reg(3, 0, 0, 5, 5)
 
-#define SYS_ID_AA64MMFR2_EL1           sys_reg(3, 0, 0, 7, 2)
-
 #define SYS_ACTLR_EL1                  sys_reg(3, 0, 1, 0, 1)
 #define SYS_RGSR_EL1                   sys_reg(3, 0, 1, 0, 5)
 #define SYS_GCR_EL1                    sys_reg(3, 0, 1, 0, 6)
@@ -749,23 +747,6 @@
 #define ID_AA64MMFR0_EL1_PARANGE_MAX   ID_AA64MMFR0_EL1_PARANGE_48
 #endif
 
-/* id_aa64mmfr2 */
-#define ID_AA64MMFR2_EL1_E0PD_SHIFT    60
-#define ID_AA64MMFR2_EL1_EVT_SHIFT     56
-#define ID_AA64MMFR2_EL1_BBM_SHIFT     52
-#define ID_AA64MMFR2_EL1_TTL_SHIFT     48
-#define ID_AA64MMFR2_EL1_FWB_SHIFT     40
-#define ID_AA64MMFR2_EL1_IDS_SHIFT     36
-#define ID_AA64MMFR2_EL1_AT_SHIFT      32
-#define ID_AA64MMFR2_EL1_ST_SHIFT      28
-#define ID_AA64MMFR2_EL1_NV_SHIFT      24
-#define ID_AA64MMFR2_EL1_CCIDX_SHIFT   20
-#define ID_AA64MMFR2_EL1_VARange_SHIFT 16
-#define ID_AA64MMFR2_EL1_IESB_SHIFT    12
-#define ID_AA64MMFR2_EL1_LSM_SHIFT     8
-#define ID_AA64MMFR2_EL1_UAO_SHIFT     4
-#define ID_AA64MMFR2_EL1_CnP_SHIFT     0
-
 /* id_aa64dfr0 */
 #define ID_AA64DFR0_MTPMU_SHIFT                48
 #define ID_AA64DFR0_TRBE_SHIFT         44

diff --git a/arch/arm64/tools/sysreg b/arch/arm64/tools/sysreg
index f56758d..711e805 100644 (file)
--- a/arch/arm64/tools/sysreg
+++ b/arch/arm64/tools/sysreg
@@ -459,6 +459,73 @@ Enum       3:0     HAFDBS
 EndEnum
 EndSysreg
 
+Sysreg ID_AA64MMFR2_EL1        3       0       0       7       2
+Enum   63:60   E0PD
+       0b0000  NI
+       0b0001  IMP
+EndEnum
+Enum   59:56   EVT
+       0b0000  NI
+       0b0001  IMP
+       0b0010  TTLBxS
+EndEnum
+Enum   55:52   BBM
+       0b0000  0
+       0b0001  1
+       0b0010  2
+EndEnum
+Enum   51:48   TTL
+       0b0000  NI
+       0b0001  IMP
+EndEnum
+Res0   47:44
+Enum   43:40   FWB
+       0b0000  NI
+       0b0001  IMP
+EndEnum
+Enum   39:36   IDS
+       0b0000  0x0
+       0b0001  0x18
+EndEnum
+Enum   35:32   AT
+       0b0000  NI
+       0b0001  IMP
+EndEnum
+Enum   31:28   ST
+       0b0000  39
+       0b0001  48_47
+EndEnum
+Enum   27:24   NV
+       0b0000  NI
+       0b0001  IMP
+       0b0010  NV2
+EndEnum
+Enum   23:20   CCIDX
+       0b0000  32
+       0b0001  64
+EndEnum
+Enum   19:16   VARange
+       0b0000  48
+       0b0001  52
+EndEnum
+Enum   15:12   IESB
+       0b0000  NI
+       0b0001  IMP
+EndEnum
+Enum   11:8    LSM
+       0b0000  NI
+       0b0001  IMP
+EndEnum
+Enum   7:4     UAO
+       0b0000  NI
+       0b0001  IMP
+EndEnum
+Enum   3:0     CnP
+       0b0000  NI
+       0b0001  IMP
+EndEnum
+EndSysreg
+
 Sysreg SCTLR_EL1       3       0       1       0       0
 Field  63      TIDCP
 Field  62      SPINMASK