clk: tl1: bringup clock for tl1 [1/1]

PD#172587

Problem:
Bringup clock for tl1.

Solution:
Bringuup clock for tl1.
Cherrypick from bringup/amlogic-4.9/tl1-20181111

1. Add hdmirx meter clock
2. fix gp0 pll error
3. remove vpu_clk enable in clktree
4. add hdmi axi clock
5. fix tl1 mpll clk overflow issue
6. fix vapb clock error rate
7. add 1.404G and 1.5G cpu freqs for tl1

Verify:
TL1 T962X2 X301 & SKT

Change-Id: I73a9afca35f8a9ce26cc6f3a75a738525fc8d728
Signed-off-by: Jian Hu <jian.hu@amlogic.com>

diff --git a/arch/arm/boot/dts/amlogic/tl1_pxp.dts b/arch/arm/boot/dts/amlogic/tl1_pxp.dts
index 34cd0c1..59576f7 100644 (file)
--- a/arch/arm/boot/dts/amlogic/tl1_pxp.dts
+++ b/arch/arm/boot/dts/amlogic/tl1_pxp.dts
@@ -415,7 +415,7 @@
                clocks = <&clkc CLKID_HDMIRX_MODET_COMP>,
                           <&clkc CLKID_HDMIRX_CFG_COMP>,
                           <&clkc CLKID_HDMIRX_ACR_COMP>,
-                          <&clkc CLKID_HDMIRX_AUDMEAS_COMP>,
+                          <&clkc CLKID_HDMIRX_METER_COMP>,
                           <&xtal>,
                           <&clkc CLKID_FCLK_DIV5>,
                           <&clkc CLKID_FCLK_DIV7>,
@@ -427,7 +427,7 @@
                clock-names = "hdmirx_modet_clk",
                        "hdmirx_cfg_clk",
                                "hdmirx_acr_ref_clk",
-                               "hdmirx_audmeas_clk",
+                               "cts_hdmirx_meter_clk",
                                "xtal",
                                "fclk_div5",
                                "fclk_div7",

diff --git a/arch/arm/boot/dts/amlogic/tl1_t962x2_skt.dts b/arch/arm/boot/dts/amlogic/tl1_t962x2_skt.dts
index 8c340c5..c335071 100644 (file)
--- a/arch/arm/boot/dts/amlogic/tl1_t962x2_skt.dts
+++ b/arch/arm/boot/dts/amlogic/tl1_t962x2_skt.dts
@@ -578,7 +578,7 @@
                clocks = <&clkc CLKID_HDMIRX_MODET_COMP>,
                           <&clkc CLKID_HDMIRX_CFG_COMP>,
                           <&clkc CLKID_HDMIRX_ACR_COMP>,
-                          <&clkc CLKID_HDMIRX_AUDMEAS_COMP>,
+                          <&clkc CLKID_HDMIRX_METER_COMP>,
                           <&xtal>,
                           <&clkc CLKID_FCLK_DIV5>,
                           <&clkc CLKID_FCLK_DIV7>,
@@ -590,7 +590,7 @@
                clock-names = "hdmirx_modet_clk",
                        "hdmirx_cfg_clk",
                                "hdmirx_acr_ref_clk",
-                               "hdmirx_audmeas_clk",
+                               "cts_hdmirx_meter_clk",
                                "xtal",
                                "fclk_div5",
                                "fclk_div7",

diff --git a/arch/arm/boot/dts/amlogic/tl1_t962x2_x301.dts b/arch/arm/boot/dts/amlogic/tl1_t962x2_x301.dts
index adf2be6..d37d00c 100644 (file)
--- a/arch/arm/boot/dts/amlogic/tl1_t962x2_x301.dts
+++ b/arch/arm/boot/dts/amlogic/tl1_t962x2_x301.dts
@@ -578,7 +578,7 @@
                clocks = <&clkc CLKID_HDMIRX_MODET_COMP>,
                           <&clkc CLKID_HDMIRX_CFG_COMP>,
                           <&clkc CLKID_HDMIRX_ACR_COMP>,
-                          <&clkc CLKID_HDMIRX_AUDMEAS_COMP>,
+                          <&clkc CLKID_HDMIRX_METER_COMP>,
                           <&xtal>,
                           <&clkc CLKID_FCLK_DIV5>,
                           <&clkc CLKID_FCLK_DIV7>,
@@ -590,7 +590,7 @@
                clock-names = "hdmirx_modet_clk",
                        "hdmirx_cfg_clk",
                                "hdmirx_acr_ref_clk",
-                               "hdmirx_audmeas_clk",
+                               "cts_hdmirx_meter_clk",
                                "xtal",
                                "fclk_div5",
                                "fclk_div7",

diff --git a/drivers/amlogic/clk/tl1/tl1.c b/drivers/amlogic/clk/tl1/tl1.c
index efe6814..472d945 100644 (file)
--- a/drivers/amlogic/clk/tl1/tl1.c
+++ b/drivers/amlogic/clk/tl1/tl1.c
@@ -51,7 +51,7 @@ static struct meson_clk_pll tl1_sys_pll = {
        },
        .n = {
                .reg_off = HHI_SYS_PLL_CNTL0,
-               .shift   = 9,
+               .shift   = 10,
                .width   = 5,
        },
        .od = {
@@ -79,13 +79,13 @@ static struct meson_clk_pll tl1_gp0_pll = {
        },
        .n = {
                .reg_off = HHI_GP0_PLL_CNTL0,
-               .shift   = 9,
+               .shift   = 10,
                .width   = 5,
        },
        .od = {
                .reg_off = HHI_GP0_PLL_CNTL0,
                .shift   = 16,
-               .width   = 2,
+               .width   = 3,
        },
        .rate_table = tl1_pll_rate_table,
        .rate_count = ARRAY_SIZE(tl1_pll_rate_table),

diff --git a/drivers/amlogic/clk/tl1/tl1.h b/drivers/amlogic/clk/tl1/tl1.h
index 92d8996..f8f0377 100644 (file)
--- a/drivers/amlogic/clk/tl1/tl1.h
+++ b/drivers/amlogic/clk/tl1/tl1.h
@@ -80,6 +80,7 @@
 #define HHI_HDMIRX_CLK_CNTL            0x200 /* 0x80 offset in datasheet1 */
 #define HHI_HDMIRX_AUD_CLK_CNTL                0x204 /* 0x81 offset in datasheet1 */
 #define HHI_VPU_CLKB_CNTL              0x20C /* 0x83 offset in datasheet1 */
+#define HHI_HDMIRX_METER_CLK_CNTL      0x234 /* 0x8d offset in datasheet1 */
 
 #define HHI_VDIN_MEAS_CLK_CNTL         0x250 /* 0x94 offset in datasheet1 */
 #define HHI_NAND_CLK_CNTL              0x25C /* 0x97 offset in datasheet1*/
@@ -114,6 +115,7 @@
 #define HHI_ADC_PLL_CNTL2              0x2AC /* 0xab offset in datasheet */
 #define HHI_ADC_PLL_CNTL3              0x2B0 /* 0xac offset in datasheet */
 #define HHI_ADC_PLL_CNTL4              0x2B4 /* 0xad offset in datasheet */
+#define HHI_HDMIRX_AXI_CLK_CNTL                0x2E0 /* 0xb8 offset in datasheet */
 
 #define HHI_SYS_PLL_CNTL0              0x2f4 /* 0xbd offset in datasheet */
 #define HHI_SYS_PLL_CNTL1              0x2f8 /* 0xbe offset in datasheet */
@@ -159,7 +161,9 @@ static const struct pll_rate_table tl1_pll_rate_table[] = {
        PLL_RATE(1200000000ULL, 200, 1, 2), /*DCO=4800M*/
        PLL_RATE(1296000000ULL, 216, 1, 2), /*DCO=5184M*/
        PLL_RATE(1398000000ULL, 233, 1, 2), /*DCO=5592M*/
+       PLL_RATE(1404000000ULL, 234, 1, 2), /*DCO=5614M*/
        PLL_RATE(1494000000ULL, 249, 1, 2), /*DCO=5976M*/
+       PLL_RATE(1500000000ULL, 125, 1, 1), /*DCO=3000M*/
        PLL_RATE(1512000000ULL, 126, 1, 1), /*DCO=3024M*/
        PLL_RATE(1608000000ULL, 134, 1, 1), /*DCO=3216M*/
        PLL_RATE(1704000000ULL, 142, 1, 1), /*DCO=3408M*/

diff --git a/drivers/amlogic/clk/tl1/tl1_clk-mpll.c b/drivers/amlogic/clk/tl1/tl1_clk-mpll.c
index 81e9dfe..4b27579 100644 (file)
--- a/drivers/amlogic/clk/tl1/tl1_clk-mpll.c
+++ b/drivers/amlogic/clk/tl1/tl1_clk-mpll.c
@@ -28,7 +28,7 @@
 #include "../clkc.h"
 /* #undef pr_debug */
 /* #define pr_debug pr_info */
-#define SDM_MAX 16384
+#define SDM_MAX 16384ULL
 #define MAX_RATE       500000000
 #define MIN_RATE       3920000
 
@@ -87,6 +87,7 @@ static int mpll_set_rate(struct clk_hw *hw, unsigned long rate,
        struct parm *p;
        unsigned long reg, sdm, n2;
        unsigned long flags = 0;
+       uint64_t rate64 = parent_rate;
 
        if ((rate > MAX_RATE) || (rate < MIN_RATE)) {
                pr_err("Err: can not set rate to %lu!\n", rate);
@@ -98,8 +99,12 @@ static int mpll_set_rate(struct clk_hw *hw, unsigned long rate,
                spin_lock_irqsave(mpll->lock, flags);
 
        /* calculate new n2 and sdm */
-       n2 = parent_rate / rate;
-       sdm = DIV_ROUND_UP((parent_rate - n2 * rate) * SDM_MAX, rate);
+       do_div(rate64, rate);
+       n2 = rate64;
+
+       rate64 = (parent_rate - n2 * rate) * SDM_MAX + rate - 1;
+       do_div(rate64, rate);
+       sdm = rate64;
        if (sdm >= SDM_MAX)
                sdm = SDM_MAX - 1;
 

diff --git a/drivers/amlogic/clk/tl1/tl1_clk_media.c b/drivers/amlogic/clk/tl1/tl1_clk_media.c
index 6be0ef2..825b7d6 100644 (file)
--- a/drivers/amlogic/clk/tl1/tl1_clk_media.c
+++ b/drivers/amlogic/clk/tl1/tl1_clk_media.c
@@ -158,15 +158,8 @@ static DIV(hdmirx_modet_div, HHI_HDMIRX_CLK_CNTL, 16, 7, "hdmirx_modet_mux",
 static GATE(hdmirx_modet_gate, HHI_HDMIRX_CLK_CNTL, 24, "hdmirx_modet_div",
                        CLK_GET_RATE_NOCACHE);
 
-/*hdmirx audmeas clock*/
 PNAME(hdmirx_ref_parent_names) = { "fclk_div4",
 "fclk_div3", "fclk_div5", "fclk_div7" };
-static MUX(hdmirx_audmeas_mux, HHI_HDMIRX_AUD_CLK_CNTL, 0x3, 9,
-hdmirx_ref_parent_names, CLK_GET_RATE_NOCACHE);
-static DIV(hdmirx_audmeas_div, HHI_HDMIRX_AUD_CLK_CNTL, 0, 7,
-"hdmirx_audmeas_mux", CLK_GET_RATE_NOCACHE);
-static GATE(hdmirx_audmeas_gate, HHI_HDMIRX_AUD_CLK_CNTL, 8,
-"hdmirx_audmeas_div", CLK_GET_RATE_NOCACHE);
 /* hdmirx acr clock*/
 static MUX(hdmirx_acr_mux, HHI_HDMIRX_AUD_CLK_CNTL, 0x3, 25,
 hdmirx_ref_parent_names, CLK_GET_RATE_NOCACHE);
@@ -194,6 +187,24 @@ static DIV(hdcp22_esm_div, HHI_HDCP22_CLK_CNTL, 0, 7, "hdcp22_esm_mux",
 static GATE(hdcp22_esm_gate, HHI_HDCP22_CLK_CNTL, 8, "hdcp22_esm_div",
                        CLK_GET_RATE_NOCACHE | CLK_IGNORE_UNUSED);
 
+PNAME(hdmirx_meter_parent_names) = { "xtal",
+"fclk_div4", "fclk_div3", "fclk_div5" };
+static MUX(hdmirx_meter_mux, HHI_HDMIRX_METER_CLK_CNTL, 0x3, 9,
+hdmirx_meter_parent_names, CLK_GET_RATE_NOCACHE);
+static DIV(hdmirx_meter_div, HHI_HDMIRX_METER_CLK_CNTL, 0, 7,
+"hdmirx_meter_mux", CLK_GET_RATE_NOCACHE);
+static GATE(hdmirx_meter_gate, HHI_HDMIRX_METER_CLK_CNTL, 8,
+"hdmirx_meter_div", CLK_GET_RATE_NOCACHE);
+
+PNAME(hdmirx_axi_parent_names) = { "xtal",
+"fclk_div4", "fclk_div3", "fclk_div5" };
+static MUX(hdmirx_axi_mux, HHI_HDMIRX_AXI_CLK_CNTL, 0x3, 9,
+hdmirx_axi_parent_names, CLK_GET_RATE_NOCACHE);
+static DIV(hdmirx_axi_div, HHI_HDMIRX_AXI_CLK_CNTL, 0, 7,
+"hdmirx_axi_mux", CLK_GET_RATE_NOCACHE);
+static GATE(hdmirx_axi_gate, HHI_HDMIRX_AXI_CLK_CNTL, 8,
+"hdmirx_axi_div", CLK_GET_RATE_NOCACHE);
+
 /*vdec clock*/
 /* cts_vdec_clk */
 PNAME(dec_parent_names) = { "fclk_div2p5", "fclk_div3",
@@ -325,7 +336,7 @@ static struct clk_mux *tl1_media_clk_muxes[] = {
        &vpu_clkb_tmp_mux,
        &hdmirx_cfg_mux,
        &hdmirx_modet_mux,
-       &hdmirx_audmeas_mux,
+       &hdmirx_meter_mux,
        &hdmirx_acr_mux,
        &hdcp22_skp_mux,
        &hdcp22_esm_mux,
@@ -349,6 +360,7 @@ static struct clk_mux *tl1_media_clk_muxes[] = {
        &tcon_pll_mux,
        &cts_demod_mux,
        &adc_extclk_in_mux,
+       &hdmirx_axi_mux,
 };
 
 /* for init div clocks reg base*/
@@ -362,7 +374,7 @@ static struct clk_divider *tl1_media_clk_divs[] = {
        &vpu_clkb_div,
        &hdmirx_cfg_div,
        &hdmirx_modet_div,
-       &hdmirx_audmeas_div,
+       &hdmirx_meter_div,
        &hdmirx_acr_div,
        &hdcp22_skp_div,
        &hdcp22_esm_div,
@@ -381,6 +393,7 @@ static struct clk_divider *tl1_media_clk_divs[] = {
        &tcon_pll_div,
        &cts_demod_div,
        &adc_extclk_in_div,
+       &hdmirx_axi_div,
 };
 
 /* for init gate clocks reg base*/
@@ -395,7 +408,7 @@ static struct clk_gate *tl1_media_clk_gates[] = {
        &vpu_clkb_gate,
        &hdmirx_cfg_gate,
        &hdmirx_modet_gate,
-       &hdmirx_audmeas_gate,
+       &hdmirx_meter_gate,
        &hdmirx_acr_gate,
        &hdcp22_skp_gate,
        &hdcp22_esm_gate,
@@ -414,6 +427,7 @@ static struct clk_gate *tl1_media_clk_gates[] = {
        &tcon_pll_gate,
        &cts_demod_gate,
        &adc_extclk_in_gate,
+       &hdmirx_axi_gate,
 };
 
 static struct meson_composite m_composite[] = {
@@ -447,13 +461,13 @@ static struct meson_composite m_composite[] = {
        },
 
        {CLKID_VAPB_P0_COMP, "vapb_p0_composite",
-       vpu_parent_names, ARRAY_SIZE(vpu_parent_names),
+       vapb_parent_names, ARRAY_SIZE(vapb_parent_names),
        &vapb_p0_mux.hw, &vapb_p0_div.hw,
        &vapb_p0_gate.hw, 0
        },
 
        {CLKID_VAPB_P1_COMP, "vapb_p1_composite",
-       vpu_parent_names, ARRAY_SIZE(vpu_parent_names),
+       vapb_parent_names, ARRAY_SIZE(vapb_parent_names),
        &vapb_p1_mux.hw, &vapb_p1_div.hw,
        &vapb_p1_gate.hw, 0
        },
@@ -470,10 +484,16 @@ static struct meson_composite m_composite[] = {
        &hdmirx_modet_gate.hw, 0
        },
 
-       {CLKID_HDMIRX_AUDMEAS_COMP, "hdmirx_audmeas_composite",
-       hdmirx_ref_parent_names, ARRAY_SIZE(hdmirx_ref_parent_names),
-       &hdmirx_audmeas_mux.hw, &hdmirx_audmeas_div.hw,
-       &hdmirx_audmeas_gate.hw, 0
+       {CLKID_HDMIRX_METER_COMP, "hdmirx_meter_composite",
+       hdmirx_meter_parent_names, ARRAY_SIZE(hdmirx_meter_parent_names),
+       &hdmirx_meter_mux.hw, &hdmirx_meter_div.hw,
+       &hdmirx_meter_gate.hw, 0
+       },
+
+       {CLKID_HDMIRX_AXI_COMP, "hdmirx_axi_composite",
+       hdmirx_axi_parent_names, ARRAY_SIZE(hdmirx_axi_parent_names),
+       &hdmirx_axi_mux.hw, &hdmirx_axi_div.hw,
+       &hdmirx_axi_gate.hw, 0
        },
 
        {CLKID_HDMIRX_ACR_COMP, "hdmirx_acr_composite",
@@ -620,11 +640,11 @@ void meson_tl1_media_init(void)
 
        clks[CLKID_VPU_MUX] = clk_register(NULL, &vpu_mux.hw);
        WARN_ON(IS_ERR(clks[CLKID_VPU_MUX]));
-       clk_prepare_enable(clks[CLKID_VPU_MUX]);
+       /* clk_prepare_enable(clks[CLKID_VPU_MUX]); //do not enable*/
 
        clks[CLKID_VAPB_MUX] = clk_register(NULL, &vapb_mux.hw);
        WARN_ON(IS_ERR(clks[CLKID_VAPB_MUX]));
-       clk_prepare_enable(clks[CLKID_VAPB_MUX]);
+       /* clk_prepare_enable(clks[CLKID_VAPB_MUX]); //do not enable*/
 
        clks[CLKID_GE2D_GATE] = clk_register(NULL, &ge2d_gate.hw);
        WARN_ON(IS_ERR(clks[CLKID_GE2D_GATE]));

diff --git a/include/dt-bindings/clock/amlogic,tl1-clkc.h b/include/dt-bindings/clock/amlogic,tl1-clkc.h
index 827c1e3..cf0bbb0 100644 (file)
--- a/include/dt-bindings/clock/amlogic,tl1-clkc.h
+++ b/include/dt-bindings/clock/amlogic,tl1-clkc.h
@@ -203,12 +203,13 @@
 
 #define CLKID_HDMIRX_CFG_COMP                  (CLKID_HDMIRX_BASE + 0)
 #define CLKID_HDMIRX_MODET_COMP                        (CLKID_HDMIRX_BASE + 1)
-#define CLKID_HDMIRX_AUDMEAS_COMP              (CLKID_HDMIRX_BASE + 2)
+#define CLKID_HDMIRX_METER_COMP                        (CLKID_HDMIRX_BASE + 2)
 #define CLKID_HDMIRX_ACR_COMP                  (CLKID_HDMIRX_BASE + 3)
 #define CLKID_HDCP22_SKP_COMP                  (CLKID_HDMIRX_BASE + 4)
 #define CLKID_HDCP22_ESM_COMP                  (CLKID_HDMIRX_BASE + 5)
+#define CLKID_HDMIRX_AXI_COMP                  (CLKID_HDMIRX_BASE + 6)
 
-#define CLKID_VHDEC_BASE                       (CLKID_HDMIRX_BASE + 6)
+#define CLKID_VHDEC_BASE                       (CLKID_HDMIRX_BASE + 7)
 
 #define CLKID_VDEC_P0_MUX                      (CLKID_VHDEC_BASE + 0)
 #define CLKID_VDEC_P0_DIV                      (CLKID_VHDEC_BASE + 1)