pinctrl: sh-pfc: r8a7796: Add CAN support

This patch adds CAN[0-1] pinmux support to r8a7796 SoC.

Based on a patch for r8a7795 by Ramesh Shanmugasundaram.

Signed-off-by: Chris Paterson <chris.paterson2@renesas.com>
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>

diff --git a/drivers/pinctrl/sh-pfc/pfc-r8a7796.c b/drivers/pinctrl/sh-pfc/pfc-r8a7796.c
index e0fe375..cd7157a 100644 (file)
--- a/drivers/pinctrl/sh-pfc/pfc-r8a7796.c
+++ b/drivers/pinctrl/sh-pfc/pfc-r8a7796.c
@@ -1647,6 +1647,38 @@ static const unsigned int avb_avtp_capture_b_mux[] = {
        AVB_AVTP_CAPTURE_B_MARK,
 };
 
+/* - CAN ------------------------------------------------------------------ */
+static const unsigned int can0_data_a_pins[] = {
+       /* TX, RX */
+       RCAR_GP_PIN(1, 23),     RCAR_GP_PIN(1, 24),
+};
+static const unsigned int can0_data_a_mux[] = {
+       CAN0_TX_A_MARK,         CAN0_RX_A_MARK,
+};
+static const unsigned int can0_data_b_pins[] = {
+       /* TX, RX */
+       RCAR_GP_PIN(2, 0),      RCAR_GP_PIN(2, 1),
+};
+static const unsigned int can0_data_b_mux[] = {
+       CAN0_TX_B_MARK,         CAN0_RX_B_MARK,
+};
+static const unsigned int can1_data_pins[] = {
+       /* TX, RX */
+       RCAR_GP_PIN(1, 22),     RCAR_GP_PIN(1, 26),
+};
+static const unsigned int can1_data_mux[] = {
+       CAN1_TX_MARK,           CAN1_RX_MARK,
+};
+
+/* - CAN Clock -------------------------------------------------------------- */
+static const unsigned int can_clk_pins[] = {
+       /* CLK */
+       RCAR_GP_PIN(1, 25),
+};
+static const unsigned int can_clk_mux[] = {
+       CAN_CLK_MARK,
+};
+
 /* - DRIF0 --------------------------------------------------------------- */
 static const unsigned int drif0_ctrl_a_pins[] = {
        /* CLK, SYNC */
@@ -2425,6 +2457,10 @@ static const struct sh_pfc_pin_group pinmux_groups[] = {
        SH_PFC_PIN_GROUP(avb_avtp_capture_a),
        SH_PFC_PIN_GROUP(avb_avtp_match_b),
        SH_PFC_PIN_GROUP(avb_avtp_capture_b),
+       SH_PFC_PIN_GROUP(can0_data_a),
+       SH_PFC_PIN_GROUP(can0_data_b),
+       SH_PFC_PIN_GROUP(can1_data),
+       SH_PFC_PIN_GROUP(can_clk),
        SH_PFC_PIN_GROUP(drif0_ctrl_a),
        SH_PFC_PIN_GROUP(drif0_data0_a),
        SH_PFC_PIN_GROUP(drif0_data1_a),
@@ -2539,6 +2575,19 @@ static const char * const avb_groups[] = {
        "avb_avtp_capture_b",
 };
 
+static const char * const can0_groups[] = {
+       "can0_data_a",
+       "can0_data_b",
+};
+
+static const char * const can1_groups[] = {
+       "can1_data",
+};
+
+static const char * const can_clk_groups[] = {
+       "can_clk",
+};
+
 static const char * const drif0_groups[] = {
        "drif0_ctrl_a",
        "drif0_data0_a",
@@ -2698,6 +2747,9 @@ static const char * const sdhi3_groups[] = {
 
 static const struct sh_pfc_function pinmux_functions[] = {
        SH_PFC_FUNCTION(avb),
+       SH_PFC_FUNCTION(can0),
+       SH_PFC_FUNCTION(can1),
+       SH_PFC_FUNCTION(can_clk),
        SH_PFC_FUNCTION(drif0),
        SH_PFC_FUNCTION(drif1),
        SH_PFC_FUNCTION(drif2),