ppc4xx: TLB init file cleanup

This patch adds new macros, with frequently used combinations of the
4xx TLB access control and storage attibutes. Additionally the 4xx init.S
files are updated to make use of these new macros. Resulting in easier
to read TLB definitions.

Additionally some init.S files are updated to use the mmu header for the
TLB defines, instead of defining their own macros.

Signed-off-by: Stefan Roese <sr@denx.de>

diff --git a/arch/ppc/include/asm/mmu.h b/arch/ppc/include/asm/mmu.h
index ce7f081..5166507 100644 (file)
--- a/arch/ppc/include/asm/mmu.h
+++ b/arch/ppc/include/asm/mmu.h
@@ -577,11 +577,16 @@ extern int num_tlb_entries;
 #define SA_M   0x00000200      /* Memory coherence */
 #define SA_G   0x00000100      /* Guarded */
 #define SA_E   0x00000080      /* Endian */
+/* Some additional macros for combinations often used */
+#define SA_IG  (SA_I | SA_G)
 
 /* Access control */
 #define AC_X   0x00000024      /* Execute */
 #define AC_W   0x00000012      /* Write */
 #define AC_R   0x00000009      /* Read */
+/* Some additional macros for combinations often used */
+#define AC_RW  (AC_R | AC_W)
+#define AC_RWX (AC_R | AC_W | AC_X)
 
 /* Some handy macros */
 

diff --git a/board/amcc/bamboo/init.S b/board/amcc/bamboo/init.S
index 7439c80..6925921 100644 (file)
--- a/board/amcc/bamboo/init.S
+++ b/board/amcc/bamboo/init.S
@@ -48,29 +48,29 @@ tlbtab:
         * speed up boot process. It is patched after relocation to enable SA_I
         */
 #ifndef CONFIG_NAND_SPL
-       tlbentry(CONFIG_SYS_BOOT_BASE_ADDR, SZ_256M, CONFIG_SYS_BOOT_BASE_ADDR, 0, AC_R|AC_W|AC_X|SA_G)
+       tlbentry(CONFIG_SYS_BOOT_BASE_ADDR, SZ_256M, CONFIG_SYS_BOOT_BASE_ADDR, 0, AC_RWX | SA_G)
 #else
-       tlbentry(CONFIG_SYS_NAND_BOOT_SPL_SRC, SZ_4K, CONFIG_SYS_NAND_BOOT_SPL_SRC, 0, AC_R|AC_W|AC_X|SA_G)
-       tlbentry(CONFIG_SYS_SDRAM_BASE, SZ_256M, CONFIG_SYS_SDRAM_BASE, 0, AC_R|AC_W|AC_X|SA_G|SA_I)
+       tlbentry(CONFIG_SYS_NAND_BOOT_SPL_SRC, SZ_4K, CONFIG_SYS_NAND_BOOT_SPL_SRC, 0, AC_RWX | SA_G)
+       tlbentry(CONFIG_SYS_SDRAM_BASE, SZ_256M, CONFIG_SYS_SDRAM_BASE, 0, AC_RWX | SA_IG)
 #endif
 
        /* TLB-entry for init-ram in dcache (SA_I must be turned off!) */
-       tlbentry(CONFIG_SYS_INIT_RAM_ADDR, SZ_4K, CONFIG_SYS_INIT_RAM_ADDR, 0, AC_R|AC_W|AC_X|SA_G)
+       tlbentry(CONFIG_SYS_INIT_RAM_ADDR, SZ_4K, CONFIG_SYS_INIT_RAM_ADDR, 0, AC_RWX | SA_G)
 
        /* PCI base & peripherals */
-       tlbentry(CONFIG_SYS_PCI_BASE, SZ_256M, CONFIG_SYS_PCI_BASE, 0, AC_R|AC_W|SA_G|SA_I)
+       tlbentry(CONFIG_SYS_PCI_BASE, SZ_256M, CONFIG_SYS_PCI_BASE, 0, AC_RW | SA_IG)
 
-       tlbentry(CONFIG_SYS_NVRAM_BASE_ADDR, SZ_256M, CONFIG_SYS_NVRAM_BASE_ADDR, 0, AC_R|AC_W|AC_X|SA_W|SA_I)
-       tlbentry(CONFIG_SYS_NAND_ADDR, SZ_4K, CONFIG_SYS_NAND_ADDR, 0, AC_R|AC_W|AC_X|SA_W|SA_I)
+       tlbentry(CONFIG_SYS_NVRAM_BASE_ADDR, SZ_256M, CONFIG_SYS_NVRAM_BASE_ADDR, 0, AC_RWX | SA_W|SA_I)
+       tlbentry(CONFIG_SYS_NAND_ADDR, SZ_4K, CONFIG_SYS_NAND_ADDR, 0, AC_RWX | SA_W|SA_I)
 
        /* PCI */
-       tlbentry(CONFIG_SYS_PCI_MEMBASE, SZ_256M, CONFIG_SYS_PCI_MEMBASE, 0, AC_R|AC_W|SA_G|SA_I)
-       tlbentry(CONFIG_SYS_PCI_MEMBASE1, SZ_256M, CONFIG_SYS_PCI_MEMBASE1, 0, AC_R|AC_W|SA_G|SA_I)
-       tlbentry(CONFIG_SYS_PCI_MEMBASE2, SZ_256M, CONFIG_SYS_PCI_MEMBASE2, 0, AC_R|AC_W|SA_G|SA_I)
-       tlbentry(CONFIG_SYS_PCI_MEMBASE3, SZ_256M, CONFIG_SYS_PCI_MEMBASE3, 0, AC_R|AC_W|SA_G|SA_I)
+       tlbentry(CONFIG_SYS_PCI_MEMBASE, SZ_256M, CONFIG_SYS_PCI_MEMBASE, 0, AC_RW | SA_IG)
+       tlbentry(CONFIG_SYS_PCI_MEMBASE1, SZ_256M, CONFIG_SYS_PCI_MEMBASE1, 0, AC_RW | SA_IG)
+       tlbentry(CONFIG_SYS_PCI_MEMBASE2, SZ_256M, CONFIG_SYS_PCI_MEMBASE2, 0, AC_RW | SA_IG)
+       tlbentry(CONFIG_SYS_PCI_MEMBASE3, SZ_256M, CONFIG_SYS_PCI_MEMBASE3, 0, AC_RW | SA_IG)
 
        /* USB 2.0 Device */
-       tlbentry(CONFIG_SYS_USB_DEVICE, SZ_1K, CONFIG_SYS_USB_DEVICE, 0, AC_R|AC_W|SA_G|SA_I)
+       tlbentry(CONFIG_SYS_USB_DEVICE, SZ_1K, CONFIG_SYS_USB_DEVICE, 0, AC_RW | SA_IG)
 
        tlbtab_end
 
@@ -81,7 +81,7 @@ tlbtab:
         */
 #define TLB00  TLB0(CONFIG_SYS_BOOT_BASE_ADDR, SZ_256M)
 #define TLB01  TLB1(CONFIG_SYS_BOOT_BASE_ADDR, 0)
-#define TLB02  TLB2(AC_R|AC_W|AC_X|SA_G|SA_I)
+#define TLB02  TLB2(AC_RWX | SA_IG)
 
        .globl  reconfig_tlb0
 reconfig_tlb0:

diff --git a/board/amcc/canyonlands/init.S b/board/amcc/canyonlands/init.S
index 993bec3..64d5d42 100644 (file)
--- a/board/amcc/canyonlands/init.S
+++ b/board/amcc/canyonlands/init.S
@@ -47,11 +47,11 @@ tlbtab:
         * enable SA_I
         */
 #ifndef CONFIG_NAND_SPL
-       tlbentry(CONFIG_SYS_BOOT_BASE_ADDR, SZ_16M, CONFIG_SYS_BOOT_BASE_ADDR, 4, AC_R|AC_W|AC_X|SA_G) /* TLB 0 */
+       tlbentry(CONFIG_SYS_BOOT_BASE_ADDR, SZ_16M, CONFIG_SYS_BOOT_BASE_ADDR, 4, AC_RWX | SA_G) /* TLB 0 */
 #else
-       tlbentry(CONFIG_SYS_NAND_BOOT_SPL_SRC, SZ_4K, CONFIG_SYS_NAND_BOOT_SPL_SRC, 4, AC_R|AC_W|AC_X|SA_G)
-       tlbentry(CONFIG_SYS_SDRAM_BASE, SZ_256M, CONFIG_SYS_SDRAM_BASE, 0, AC_R|AC_W|AC_X|SA_G|SA_I)
-       tlbentry(256 << 20, SZ_256M, 256 << 20, 0, AC_R|AC_W|AC_X|SA_G|SA_I)
+       tlbentry(CONFIG_SYS_NAND_BOOT_SPL_SRC, SZ_4K, CONFIG_SYS_NAND_BOOT_SPL_SRC, 4, AC_RWX | SA_G)
+       tlbentry(CONFIG_SYS_SDRAM_BASE, SZ_256M, CONFIG_SYS_SDRAM_BASE, 0, AC_RWX | SA_IG)
+       tlbentry(256 << 20, SZ_256M, 256 << 20, 0, AC_RWX | SA_IG)
 #endif
 
        /*
@@ -62,51 +62,51 @@ tlbtab:
 
 #ifdef CONFIG_SYS_INIT_RAM_DCACHE
        /* TLB-entry for init-ram in dcache (SA_I must be turned off!) */
-       tlbentry(CONFIG_SYS_INIT_RAM_ADDR, SZ_4K, CONFIG_SYS_INIT_RAM_ADDR, 0, AC_R|AC_W|AC_X|SA_G)
+       tlbentry(CONFIG_SYS_INIT_RAM_ADDR, SZ_4K, CONFIG_SYS_INIT_RAM_ADDR, 0, AC_RWX | SA_G)
 #endif
 
-       tlbentry(CONFIG_SYS_PCI_BASE, SZ_256M, 0x00000000, 0xC, AC_R|AC_W|SA_G|SA_I)
-       tlbentry(CONFIG_SYS_PCI_MEMBASE, SZ_256M, 0x20000000, 0xC, AC_R|AC_W|SA_G|SA_I)
-       tlbentry(CONFIG_SYS_PCIE_MEMBASE, SZ_256M, 0xB0000000, 0xD, AC_R|AC_W|SA_G|SA_I)
+       tlbentry(CONFIG_SYS_PCI_BASE, SZ_256M, 0x00000000, 0xC, AC_RW | SA_IG)
+       tlbentry(CONFIG_SYS_PCI_MEMBASE, SZ_256M, 0x20000000, 0xC, AC_RW | SA_IG)
+       tlbentry(CONFIG_SYS_PCIE_MEMBASE, SZ_256M, 0xB0000000, 0xD, AC_RW | SA_IG)
 
-       tlbentry(CONFIG_SYS_PCIE0_CFGBASE, SZ_16M, 0x00000000, 0xD, AC_R|AC_W|SA_G|SA_I)
-       tlbentry(CONFIG_SYS_PCIE1_CFGBASE, SZ_16M, 0x20000000, 0xD, AC_R|AC_W|SA_G|SA_I)
-       tlbentry(CONFIG_SYS_PCIE0_XCFGBASE, SZ_1K, 0x10000000, 0xD, AC_R|AC_W|SA_G|SA_I)
-       tlbentry(CONFIG_SYS_PCIE1_XCFGBASE, SZ_1K, 0x30000000, 0xD, AC_R|AC_W|SA_G|SA_I)
+       tlbentry(CONFIG_SYS_PCIE0_CFGBASE, SZ_16M, 0x00000000, 0xD, AC_RW | SA_IG)
+       tlbentry(CONFIG_SYS_PCIE1_CFGBASE, SZ_16M, 0x20000000, 0xD, AC_RW | SA_IG)
+       tlbentry(CONFIG_SYS_PCIE0_XCFGBASE, SZ_1K, 0x10000000, 0xD, AC_RW | SA_IG)
+       tlbentry(CONFIG_SYS_PCIE1_XCFGBASE, SZ_1K, 0x30000000, 0xD, AC_RW | SA_IG)
 
        /* PCIe UTL register */
-       tlbentry(CONFIG_SYS_PCIE_BASE, SZ_16K, 0x08010000, 0xC, AC_R|AC_W|SA_G|SA_I)
+       tlbentry(CONFIG_SYS_PCIE_BASE, SZ_16K, 0x08010000, 0xC, AC_RW | SA_IG)
 
 #if !defined(CONFIG_ARCHES)
        /* TLB-entry for NAND */
-       tlbentry(CONFIG_SYS_NAND_ADDR, SZ_16M, CONFIG_SYS_NAND_ADDR, 4, AC_R|AC_W|AC_X|SA_G|SA_I)
+       tlbentry(CONFIG_SYS_NAND_ADDR, SZ_16M, CONFIG_SYS_NAND_ADDR, 4, AC_RWX | SA_IG)
 
        /* TLB-entry for CPLD */
-       tlbentry(CONFIG_SYS_BCSR_BASE, SZ_1K, CONFIG_SYS_BCSR_BASE, 4, AC_R|AC_W|SA_G|SA_I)
+       tlbentry(CONFIG_SYS_BCSR_BASE, SZ_1K, CONFIG_SYS_BCSR_BASE, 4, AC_RW | SA_IG)
 #else
        /* TLB-entry for FPGA */
-       tlbentry(CONFIG_SYS_FPGA_BASE, SZ_16M, CONFIG_SYS_FPGA_BASE, 4, AC_R|AC_W|SA_G|SA_I)
+       tlbentry(CONFIG_SYS_FPGA_BASE, SZ_16M, CONFIG_SYS_FPGA_BASE, 4, AC_RW | SA_IG)
 #endif
 
        /* TLB-entry for OCM */
-       tlbentry(CONFIG_SYS_OCM_BASE, SZ_1M, 0x00000000, 4, AC_R|AC_W|AC_X|SA_I)
+       tlbentry(CONFIG_SYS_OCM_BASE, SZ_1M, 0x00000000, 4, AC_RWX | SA_I)
 
        /* TLB-entry for Local Configuration registers => peripherals */
-       tlbentry(CONFIG_SYS_LOCAL_CONF_REGS, SZ_16M, CONFIG_SYS_LOCAL_CONF_REGS, 4, AC_R|AC_W|AC_X|SA_G|SA_I)
+       tlbentry(CONFIG_SYS_LOCAL_CONF_REGS, SZ_16M, CONFIG_SYS_LOCAL_CONF_REGS, 4, AC_RWX | SA_IG)
 
        /* AHB: Internal USB Peripherals (USB, SATA) */
-       tlbentry(CONFIG_SYS_AHB_BASE, SZ_1M, 0xbff00000, 4, AC_R|AC_W|AC_X|SA_G|SA_I)
+       tlbentry(CONFIG_SYS_AHB_BASE, SZ_1M, 0xbff00000, 4, AC_RWX | SA_IG)
 
 #if defined(CONFIG_RAPIDIO)
        /* TLB-entries for RapidIO (SRIO) */
        tlbentry(CONFIG_SYS_SRGPL0_REG_BAR, SZ_16M, CONFIG_SYS_SRGPL0_REG_BAR,
-                                       0xD, AC_R|AC_W|SA_G|SA_I)
+                                       0xD, AC_RW | SA_IG)
        tlbentry(CONFIG_SYS_SRGPL0_CFG_BAR, SZ_16M, CONFIG_SYS_SRGPL0_CFG_BAR,
-                                       0xD, AC_R|AC_W|SA_G|SA_I)
+                                       0xD, AC_RW | SA_IG)
        tlbentry(CONFIG_SYS_SRGPL0_MNT_BAR, SZ_16M, CONFIG_SYS_SRGPL0_MNT_BAR,
-                                       0xD, AC_R|AC_W|SA_G|SA_I)
+                                       0xD, AC_RW | SA_IG)
        tlbentry(CONFIG_SYS_I2ODMA_BASE, SZ_1K,  0x00100000,
-                                       0x4, AC_R|AC_W|SA_G|SA_I)
+                                       0x4, AC_RW | SA_IG)
 #endif
 
        tlbtab_end
@@ -118,7 +118,7 @@ tlbtab:
         */
 #define TLB00  TLB0(CONFIG_SYS_BOOT_BASE_ADDR, SZ_256M)
 #define TLB01  TLB1(CONFIG_SYS_BOOT_BASE_ADDR, 1)
-#define TLB02  TLB2(AC_R|AC_W|AC_X|SA_G|SA_I)
+#define TLB02  TLB2(AC_RWX | SA_IG)
 
        .globl  reconfig_tlb0
 reconfig_tlb0:

diff --git a/board/amcc/ebony/init.S b/board/amcc/ebony/init.S
index 153fa81..c911763 100644 (file)
--- a/board/amcc/ebony/init.S
+++ b/board/amcc/ebony/init.S
@@ -41,7 +41,7 @@
 tlbtab:
        tlbtab_start
 
-       tlbentry(0xf0000000, SZ_256M, 0xf0000000, 1, AC_R|AC_W|AC_X|SA_G|SA_I)
+       tlbentry(0xf0000000, SZ_256M, 0xf0000000, 1, AC_RWX | SA_IG)
 
        /*
         * TLB entries for SDRAM are not needed on this platform.
@@ -49,9 +49,9 @@ tlbtab:
         * routine.
         */
 
-       tlbentry(CONFIG_SYS_PERIPHERAL_BASE, SZ_256M, 0x40000000, 1, AC_R|AC_W|SA_G|SA_I)
-       tlbentry(CONFIG_SYS_ISRAM_BASE, SZ_4K, 0x80000000, 0, AC_R|AC_W|AC_X)
-       tlbentry(CONFIG_SYS_ISRAM_BASE + 0x1000, SZ_4K, 0x80001000, 0, AC_R|AC_W|AC_X)
-       tlbentry(CONFIG_SYS_PCI_BASE, SZ_256M, 0x00000000, 2, AC_R|AC_W|SA_G|SA_I)
-       tlbentry(CONFIG_SYS_PCI_MEMBASE, SZ_256M, 0x00000000, 3, AC_R|AC_W|SA_G|SA_I)
+       tlbentry(CONFIG_SYS_PERIPHERAL_BASE, SZ_256M, 0x40000000, 1, AC_RW | SA_IG)
+       tlbentry(CONFIG_SYS_ISRAM_BASE, SZ_4K, 0x80000000, 0, AC_RWX)
+       tlbentry(CONFIG_SYS_ISRAM_BASE + 0x1000, SZ_4K, 0x80001000, 0, AC_RWX)
+       tlbentry(CONFIG_SYS_PCI_BASE, SZ_256M, 0x00000000, 2, AC_RW | SA_IG)
+       tlbentry(CONFIG_SYS_PCI_MEMBASE, SZ_256M, 0x00000000, 3, AC_RW | SA_IG)
        tlbtab_end

diff --git a/board/amcc/katmai/init.S b/board/amcc/katmai/init.S
index 90598f6..59ccf2b 100644 (file)
--- a/board/amcc/katmai/init.S
+++ b/board/amcc/katmai/init.S
@@ -51,7 +51,7 @@ tlbtabA:
         * BOOT_CS (FLASH) must be first. Before relocation SA_I can be off to use the
         * speed up boot process. It is patched after relocation to enable SA_I
         */
-       tlbentry(0xff000000, SZ_16M, 0xff000000, 4, AC_R|AC_W|AC_X|SA_G)
+       tlbentry(0xff000000, SZ_16M, 0xff000000, 4, AC_RWX | SA_G)
 
        /*
         * TLB entries for SDRAM are not needed on this platform.
@@ -59,20 +59,20 @@ tlbtabA:
         * routine.
         */
 
-       tlbentry(CONFIG_SYS_ISRAM_BASE, SZ_256K, 0x00000000, 4, AC_R|AC_W|AC_X|SA_I)
-       tlbentry(CONFIG_SYS_PERIPHERAL_BASE, SZ_4K, 0xF0000000, 4, AC_R|AC_W|SA_G|SA_I)
+       tlbentry(CONFIG_SYS_ISRAM_BASE, SZ_256K, 0x00000000, 4, AC_RWX | SA_I)
+       tlbentry(CONFIG_SYS_PERIPHERAL_BASE, SZ_4K, 0xF0000000, 4, AC_RW | SA_IG)
 
-       tlbentry(CONFIG_SYS_PCI_BASE, SZ_256M, 0x00000000, 0xC, AC_R|AC_W|SA_G|SA_I)
-       tlbentry(CONFIG_SYS_PCI_MEMBASE, SZ_256M, 0x10000000, 0xC, AC_R|AC_W|SA_G|SA_I)
-       tlbentry(CONFIG_SYS_PCIE_MEMBASE, SZ_256M, 0xB0000000, 0xD, AC_R|AC_W|SA_G|SA_I)
-       tlbentry(CONFIG_SYS_PCIE_BASE, SZ_16K, 0x20000000, 0xC, AC_R|AC_W|SA_G|SA_I)
+       tlbentry(CONFIG_SYS_PCI_BASE, SZ_256M, 0x00000000, 0xC, AC_RW | SA_IG)
+       tlbentry(CONFIG_SYS_PCI_MEMBASE, SZ_256M, 0x10000000, 0xC, AC_RW | SA_IG)
+       tlbentry(CONFIG_SYS_PCIE_MEMBASE, SZ_256M, 0xB0000000, 0xD, AC_RW | SA_IG)
+       tlbentry(CONFIG_SYS_PCIE_BASE, SZ_16K, 0x20000000, 0xC, AC_RW | SA_IG)
 
-       tlbentry(CONFIG_SYS_PCIE0_CFGBASE, SZ_16M, 0x40000000, 0xC, AC_R|AC_W|SA_G|SA_I)
-       tlbentry(CONFIG_SYS_PCIE1_CFGBASE, SZ_16M, 0x80000000, 0xC, AC_R|AC_W|SA_G|SA_I)
-       tlbentry(CONFIG_SYS_PCIE2_CFGBASE, SZ_16M, 0xC0000000, 0xC, AC_R|AC_W|SA_G|SA_I)
-       tlbentry(CONFIG_SYS_PCIE0_XCFGBASE, SZ_1K, 0x50000000, 0xC, AC_R|AC_W|SA_G|SA_I)
-       tlbentry(CONFIG_SYS_PCIE1_XCFGBASE, SZ_1K, 0x90000000, 0xC, AC_R|AC_W|SA_G|SA_I)
-       tlbentry(CONFIG_SYS_PCIE2_XCFGBASE, SZ_1K, 0xD0000000, 0xC, AC_R|AC_W|SA_G|SA_I)
+       tlbentry(CONFIG_SYS_PCIE0_CFGBASE, SZ_16M, 0x40000000, 0xC, AC_RW | SA_IG)
+       tlbentry(CONFIG_SYS_PCIE1_CFGBASE, SZ_16M, 0x80000000, 0xC, AC_RW | SA_IG)
+       tlbentry(CONFIG_SYS_PCIE2_CFGBASE, SZ_16M, 0xC0000000, 0xC, AC_RW | SA_IG)
+       tlbentry(CONFIG_SYS_PCIE0_XCFGBASE, SZ_1K, 0x50000000, 0xC, AC_RW | SA_IG)
+       tlbentry(CONFIG_SYS_PCIE1_XCFGBASE, SZ_1K, 0x90000000, 0xC, AC_RW | SA_IG)
+       tlbentry(CONFIG_SYS_PCIE2_XCFGBASE, SZ_1K, 0xD0000000, 0xC, AC_RW | SA_IG)
        tlbtab_end
 
 /**************************************************************************
@@ -91,7 +91,7 @@ tlbtabB:
         * BOOT_CS (FLASH) must be first. Before relocation SA_I can be off to use the
         * speed up boot process. It is patched after relocation to enable SA_I
         */
-       tlbentry(0xff000000, SZ_16M, 0xff000000, 4, AC_R|AC_W|AC_X|SA_G)
+       tlbentry(0xff000000, SZ_16M, 0xff000000, 4, AC_RWX | SA_G)
 
        /*
         * TLB entries for SDRAM are not needed on this platform.
@@ -99,20 +99,20 @@ tlbtabB:
         * routine.
         */
 
-       tlbentry(CONFIG_SYS_ISRAM_BASE, SZ_256K, 0x00000000, 4, AC_R|AC_W|AC_X|SA_I)
+       tlbentry(CONFIG_SYS_ISRAM_BASE, SZ_256K, 0x00000000, 4, AC_RWX | SA_I)
 
-       tlbentry(CONFIG_SYS_PERIPHERAL_BASE, SZ_4K, 0xF0000000, 4, AC_R|AC_W|SA_G|SA_I)
+       tlbentry(CONFIG_SYS_PERIPHERAL_BASE, SZ_4K, 0xF0000000, 4, AC_RW | SA_IG)
 
-       tlbentry(CONFIG_SYS_ACE_BASE, SZ_1K, CONFIG_SYS_ACE_BASE, 4,AC_R|AC_W|SA_G|SA_I)
+       tlbentry(CONFIG_SYS_ACE_BASE, SZ_1K, CONFIG_SYS_ACE_BASE, 4,AC_RW | SA_IG)
 
-       tlbentry(CONFIG_SYS_PCI_BASE, SZ_256M, 0x00000000, 0xC, AC_R|AC_W|SA_G|SA_I)
-       tlbentry(CONFIG_SYS_PCI_MEMBASE, SZ_256M, 0x10000000, 0xC, AC_R|AC_W|SA_G|SA_I)
-       tlbentry(CONFIG_SYS_PCIE_MEMBASE, SZ_256M, 0xB0000000, 0xD, AC_R|AC_W|SA_G|SA_I)
+       tlbentry(CONFIG_SYS_PCI_BASE, SZ_256M, 0x00000000, 0xC, AC_RW | SA_IG)
+       tlbentry(CONFIG_SYS_PCI_MEMBASE, SZ_256M, 0x10000000, 0xC, AC_RW | SA_IG)
+       tlbentry(CONFIG_SYS_PCIE_MEMBASE, SZ_256M, 0xB0000000, 0xD, AC_RW | SA_IG)
 
-       tlbentry(CONFIG_SYS_PCIE0_CFGBASE, SZ_16M, 0x00000000, 0xD, AC_R|AC_W|SA_G|SA_I)
-       tlbentry(CONFIG_SYS_PCIE1_CFGBASE, SZ_16M, 0x20000000, 0xD, AC_R|AC_W|SA_G|SA_I)
-       tlbentry(CONFIG_SYS_PCIE2_CFGBASE, SZ_16M, 0x40000000, 0xD, AC_R|AC_W|SA_G|SA_I)
-       tlbentry(CONFIG_SYS_PCIE0_XCFGBASE, SZ_1K, 0x10000000, 0xD, AC_R|AC_W|SA_G|SA_I)
-       tlbentry(CONFIG_SYS_PCIE1_XCFGBASE, SZ_1K, 0x30000000, 0xD, AC_R|AC_W|SA_G|SA_I)
-       tlbentry(CONFIG_SYS_PCIE2_XCFGBASE, SZ_1K, 0x50000000, 0xD, AC_R|AC_W|SA_G|SA_I)
+       tlbentry(CONFIG_SYS_PCIE0_CFGBASE, SZ_16M, 0x00000000, 0xD, AC_RW | SA_IG)
+       tlbentry(CONFIG_SYS_PCIE1_CFGBASE, SZ_16M, 0x20000000, 0xD, AC_RW | SA_IG)
+       tlbentry(CONFIG_SYS_PCIE2_CFGBASE, SZ_16M, 0x40000000, 0xD, AC_RW | SA_IG)
+       tlbentry(CONFIG_SYS_PCIE0_XCFGBASE, SZ_1K, 0x10000000, 0xD, AC_RW | SA_IG)
+       tlbentry(CONFIG_SYS_PCIE1_XCFGBASE, SZ_1K, 0x30000000, 0xD, AC_RW | SA_IG)
+       tlbentry(CONFIG_SYS_PCIE2_XCFGBASE, SZ_1K, 0x50000000, 0xD, AC_RW | SA_IG)
        tlbtab_end

diff --git a/board/amcc/luan/init.S b/board/amcc/luan/init.S
index 513b0fc..06428d2 100644 (file)
--- a/board/amcc/luan/init.S
+++ b/board/amcc/luan/init.S
@@ -48,13 +48,13 @@ tlbtab:
         * BOOT_CS (FLASH) must be first. Before relocation SA_I can be off to use the
         * speed up boot process. It is patched after relocation to enable SA_I
         */
-       tlbentry(0xfff00000, SZ_1M, 0xfff00000, 1, AC_R|AC_W|AC_X|SA_G)
+       tlbentry(0xfff00000, SZ_1M, 0xfff00000, 1, AC_RWX | SA_G)
 
-       tlbentry(0xffc00000, SZ_1M, 0xffc00000, 1, AC_R|AC_W|AC_X|SA_G|SA_I)
-       tlbentry(0xffd00000, SZ_1M, 0xffd00000, 1, AC_R|AC_W|AC_X|SA_G|SA_I)
-       tlbentry(0xffe00000, SZ_1M, 0xffe00000, 1, AC_R|AC_W|AC_X|SA_G|SA_I)
-       tlbentry(0xff900000, SZ_1M, 0xff900000, 1, AC_R|AC_W|AC_X|SA_G|SA_I)
-       tlbentry(CONFIG_SYS_EPLD_BASE, SZ_256K, 0xff000000, 1, AC_R|AC_W|SA_G|SA_I)
+       tlbentry(0xffc00000, SZ_1M, 0xffc00000, 1, AC_RWX | SA_IG)
+       tlbentry(0xffd00000, SZ_1M, 0xffd00000, 1, AC_RWX | SA_IG)
+       tlbentry(0xffe00000, SZ_1M, 0xffe00000, 1, AC_RWX | SA_IG)
+       tlbentry(0xff900000, SZ_1M, 0xff900000, 1, AC_RWX | SA_IG)
+       tlbentry(CONFIG_SYS_EPLD_BASE, SZ_256K, 0xff000000, 1, AC_RW | SA_IG)
 
        /*
         * TLB entries for SDRAM are not needed on this platform.
@@ -63,12 +63,12 @@ tlbtab:
         */
 
        /* internal ram (l2 cache) */
-       tlbentry(CONFIG_SYS_ISRAM_BASE, SZ_256K, 0x80000000, 0, AC_R|AC_W|AC_X|SA_I)
+       tlbentry(CONFIG_SYS_ISRAM_BASE, SZ_256K, 0x80000000, 0, AC_RWX | SA_I)
 
        /* peripherals at f0000000 */
-       tlbentry(CONFIG_SYS_PERIPHERAL_BASE, SZ_4K, CONFIG_SYS_PERIPHERAL_BASE, 1, AC_R|AC_W|SA_G|SA_I)
+       tlbentry(CONFIG_SYS_PERIPHERAL_BASE, SZ_4K, CONFIG_SYS_PERIPHERAL_BASE, 1, AC_RW | SA_IG)
 
        /* PCI */
-       tlbentry(CONFIG_SYS_PCI_BASE, SZ_256M, 0x00000000, 9, AC_R|AC_W|SA_G|SA_I)
-       tlbentry(CONFIG_SYS_PCI_MEMBASE, SZ_256M, 0x10000000, 9, AC_R|AC_W|SA_G|SA_I)
+       tlbentry(CONFIG_SYS_PCI_BASE, SZ_256M, 0x00000000, 9, AC_RW | SA_IG)
+       tlbentry(CONFIG_SYS_PCI_MEMBASE, SZ_256M, 0x10000000, 9, AC_RW | SA_IG)
        tlbtab_end

diff --git a/board/amcc/ocotea/init.S b/board/amcc/ocotea/init.S
index e7c75df..2ef11cc 100644 (file)
--- a/board/amcc/ocotea/init.S
+++ b/board/amcc/ocotea/init.S
@@ -41,7 +41,7 @@
 tlbtab:
        tlbtab_start
 
-       tlbentry(0xf0000000, SZ_256M, 0xf0000000, 1, AC_R|AC_W|AC_X|SA_G|SA_I)
+       tlbentry(0xf0000000, SZ_256M, 0xf0000000, 1, AC_RWX | SA_IG)
 
        /*
         * TLB entries for SDRAM are not needed on this platform.
@@ -49,9 +49,9 @@ tlbtab:
         * routine.
         */
 
-       tlbentry(CONFIG_SYS_PERIPHERAL_BASE, SZ_256M, 0x40000000, 1, AC_R|AC_W|SA_G|SA_I)
-       tlbentry(CONFIG_SYS_ISRAM_BASE, SZ_4K, 0x80000000, 0, AC_R|AC_W|AC_X)
-       tlbentry(CONFIG_SYS_ISRAM_BASE + 0x1000, SZ_4K, 0x80001000, 0, AC_R|AC_W|AC_X)
-       tlbentry(CONFIG_SYS_PCI_BASE, SZ_256M, 0x00000000, 2, AC_R|AC_W|SA_G|SA_I)
-       tlbentry(CONFIG_SYS_PCI_MEMBASE, SZ_256M, 0x00000000, 3, AC_R|AC_W|SA_G|SA_I)
+       tlbentry(CONFIG_SYS_PERIPHERAL_BASE, SZ_256M, 0x40000000, 1, AC_RW | SA_IG)
+       tlbentry(CONFIG_SYS_ISRAM_BASE, SZ_4K, 0x80000000, 0, AC_RWX)
+       tlbentry(CONFIG_SYS_ISRAM_BASE + 0x1000, SZ_4K, 0x80001000, 0, AC_RWX)
+       tlbentry(CONFIG_SYS_PCI_BASE, SZ_256M, 0x00000000, 2, AC_RW | SA_IG)
+       tlbentry(CONFIG_SYS_PCI_MEMBASE, SZ_256M, 0x00000000, 3, AC_RW | SA_IG)
        tlbtab_end

diff --git a/board/amcc/redwood/init.S b/board/amcc/redwood/init.S
index 4da5869..fb10520 100644 (file)
--- a/board/amcc/redwood/init.S
+++ b/board/amcc/redwood/init.S
@@ -45,7 +45,7 @@ tlbtab:
         * BOOT_CS (FLASH) must be first. Before relocation SA_I can be off to use the
         * speed up boot process. It is patched after relocation to enable SA_I
         */
-       tlbentry(0xff000000, SZ_16M, 0xff000000, 4, AC_R|AC_W|AC_X|SA_G)
+       tlbentry(0xff000000, SZ_16M, 0xff000000, 4, AC_RWX | SA_G)
 
        /*
         * TLB entries for SDRAM are not needed on this platform.
@@ -54,24 +54,24 @@ tlbtab:
         */
 
        /* Although 512 KB, map 256k at a time */
-       tlbentry(CONFIG_SYS_ISRAM_BASE, SZ_256K, 0x00000000, 4, AC_R|AC_W|AC_X|SA_I)
-       tlbentry(CONFIG_SYS_ISRAM_BASE + 0x40000, SZ_256K, 0x00040000, 4, AC_R|AC_W|AC_X|SA_I)
+       tlbentry(CONFIG_SYS_ISRAM_BASE, SZ_256K, 0x00000000, 4, AC_RWX | SA_I)
+       tlbentry(CONFIG_SYS_ISRAM_BASE + 0x40000, SZ_256K, 0x00040000, 4, AC_RWX | SA_I)
 
-       tlbentry(CONFIG_SYS_OPER_FLASH, SZ_16M, 0xE7000000, 4,AC_R|AC_W|AC_X|SA_G|SA_I)
+       tlbentry(CONFIG_SYS_OPER_FLASH, SZ_16M, 0xE7000000, 4,AC_RWX | SA_IG)
 
        /*
         * Peripheral base
         */
-       tlbentry(CONFIG_SYS_PERIPHERAL_BASE, SZ_16K, 0xEF600000, 4, AC_R|AC_W|SA_G|SA_I)
+       tlbentry(CONFIG_SYS_PERIPHERAL_BASE, SZ_16K, 0xEF600000, 4, AC_RW | SA_IG)
 
-       tlbentry(CONFIG_SYS_PCIE0_XCFGBASE,SZ_16M, 0x00000000, 0xC, AC_R|AC_W|SA_G|SA_I)
-       tlbentry(CONFIG_SYS_PCIE1_XCFGBASE,SZ_16M, 0x10000000, 0xC, AC_R|AC_W|SA_G|SA_I)
-       tlbentry(CONFIG_SYS_PCIE2_XCFGBASE,SZ_16M, 0x20000000, 0xC, AC_R|AC_W|SA_G|SA_I)
+       tlbentry(CONFIG_SYS_PCIE0_XCFGBASE,SZ_16M, 0x00000000, 0xC, AC_RW | SA_IG)
+       tlbentry(CONFIG_SYS_PCIE1_XCFGBASE,SZ_16M, 0x10000000, 0xC, AC_RW | SA_IG)
+       tlbentry(CONFIG_SYS_PCIE2_XCFGBASE,SZ_16M, 0x20000000, 0xC, AC_RW | SA_IG)
 
-       tlbentry(CONFIG_SYS_PCIE0_MEMBASE, SZ_256M, 0x00000000, 0xD, AC_R|AC_W|SA_G|SA_I)
-       tlbentry(CONFIG_SYS_PCIE1_MEMBASE, SZ_256M, 0x00000000, 0xE, AC_R|AC_W|SA_G|SA_I)
+       tlbentry(CONFIG_SYS_PCIE0_MEMBASE, SZ_256M, 0x00000000, 0xD, AC_RW | SA_IG)
+       tlbentry(CONFIG_SYS_PCIE1_MEMBASE, SZ_256M, 0x00000000, 0xE, AC_RW | SA_IG)
 
-       tlbentry(CONFIG_SYS_PCIE0_REGBASE, SZ_64K, 0x30000000, 0xC, AC_R|AC_W|SA_G|SA_I)
-       tlbentry(CONFIG_SYS_PCIE1_REGBASE, SZ_64K, 0x30010000, 0xC, AC_R|AC_W|SA_G|SA_I)
-       tlbentry(CONFIG_SYS_PCIE2_REGBASE, SZ_64K, 0x30020000, 0xC, AC_R|AC_W|SA_G|SA_I)
+       tlbentry(CONFIG_SYS_PCIE0_REGBASE, SZ_64K, 0x30000000, 0xC, AC_RW | SA_IG)
+       tlbentry(CONFIG_SYS_PCIE1_REGBASE, SZ_64K, 0x30010000, 0xC, AC_RW | SA_IG)
+       tlbentry(CONFIG_SYS_PCIE2_REGBASE, SZ_64K, 0x30020000, 0xC, AC_RW | SA_IG)
        tlbtab_end

diff --git a/board/amcc/sequoia/init.S b/board/amcc/sequoia/init.S
index f090070..7139aae 100644 (file)
--- a/board/amcc/sequoia/init.S
+++ b/board/amcc/sequoia/init.S
@@ -41,7 +41,7 @@ tlbtab:
        tlbtab_start
 
        /* vxWorks needs this as first entry for the Machine Check interrupt */
-       tlbentry( 0x40000000, SZ_256M, 0, 0, AC_R|AC_W|AC_X|SA_G|SA_I )
+       tlbentry( 0x40000000, SZ_256M, 0, 0, AC_RWX | SA_IG )
 
        /*
         * The RAM-boot version skips the SDRAM TLB (identified by EPN=0). This
@@ -51,49 +51,49 @@ tlbtab:
 #ifndef CONFIG_SYS_RAMBOOT
        /* TLB-entry for DDR SDRAM (Up to 2GB) */
 #ifdef CONFIG_4xx_DCACHE
-       tlbentry( CONFIG_SYS_SDRAM_BASE, SZ_256M, CONFIG_SYS_SDRAM_BASE, 0, AC_R|AC_W|AC_X|SA_G)
+       tlbentry( CONFIG_SYS_SDRAM_BASE, SZ_256M, CONFIG_SYS_SDRAM_BASE, 0, AC_RWX | SA_G)
 #else
-       tlbentry( CONFIG_SYS_SDRAM_BASE, SZ_256M, CONFIG_SYS_SDRAM_BASE, 0, AC_R|AC_W|AC_X|SA_G|SA_I )
+       tlbentry( CONFIG_SYS_SDRAM_BASE, SZ_256M, CONFIG_SYS_SDRAM_BASE, 0, AC_RWX | SA_IG )
 #endif
 #endif /* CONFIG_SYS_RAMBOOT */
 
        /* TLB-entry for EBC */
-       tlbentry( CONFIG_SYS_BCSR_BASE, SZ_256M, CONFIG_SYS_BCSR_BASE, 1, AC_R|AC_W|AC_X|SA_G|SA_I )
+       tlbentry( CONFIG_SYS_BCSR_BASE, SZ_256M, CONFIG_SYS_BCSR_BASE, 1, AC_RWX | SA_IG )
 
        /* BOOT_CS (FLASH) must be forth. Before relocation SA_I can be off to use the
         * speed up boot process. It is patched after relocation to enable SA_I
         */
 #ifndef CONFIG_NAND_SPL
-       tlbentry( CONFIG_SYS_BOOT_BASE_ADDR, SZ_256M, CONFIG_SYS_BOOT_BASE_ADDR, 1, AC_R|AC_W|AC_X|SA_G )
+       tlbentry( CONFIG_SYS_BOOT_BASE_ADDR, SZ_256M, CONFIG_SYS_BOOT_BASE_ADDR, 1, AC_RWX | SA_G )
 #else
-       tlbentry( CONFIG_SYS_NAND_BOOT_SPL_SRC, SZ_4K, CONFIG_SYS_NAND_BOOT_SPL_SRC, 1, AC_R|AC_W|AC_X|SA_G )
+       tlbentry( CONFIG_SYS_NAND_BOOT_SPL_SRC, SZ_4K, CONFIG_SYS_NAND_BOOT_SPL_SRC, 1, AC_RWX | SA_G )
 #endif
 
 #ifdef CONFIG_SYS_INIT_RAM_DCACHE
        /* TLB-entry for init-ram in dcache (SA_I must be turned off!) */
-       tlbentry( CONFIG_SYS_INIT_RAM_ADDR, SZ_64K, CONFIG_SYS_INIT_RAM_ADDR, 0, AC_R|AC_W|AC_X|SA_G )
+       tlbentry( CONFIG_SYS_INIT_RAM_ADDR, SZ_64K, CONFIG_SYS_INIT_RAM_ADDR, 0, AC_RWX | SA_G )
 #endif
 
        /* TLB-entry for PCI Memory */
-       tlbentry( CONFIG_SYS_PCI_MEMBASE, SZ_256M, CONFIG_SYS_PCI_MEMBASE, 1, AC_R|AC_W|SA_G|SA_I )
-       tlbentry( CONFIG_SYS_PCI_MEMBASE1, SZ_256M, CONFIG_SYS_PCI_MEMBASE1, 1, AC_R|AC_W|SA_G|SA_I )
-       tlbentry( CONFIG_SYS_PCI_MEMBASE2, SZ_256M, CONFIG_SYS_PCI_MEMBASE2, 1, AC_R|AC_W|SA_G|SA_I )
-       tlbentry( CONFIG_SYS_PCI_MEMBASE3, SZ_256M, CONFIG_SYS_PCI_MEMBASE3, 1, AC_R|AC_W|SA_G|SA_I )
+       tlbentry( CONFIG_SYS_PCI_MEMBASE, SZ_256M, CONFIG_SYS_PCI_MEMBASE, 1, AC_RW | SA_IG )
+       tlbentry( CONFIG_SYS_PCI_MEMBASE1, SZ_256M, CONFIG_SYS_PCI_MEMBASE1, 1, AC_RW | SA_IG )
+       tlbentry( CONFIG_SYS_PCI_MEMBASE2, SZ_256M, CONFIG_SYS_PCI_MEMBASE2, 1, AC_RW | SA_IG )
+       tlbentry( CONFIG_SYS_PCI_MEMBASE3, SZ_256M, CONFIG_SYS_PCI_MEMBASE3, 1, AC_RW | SA_IG )
 
        /* TLB-entry for NAND */
-       tlbentry( CONFIG_SYS_NAND_ADDR, SZ_1K, CONFIG_SYS_NAND_ADDR, 1, AC_R|AC_W|AC_X|SA_G|SA_I )
+       tlbentry( CONFIG_SYS_NAND_ADDR, SZ_1K, CONFIG_SYS_NAND_ADDR, 1, AC_RWX | SA_IG )
 
        /* TLB-entry for Internal Registers & OCM */
-       tlbentry( 0xe0000000, SZ_16M, 0xe0000000, 0,  AC_R|AC_W|AC_X|SA_I )
+       tlbentry( 0xe0000000, SZ_16M, 0xe0000000, 0,  AC_RWX | SA_I )
 
        /*TLB-entry PCI registers*/
-       tlbentry( 0xEEC00000, SZ_1K, 0xEEC00000, 1,  AC_R|AC_W|AC_X|SA_G|SA_I )
+       tlbentry( 0xEEC00000, SZ_1K, 0xEEC00000, 1,  AC_RWX | SA_IG )
 
        /* TLB-entry for peripherals */
-       tlbentry( 0xEF000000, SZ_16M, 0xEF000000, 1, AC_R|AC_W|AC_X|SA_G|SA_I)
+       tlbentry( 0xEF000000, SZ_16M, 0xEF000000, 1, AC_RWX | SA_IG)
 
        /* TLB-entry PCI IO Space - from sr@denx.de */
-       tlbentry(0xE8000000, SZ_64K, 0xE8000000, 1, AC_R|AC_W|AC_X|SA_G|SA_I)
+       tlbentry(0xE8000000, SZ_64K, 0xE8000000, 1, AC_RWX | SA_IG)
 
        tlbtab_end
 
@@ -104,7 +104,7 @@ tlbtab:
         */
 #define TLB00  TLB0(CONFIG_SYS_BOOT_BASE_ADDR, SZ_256M)
 #define TLB01  TLB1(CONFIG_SYS_BOOT_BASE_ADDR, 1)
-#define TLB02  TLB2(AC_R|AC_W|AC_X|SA_G|SA_I)
+#define TLB02  TLB2(AC_RWX | SA_IG)
 
        .globl  reconfig_tlb0
 reconfig_tlb0:

diff --git a/board/amcc/taishan/init.S b/board/amcc/taishan/init.S
index 748ec0a..ac4e95d 100644 (file)
--- a/board/amcc/taishan/init.S
+++ b/board/amcc/taishan/init.S
@@ -22,56 +22,9 @@
  */
 
 #include <ppc_asm.tmpl>
+#include <asm/mmu.h>
 #include <config.h>
 
-/* General */
-#define TLB_VALID   0x00000200
-#define _256M       0x10000000
-
-/* Supported page sizes */
-
-#define SZ_1K      0x00000000
-#define SZ_4K      0x00000010
-#define SZ_16K     0x00000020
-#define SZ_64K     0x00000030
-#define SZ_256K            0x00000040
-#define SZ_1M      0x00000050
-#define SZ_8M       0x00000060
-#define SZ_16M     0x00000070
-#define SZ_256M            0x00000090
-
-/* Storage attributes */
-#define SA_W       0x00000800      /* Write-through */
-#define SA_I       0x00000400      /* Caching inhibited */
-#define SA_M       0x00000200      /* Memory coherence */
-#define SA_G       0x00000100      /* Guarded */
-#define SA_E       0x00000080      /* Endian */
-
-/* Access control */
-#define AC_X       0x00000024      /* Execute */
-#define AC_W       0x00000012      /* Write */
-#define AC_R       0x00000009      /* Read */
-
-/* Some handy macros */
-
-#define EPN(e)         ((e) & 0xfffffc00)
-#define TLB0(epn,sz)   ( (EPN((epn)) | (sz) | TLB_VALID ) )
-#define TLB1(rpn,erpn) ( ((rpn)&0xfffffc00) | (erpn) )
-#define TLB2(a)                ( (a)&0x00000fbf )
-
-#define tlbtab_start\
-       mflr    r1  ;\
-       bl 0f       ;
-
-#define tlbtab_end\
-       .long 0, 0, 0   ;   \
-0:     mflr    r0      ;   \
-       mtlr    r1      ;   \
-       blr             ;
-
-#define tlbentry(epn,sz,rpn,erpn,attr)\
-       .long TLB0(epn,sz),TLB1(rpn,erpn),TLB2(attr)
-
 /**************************************************************************
  * TLB TABLE
  *
@@ -88,10 +41,10 @@
 
 tlbtab:
        tlbtab_start
-       tlbentry( 0xf0000000, SZ_256M, 0xf0000000, 1, AC_R|AC_W|AC_X|SA_G|SA_I)
-       tlbentry( CONFIG_SYS_PERIPHERAL_BASE, SZ_256M, 0x40000000, 1, AC_R|AC_W|SA_G|SA_I)
-       tlbentry( CONFIG_SYS_ISRAM_BASE, SZ_256K, 0x80000000, 0, AC_R|AC_W|AC_X )
-       tlbentry( CONFIG_SYS_SDRAM_BASE, SZ_256M, 0x00000000, 0, AC_R|AC_W|AC_X|SA_G|SA_I )
-       tlbentry( CONFIG_SYS_PCI_BASE, SZ_256M, 0x00000000, 2, AC_R|AC_W|SA_G|SA_I )
-       tlbentry( CONFIG_SYS_PCI_MEMBASE, SZ_256M, 0x00000000, 3, AC_R|AC_W|SA_G|SA_I )
+       tlbentry( 0xf0000000, SZ_256M, 0xf0000000, 1, AC_RWX | SA_IG)
+       tlbentry( CONFIG_SYS_PERIPHERAL_BASE, SZ_256M, 0x40000000, 1, AC_RW | SA_IG)
+       tlbentry( CONFIG_SYS_ISRAM_BASE, SZ_256K, 0x80000000, 0, AC_RWX )
+       tlbentry( CONFIG_SYS_SDRAM_BASE, SZ_256M, 0x00000000, 0, AC_RWX | SA_IG )
+       tlbentry( CONFIG_SYS_PCI_BASE, SZ_256M, 0x00000000, 2, AC_RW | SA_IG )
+       tlbentry( CONFIG_SYS_PCI_MEMBASE, SZ_256M, 0x00000000, 3, AC_RW | SA_IG )
        tlbtab_end

diff --git a/board/amcc/yosemite/init.S b/board/amcc/yosemite/init.S
index f938236..ed3741c 100644 (file)
--- a/board/amcc/yosemite/init.S
+++ b/board/amcc/yosemite/init.S
@@ -20,56 +20,9 @@
 */
 
 #include <ppc_asm.tmpl>
+#include <asm/mmu.h>
 #include <config.h>
 
-/* General */
-#define TLB_VALID   0x00000200
-
-/* Supported page sizes */
-
-#define SZ_1K      0x00000000
-#define SZ_4K      0x00000010
-#define SZ_16K     0x00000020
-#define SZ_64K     0x00000030
-#define SZ_256K            0x00000040
-#define SZ_1M      0x00000050
-#define SZ_8M       0x00000060
-#define SZ_16M     0x00000070
-#define SZ_256M            0x00000090
-
-/* Storage attributes */
-#define SA_W       0x00000800      /* Write-through */
-#define SA_I       0x00000400      /* Caching inhibited */
-#define SA_M       0x00000200      /* Memory coherence */
-#define SA_G       0x00000100      /* Guarded */
-#define SA_E       0x00000080      /* Endian */
-
-/* Access control */
-#define AC_X       0x00000024      /* Execute */
-#define AC_W       0x00000012      /* Write */
-#define AC_R       0x00000009      /* Read */
-
-/* Some handy macros */
-
-#define EPN(e)         ((e) & 0xfffffc00)
-#define TLB0(epn,sz)   ( (EPN((epn)) | (sz) | TLB_VALID ) )
-#define TLB1(rpn,erpn) ( ((rpn)&0xfffffc00) | (erpn) )
-#define TLB2(a)                ( (a)&0x00000fbf )
-
-#define tlbtab_start\
-       mflr    r1  ;\
-       bl 0f       ;
-
-#define tlbtab_end\
-       .long 0, 0, 0   ;   \
-0:     mflr    r0      ;   \
-       mtlr    r1      ;   \
-       blr             ;
-
-#define tlbentry(epn,sz,rpn,erpn,attr)\
-       .long TLB0(epn,sz),TLB1(rpn,erpn),TLB2(attr)
-
-
 /**************************************************************************
  * TLB TABLE
  *
@@ -91,22 +44,22 @@ tlbtab:
      * BOOT_CS (FLASH) must be first. Before relocation SA_I can be off to use the
      * speed up boot process. It is patched after relocation to enable SA_I
      */
-    tlbentry( CONFIG_SYS_BOOT_BASE_ADDR, SZ_256M, CONFIG_SYS_BOOT_BASE_ADDR, 0, AC_R|AC_W|AC_X|SA_G/*|SA_I*/)
+    tlbentry( CONFIG_SYS_BOOT_BASE_ADDR, SZ_256M, CONFIG_SYS_BOOT_BASE_ADDR, 0, AC_RWX | SA_G/*|SA_I*/)
 
     /* TLB-entry for init-ram in dcache (SA_I must be turned off!) */
-    tlbentry( CONFIG_SYS_INIT_RAM_ADDR, SZ_64K, CONFIG_SYS_INIT_RAM_ADDR, 0, AC_R|AC_W|AC_X|SA_G )
+    tlbentry( CONFIG_SYS_INIT_RAM_ADDR, SZ_64K, CONFIG_SYS_INIT_RAM_ADDR, 0, AC_RWX | SA_G )
 
-    tlbentry( CONFIG_SYS_SDRAM_BASE, SZ_256M, CONFIG_SYS_SDRAM_BASE, 0, AC_R|AC_W|AC_X|SA_G|SA_I )
-    tlbentry( CONFIG_SYS_PCI_BASE, SZ_256M, CONFIG_SYS_PCI_BASE, 0, AC_R|AC_W|SA_G|SA_I )
-    tlbentry( CONFIG_SYS_NVRAM_BASE_ADDR, SZ_256M, CONFIG_SYS_NVRAM_BASE_ADDR, 0, AC_R|AC_W|AC_X|SA_W|SA_I )
+    tlbentry( CONFIG_SYS_SDRAM_BASE, SZ_256M, CONFIG_SYS_SDRAM_BASE, 0, AC_RWX | SA_IG )
+    tlbentry( CONFIG_SYS_PCI_BASE, SZ_256M, CONFIG_SYS_PCI_BASE, 0, AC_RW | SA_IG )
+    tlbentry( CONFIG_SYS_NVRAM_BASE_ADDR, SZ_256M, CONFIG_SYS_NVRAM_BASE_ADDR, 0, AC_RWX | SA_W|SA_I )
 
     /* PCI */
-    tlbentry( CONFIG_SYS_PCI_MEMBASE, SZ_256M, CONFIG_SYS_PCI_MEMBASE, 0, AC_R|AC_W|SA_G|SA_I )
-    tlbentry( CONFIG_SYS_PCI_MEMBASE1, SZ_256M, CONFIG_SYS_PCI_MEMBASE1, 0, AC_R|AC_W|SA_G|SA_I )
-    tlbentry( CONFIG_SYS_PCI_MEMBASE2, SZ_256M, CONFIG_SYS_PCI_MEMBASE2, 0, AC_R|AC_W|SA_G|SA_I )
-    tlbentry( CONFIG_SYS_PCI_MEMBASE3, SZ_256M, CONFIG_SYS_PCI_MEMBASE3, 0, AC_R|AC_W|SA_G|SA_I )
+    tlbentry( CONFIG_SYS_PCI_MEMBASE, SZ_256M, CONFIG_SYS_PCI_MEMBASE, 0, AC_RW | SA_IG )
+    tlbentry( CONFIG_SYS_PCI_MEMBASE1, SZ_256M, CONFIG_SYS_PCI_MEMBASE1, 0, AC_RW | SA_IG )
+    tlbentry( CONFIG_SYS_PCI_MEMBASE2, SZ_256M, CONFIG_SYS_PCI_MEMBASE2, 0, AC_RW | SA_IG )
+    tlbentry( CONFIG_SYS_PCI_MEMBASE3, SZ_256M, CONFIG_SYS_PCI_MEMBASE3, 0, AC_RW | SA_IG )
 
     /* USB 2.0 Device */
-    tlbentry( CONFIG_SYS_USB_DEVICE, SZ_1K, 0x50000000, 0, AC_R|AC_W|SA_G|SA_I )
+    tlbentry( CONFIG_SYS_USB_DEVICE, SZ_1K, 0x50000000, 0, AC_RW | SA_IG )
 
     tlbtab_end

diff --git a/board/amcc/yucca/init.S b/board/amcc/yucca/init.S
index f51035f..b2ac3ca 100644 (file)
--- a/board/amcc/yucca/init.S
+++ b/board/amcc/yucca/init.S
@@ -51,7 +51,7 @@ tlbtabA:
         * BOOT_CS (FLASH) must be first. Before relocation SA_I can be off to use the
         * speed up boot process. It is patched after relocation to enable SA_I
         */
-       tlbentry(0xff000000, SZ_16M, 0xff000000, 4, AC_R|AC_W|AC_X|SA_G)
+       tlbentry(0xff000000, SZ_16M, 0xff000000, 4, AC_RWX | SA_G)
 
        /*
         * TLB entries for SDRAM are not needed on this platform.
@@ -59,23 +59,23 @@ tlbtabA:
         * routine.
         */
 
-       tlbentry(CONFIG_SYS_ISRAM_BASE, SZ_256K, 0x00000000, 4, AC_R|AC_W|AC_X|SA_I)
-       tlbentry(CONFIG_SYS_FPGA_BASE, SZ_1K, 0xE2000000, 4,AC_R|AC_W|SA_I)
+       tlbentry(CONFIG_SYS_ISRAM_BASE, SZ_256K, 0x00000000, 4, AC_RWX | SA_I)
+       tlbentry(CONFIG_SYS_FPGA_BASE, SZ_1K, 0xE2000000, 4,AC_RW | SA_I)
 
-       tlbentry(CONFIG_SYS_OPER_FLASH, SZ_16M, 0xE7000000, 4,AC_R|AC_W|AC_X|SA_G|SA_I)
-       tlbentry(CONFIG_SYS_PERIPHERAL_BASE, SZ_4K, 0xF0000000, 4, AC_R|AC_W|SA_G|SA_I)
+       tlbentry(CONFIG_SYS_OPER_FLASH, SZ_16M, 0xE7000000, 4,AC_RWX | SA_IG)
+       tlbentry(CONFIG_SYS_PERIPHERAL_BASE, SZ_4K, 0xF0000000, 4, AC_RW | SA_IG)
 
-       tlbentry(CONFIG_SYS_PCI_BASE, SZ_256M, 0x00000000, 0xC, AC_R|AC_W|SA_G|SA_I)
-       tlbentry(CONFIG_SYS_PCI_MEMBASE, SZ_256M, 0x10000000, 0xC, AC_R|AC_W|SA_G|SA_I)
-       tlbentry(CONFIG_SYS_PCIE_MEMBASE, SZ_256M, 0xB0000000, 0xD, AC_R|AC_W|SA_G|SA_I)
-       tlbentry(CONFIG_SYS_PCIE_BASE, SZ_16K, 0x20000000, 0xC, AC_R|AC_W|SA_G|SA_I)
+       tlbentry(CONFIG_SYS_PCI_BASE, SZ_256M, 0x00000000, 0xC, AC_RW | SA_IG)
+       tlbentry(CONFIG_SYS_PCI_MEMBASE, SZ_256M, 0x10000000, 0xC, AC_RW | SA_IG)
+       tlbentry(CONFIG_SYS_PCIE_MEMBASE, SZ_256M, 0xB0000000, 0xD, AC_RW | SA_IG)
+       tlbentry(CONFIG_SYS_PCIE_BASE, SZ_16K, 0x20000000, 0xC, AC_RW | SA_IG)
 
-       tlbentry(CONFIG_SYS_PCIE0_CFGBASE, SZ_16M, 0x40000000, 0xC, AC_R|AC_W|SA_G|SA_I)
-       tlbentry(CONFIG_SYS_PCIE1_CFGBASE, SZ_16M, 0x80000000, 0xC, AC_R|AC_W|SA_G|SA_I)
-       tlbentry(CONFIG_SYS_PCIE2_CFGBASE, SZ_16M, 0xC0000000, 0xC, AC_R|AC_W|SA_G|SA_I)
-       tlbentry(CONFIG_SYS_PCIE0_XCFGBASE, SZ_1K, 0x50000000, 0xC, AC_R|AC_W|SA_G|SA_I)
-       tlbentry(CONFIG_SYS_PCIE1_XCFGBASE, SZ_1K, 0x90000000, 0xC, AC_R|AC_W|SA_G|SA_I)
-       tlbentry(CONFIG_SYS_PCIE2_XCFGBASE, SZ_1K, 0xD0000000, 0xC, AC_R|AC_W|SA_G|SA_I)
+       tlbentry(CONFIG_SYS_PCIE0_CFGBASE, SZ_16M, 0x40000000, 0xC, AC_RW | SA_IG)
+       tlbentry(CONFIG_SYS_PCIE1_CFGBASE, SZ_16M, 0x80000000, 0xC, AC_RW | SA_IG)
+       tlbentry(CONFIG_SYS_PCIE2_CFGBASE, SZ_16M, 0xC0000000, 0xC, AC_RW | SA_IG)
+       tlbentry(CONFIG_SYS_PCIE0_XCFGBASE, SZ_1K, 0x50000000, 0xC, AC_RW | SA_IG)
+       tlbentry(CONFIG_SYS_PCIE1_XCFGBASE, SZ_1K, 0x90000000, 0xC, AC_RW | SA_IG)
+       tlbentry(CONFIG_SYS_PCIE2_XCFGBASE, SZ_1K, 0xD0000000, 0xC, AC_RW | SA_IG)
        tlbtab_end
 
 /**************************************************************************
@@ -94,7 +94,7 @@ tlbtabB:
         * BOOT_CS (FLASH) must be first. Before relocation SA_I can be off to use the
         * speed up boot process. It is patched after relocation to enable SA_I
         */
-       tlbentry(0xff000000, SZ_16M, 0xff000000, 4, AC_R|AC_W|AC_X|SA_G)
+       tlbentry(0xff000000, SZ_16M, 0xff000000, 4, AC_RWX | SA_G)
 
        /*
         * TLB entries for SDRAM are not needed on this platform.
@@ -102,20 +102,20 @@ tlbtabB:
         * routine.
         */
 
-       tlbentry(CONFIG_SYS_ISRAM_BASE, SZ_256K, 0x00000000, 4, AC_R|AC_W|AC_X|SA_I)
-       tlbentry(CONFIG_SYS_FPGA_BASE, SZ_1K, 0xE2000000, 4,AC_R|AC_W|SA_I)
+       tlbentry(CONFIG_SYS_ISRAM_BASE, SZ_256K, 0x00000000, 4, AC_RWX | SA_I)
+       tlbentry(CONFIG_SYS_FPGA_BASE, SZ_1K, 0xE2000000, 4,AC_RW | SA_I)
 
-       tlbentry(CONFIG_SYS_OPER_FLASH, SZ_16M, 0xE7000000, 4,AC_R|AC_W|AC_X|SA_G|SA_I)
-       tlbentry(CONFIG_SYS_PERIPHERAL_BASE, SZ_4K, 0xF0000000, 4, AC_R|AC_W|SA_G|SA_I)
+       tlbentry(CONFIG_SYS_OPER_FLASH, SZ_16M, 0xE7000000, 4,AC_RWX | SA_IG)
+       tlbentry(CONFIG_SYS_PERIPHERAL_BASE, SZ_4K, 0xF0000000, 4, AC_RW | SA_IG)
 
-       tlbentry(CONFIG_SYS_PCI_BASE, SZ_256M, 0x00000000, 0xC, AC_R|AC_W|SA_G|SA_I)
-       tlbentry(CONFIG_SYS_PCI_MEMBASE, SZ_256M, 0x10000000, 0xC, AC_R|AC_W|SA_G|SA_I)
-       tlbentry(CONFIG_SYS_PCIE_MEMBASE, SZ_256M, 0xB0000000, 0xD, AC_R|AC_W|SA_G|SA_I)
+       tlbentry(CONFIG_SYS_PCI_BASE, SZ_256M, 0x00000000, 0xC, AC_RW | SA_IG)
+       tlbentry(CONFIG_SYS_PCI_MEMBASE, SZ_256M, 0x10000000, 0xC, AC_RW | SA_IG)
+       tlbentry(CONFIG_SYS_PCIE_MEMBASE, SZ_256M, 0xB0000000, 0xD, AC_RW | SA_IG)
 
-       tlbentry(CONFIG_SYS_PCIE0_CFGBASE, SZ_16M, 0x00000000, 0xD, AC_R|AC_W|SA_G|SA_I)
-       tlbentry(CONFIG_SYS_PCIE1_CFGBASE, SZ_16M, 0x20000000, 0xD, AC_R|AC_W|SA_G|SA_I)
-       tlbentry(CONFIG_SYS_PCIE2_CFGBASE, SZ_16M, 0x40000000, 0xD, AC_R|AC_W|SA_G|SA_I)
-       tlbentry(CONFIG_SYS_PCIE0_XCFGBASE, SZ_1K, 0x10000000, 0xD, AC_R|AC_W|SA_G|SA_I)
-       tlbentry(CONFIG_SYS_PCIE1_XCFGBASE, SZ_1K, 0x30000000, 0xD, AC_R|AC_W|SA_G|SA_I)
-       tlbentry(CONFIG_SYS_PCIE2_XCFGBASE, SZ_1K, 0x50000000, 0xD, AC_R|AC_W|SA_G|SA_I)
+       tlbentry(CONFIG_SYS_PCIE0_CFGBASE, SZ_16M, 0x00000000, 0xD, AC_RW | SA_IG)
+       tlbentry(CONFIG_SYS_PCIE1_CFGBASE, SZ_16M, 0x20000000, 0xD, AC_RW | SA_IG)
+       tlbentry(CONFIG_SYS_PCIE2_CFGBASE, SZ_16M, 0x40000000, 0xD, AC_RW | SA_IG)
+       tlbentry(CONFIG_SYS_PCIE0_XCFGBASE, SZ_1K, 0x10000000, 0xD, AC_RW | SA_IG)
+       tlbentry(CONFIG_SYS_PCIE1_XCFGBASE, SZ_1K, 0x30000000, 0xD, AC_RW | SA_IG)
+       tlbentry(CONFIG_SYS_PCIE2_XCFGBASE, SZ_1K, 0x50000000, 0xD, AC_RW | SA_IG)
        tlbtab_end

diff --git a/board/esd/du440/init.S b/board/esd/du440/init.S
index afcf9c4..351095a 100644 (file)
--- a/board/esd/du440/init.S
+++ b/board/esd/du440/init.S
@@ -44,38 +44,38 @@ tlbtab:
         * BOOT_CS (FLASH) must be first. Before relocation SA_I can be off to use the
         * speed up boot process. It is patched after relocation to enable SA_I
         */
-       tlbentry( CONFIG_SYS_BOOT_BASE_ADDR, SZ_256M, CONFIG_SYS_BOOT_BASE_ADDR, 1, AC_R|AC_W|AC_X|SA_G )
+       tlbentry( CONFIG_SYS_BOOT_BASE_ADDR, SZ_256M, CONFIG_SYS_BOOT_BASE_ADDR, 1, AC_RWX | SA_G )
 
 #ifdef CONFIG_SYS_INIT_RAM_DCACHE
        /* TLB-entry for init-ram in dcache (SA_I must be turned off!) */
-       tlbentry( CONFIG_SYS_INIT_RAM_ADDR, SZ_64K, CONFIG_SYS_INIT_RAM_ADDR, 0, AC_R|AC_W|AC_X|SA_G )
+       tlbentry( CONFIG_SYS_INIT_RAM_ADDR, SZ_64K, CONFIG_SYS_INIT_RAM_ADDR, 0, AC_RWX | SA_G )
 #endif
 
        /* TLB-entry for PCI Memory */
-       tlbentry( CONFIG_SYS_PCI_MEMBASE, SZ_256M,  CONFIG_SYS_PCI_MEMBASE, 1, AC_R|AC_W|SA_G|SA_I )
-       tlbentry( CONFIG_SYS_PCI_MEMBASE1, SZ_256M, CONFIG_SYS_PCI_MEMBASE1, 1, AC_R|AC_W|SA_G|SA_I )
-       tlbentry( CONFIG_SYS_PCI_MEMBASE2, SZ_256M, CONFIG_SYS_PCI_MEMBASE2, 1, AC_R|AC_W|SA_G|SA_I )
-       tlbentry( CONFIG_SYS_PCI_MEMBASE3, SZ_256M, CONFIG_SYS_PCI_MEMBASE3, 1, AC_R|AC_W|SA_G|SA_I )
+       tlbentry( CONFIG_SYS_PCI_MEMBASE, SZ_256M,  CONFIG_SYS_PCI_MEMBASE, 1, AC_RW | SA_IG )
+       tlbentry( CONFIG_SYS_PCI_MEMBASE1, SZ_256M, CONFIG_SYS_PCI_MEMBASE1, 1, AC_RW | SA_IG )
+       tlbentry( CONFIG_SYS_PCI_MEMBASE2, SZ_256M, CONFIG_SYS_PCI_MEMBASE2, 1, AC_RW | SA_IG )
+       tlbentry( CONFIG_SYS_PCI_MEMBASE3, SZ_256M, CONFIG_SYS_PCI_MEMBASE3, 1, AC_RW | SA_IG )
 
        /* TLB-entry for PCI IO */
-       tlbentry( CONFIG_SYS_PCI_IOBASE, SZ_64K, CONFIG_SYS_PCI_IOBASE, 1, AC_R|AC_W|SA_G|SA_I )
+       tlbentry( CONFIG_SYS_PCI_IOBASE, SZ_64K, CONFIG_SYS_PCI_IOBASE, 1, AC_RW | SA_IG )
 
        /* TLB-entries for EBC:  CPLD, DUMEM, DUIO */
-       tlbentry( CONFIG_SYS_CPLD_BASE, SZ_1K, CONFIG_SYS_CPLD_BASE, 1, AC_R|AC_W|AC_X|SA_G|SA_I )
-       tlbentry( CONFIG_SYS_DUMEM_BASE, SZ_1M, CONFIG_SYS_DUMEM_BASE, 1, AC_R|AC_W|AC_X|SA_G|SA_I )
-       tlbentry( CONFIG_SYS_DUIO_BASE, SZ_64K, CONFIG_SYS_DUIO_BASE, 1, AC_R|AC_W|AC_X|SA_G|SA_I )
+       tlbentry( CONFIG_SYS_CPLD_BASE, SZ_1K, CONFIG_SYS_CPLD_BASE, 1, AC_RWX | SA_IG )
+       tlbentry( CONFIG_SYS_DUMEM_BASE, SZ_1M, CONFIG_SYS_DUMEM_BASE, 1, AC_RWX | SA_IG )
+       tlbentry( CONFIG_SYS_DUIO_BASE, SZ_64K, CONFIG_SYS_DUIO_BASE, 1, AC_RWX | SA_IG )
 
        /* TLB-entry for NAND */
-       tlbentry( CONFIG_SYS_NAND0_ADDR, SZ_1K, CONFIG_SYS_NAND0_ADDR, 1, AC_R|AC_W|AC_X|SA_G|SA_I )
-       tlbentry( CONFIG_SYS_NAND1_ADDR, SZ_1K, CONFIG_SYS_NAND1_ADDR, 1, AC_R|AC_W|AC_X|SA_G|SA_I )
+       tlbentry( CONFIG_SYS_NAND0_ADDR, SZ_1K, CONFIG_SYS_NAND0_ADDR, 1, AC_RWX | SA_IG )
+       tlbentry( CONFIG_SYS_NAND1_ADDR, SZ_1K, CONFIG_SYS_NAND1_ADDR, 1, AC_RWX | SA_IG )
 
        /* TLB-entry for Internal Registers & OCM */
-       tlbentry( 0xe0000000, SZ_16M, 0xe0000000, 0,  AC_R|AC_W|AC_X|SA_I )
+       tlbentry( 0xe0000000, SZ_16M, 0xe0000000, 0,  AC_RWX | SA_I )
 
        /* TLB-entry PCI registers */
-       tlbentry( 0xEEC00000, SZ_1K, 0xEEC00000, 1,  AC_R|AC_W|AC_X|SA_G|SA_I )
+       tlbentry( 0xEEC00000, SZ_1K, 0xEEC00000, 1,  AC_RWX | SA_IG )
 
        /* TLB-entry for peripherals */
-       tlbentry( 0xEF000000, SZ_16M, 0xEF000000, 1, AC_R|AC_W|AC_X|SA_G|SA_I)
+       tlbentry( 0xEF000000, SZ_16M, 0xEF000000, 1, AC_RWX | SA_IG)
 
        tlbtab_end

diff --git a/board/esd/pmc440/init.S b/board/esd/pmc440/init.S
index d51cd0c..96f7206 100644 (file)
--- a/board/esd/pmc440/init.S
+++ b/board/esd/pmc440/init.S
@@ -44,23 +44,23 @@ tlbtab:
         * speed up boot process. It is patched after relocation to enable SA_I
         */
 #ifndef CONFIG_NAND_SPL
-       tlbentry( CONFIG_SYS_BOOT_BASE_ADDR, SZ_256M, CONFIG_SYS_BOOT_BASE_ADDR, 1, AC_R|AC_W|AC_X|SA_G )
+       tlbentry( CONFIG_SYS_BOOT_BASE_ADDR, SZ_256M, CONFIG_SYS_BOOT_BASE_ADDR, 1, AC_RWX | SA_G )
 #else
-       tlbentry( CONFIG_SYS_NAND_BOOT_SPL_SRC, SZ_4K, CONFIG_SYS_NAND_BOOT_SPL_SRC, 1, AC_R|AC_W|AC_X|SA_G )
+       tlbentry( CONFIG_SYS_NAND_BOOT_SPL_SRC, SZ_4K, CONFIG_SYS_NAND_BOOT_SPL_SRC, 1, AC_RWX | SA_G )
 #endif
 
        /* TLB entries for DDR2 SDRAM are generated dynamically */
 
 #ifdef CONFIG_SYS_INIT_RAM_DCACHE
        /* TLB-entry for init-ram in dcache (SA_I must be turned off!) */
-       tlbentry( CONFIG_SYS_INIT_RAM_ADDR, SZ_64K, CONFIG_SYS_INIT_RAM_ADDR, 0, AC_R|AC_W|AC_X|SA_G )
+       tlbentry( CONFIG_SYS_INIT_RAM_ADDR, SZ_64K, CONFIG_SYS_INIT_RAM_ADDR, 0, AC_RWX | SA_G )
 #endif
 
        /* TLB-entry for PCI Memory */
-       tlbentry( CONFIG_SYS_PCI_MEMBASE, SZ_256M, CONFIG_SYS_PCI_MEMBASE, 1, AC_R|AC_W|SA_G|SA_I )
-       tlbentry( CONFIG_SYS_PCI_MEMBASE1, SZ_256M, CONFIG_SYS_PCI_MEMBASE1, 1, AC_R|AC_W|SA_G|SA_I )
-       tlbentry( CONFIG_SYS_PCI_MEMBASE2, SZ_256M, CONFIG_SYS_PCI_MEMBASE2, 1, AC_R|AC_W|SA_G|SA_I )
-       tlbentry( CONFIG_SYS_PCI_MEMBASE3, SZ_256M, CONFIG_SYS_PCI_MEMBASE3, 1, AC_R|AC_W|SA_G|SA_I )
+       tlbentry( CONFIG_SYS_PCI_MEMBASE, SZ_256M, CONFIG_SYS_PCI_MEMBASE, 1, AC_RW | SA_IG )
+       tlbentry( CONFIG_SYS_PCI_MEMBASE1, SZ_256M, CONFIG_SYS_PCI_MEMBASE1, 1, AC_RW | SA_IG )
+       tlbentry( CONFIG_SYS_PCI_MEMBASE2, SZ_256M, CONFIG_SYS_PCI_MEMBASE2, 1, AC_RW | SA_IG )
+       tlbentry( CONFIG_SYS_PCI_MEMBASE3, SZ_256M, CONFIG_SYS_PCI_MEMBASE3, 1, AC_RW | SA_IG )
 
        /* TLB-entries for EBC */
        /* PMC440 maps EBC to 0xef000000 which is handled by the peripheral
@@ -68,22 +68,22 @@ tlbtab:
         * This dummy entry is only for convinience in order not to modify the
         * amount of entries. Currently OS/9 relies on this :-)
         */
-       tlbentry( 0xc0000000, SZ_256M, 0xc0000000, 1, AC_R|AC_W|AC_X|SA_G|SA_I )
+       tlbentry( 0xc0000000, SZ_256M, 0xc0000000, 1, AC_RWX | SA_IG )
 
        /* TLB-entry for NAND */
-       tlbentry( CONFIG_SYS_NAND_ADDR, SZ_1K, CONFIG_SYS_NAND_ADDR, 1, AC_R|AC_W|AC_X|SA_G|SA_I )
+       tlbentry( CONFIG_SYS_NAND_ADDR, SZ_1K, CONFIG_SYS_NAND_ADDR, 1, AC_RWX | SA_IG )
 
        /* TLB-entry for Internal Registers & OCM */
-       tlbentry( 0xe0000000, SZ_16M, 0xe0000000, 0,  AC_R|AC_W|AC_X|SA_I )
+       tlbentry( 0xe0000000, SZ_16M, 0xe0000000, 0,  AC_RWX | SA_I )
 
        /*TLB-entry PCI registers*/
-       tlbentry( 0xEEC00000, SZ_1K, 0xEEC00000, 1,  AC_R|AC_W|AC_X|SA_G|SA_I )
+       tlbentry( 0xEEC00000, SZ_1K, 0xEEC00000, 1,  AC_RWX | SA_IG )
 
        /* TLB-entry for peripherals */
-       tlbentry( 0xEF000000, SZ_16M, 0xEF000000, 1, AC_R|AC_W|AC_X|SA_G|SA_I)
+       tlbentry( 0xEF000000, SZ_16M, 0xEF000000, 1, AC_RWX | SA_IG)
 
        /* TLB-entry PCI IO space */
-       tlbentry(0xE8000000, SZ_64K, 0xE8000000, 1, AC_R|AC_W|AC_X|SA_G|SA_I)
+       tlbentry(0xE8000000, SZ_64K, 0xE8000000, 1, AC_RWX | SA_IG)
 
        /* TODO:  what about high IO space */
        tlbtab_end
@@ -95,7 +95,7 @@ tlbtab:
         */
 #define TLB00  TLB0(CONFIG_SYS_BOOT_BASE_ADDR, SZ_256M)
 #define TLB01  TLB1(CONFIG_SYS_BOOT_BASE_ADDR, 1)
-#define TLB02  TLB2(AC_R|AC_W|AC_X|SA_G|SA_I)
+#define TLB02  TLB2(AC_RWX | SA_IG)
 
        .globl  reconfig_tlb0
 reconfig_tlb0:

diff --git a/board/gdsys/gdppc440etx/init.S b/board/gdsys/gdppc440etx/init.S
index 0bbd45a..ba750cb 100644 (file)
--- a/board/gdsys/gdppc440etx/init.S
+++ b/board/gdsys/gdppc440etx/init.S
@@ -51,25 +51,25 @@ tlbtab:
      * the speed up boot process. It is patched after relocation to enable SA_I
      */
     tlbentry( CONFIG_SYS_BOOT_BASE_ADDR, SZ_256M, CONFIG_SYS_BOOT_BASE_ADDR,
-       0, AC_R|AC_W|AC_X|SA_G/*|SA_I*/)
+       0, AC_RWX | SA_G/*|SA_I*/)
 
     /* TLB-entry for init-ram in dcache (SA_I must be turned off!) */
     tlbentry( CONFIG_SYS_INIT_RAM_ADDR, SZ_64K, CONFIG_SYS_INIT_RAM_ADDR,
-       0, AC_R|AC_W|AC_X|SA_G )
+       0, AC_RWX | SA_G )
 
     tlbentry( CONFIG_SYS_SDRAM_BASE, SZ_256M, CONFIG_SYS_SDRAM_BASE,
-       0, AC_R|AC_W|AC_X|SA_G|SA_I )
+       0, AC_RWX | SA_IG )
     tlbentry( CONFIG_SYS_PCI_BASE, SZ_256M, CONFIG_SYS_PCI_BASE,
-       0, AC_R|AC_W|SA_G|SA_I )
+       0, AC_RW | SA_IG )
 
     /* PCI */
     tlbentry( CONFIG_SYS_PCI_MEMBASE, SZ_256M, CONFIG_SYS_PCI_MEMBASE,
-       0, AC_R|AC_W|SA_G|SA_I )
+       0, AC_RW | SA_IG )
     tlbentry( CONFIG_SYS_PCI_MEMBASE1, SZ_256M, CONFIG_SYS_PCI_MEMBASE1,
-       0, AC_R|AC_W|SA_G|SA_I )
+       0, AC_RW | SA_IG )
     tlbentry( CONFIG_SYS_PCI_MEMBASE2, SZ_256M, CONFIG_SYS_PCI_MEMBASE2,
-       0, AC_R|AC_W|SA_G|SA_I )
+       0, AC_RW | SA_IG )
     tlbentry( CONFIG_SYS_PCI_MEMBASE3, SZ_256M, CONFIG_SYS_PCI_MEMBASE3,
-       0, AC_R|AC_W|SA_G|SA_I )
+       0, AC_RW | SA_IG )
 
     tlbtab_end

diff --git a/board/gdsys/intip/init.S b/board/gdsys/intip/init.S
index a8e8b6c..5a819c2 100644 (file)
--- a/board/gdsys/intip/init.S
+++ b/board/gdsys/intip/init.S
@@ -51,7 +51,7 @@ tlbtab:
         * enable SA_I
         */
        tlbentry(CONFIG_SYS_BOOT_BASE_ADDR, SZ_16M, CONFIG_SYS_BOOT_BASE_ADDR,
-               4, AC_R|AC_W|AC_X|SA_G) /* TLB 0 */
+               4, AC_RWX | SA_G) /* TLB 0 */
 
        /*
         * TLB entries for SDRAM are not needed on this platform.
@@ -62,36 +62,36 @@ tlbtab:
 #ifdef CONFIG_SYS_INIT_RAM_DCACHE
        /* TLB-entry for init-ram in dcache (SA_I must be turned off!) */
        tlbentry(CONFIG_SYS_INIT_RAM_ADDR, SZ_4K, CONFIG_SYS_INIT_RAM_ADDR,
-               0, AC_R|AC_W|AC_X|SA_G)
+               0, AC_RWX | SA_G)
 #endif
 
        tlbentry(CONFIG_SYS_PCI_BASE, SZ_256M, 0x00000000, 0xC,
-               AC_R|AC_W|SA_G|SA_I)
+               AC_RW | SA_IG)
        tlbentry(CONFIG_SYS_PCI_MEMBASE, SZ_256M, 0x20000000, 0xC,
-               AC_R|AC_W|SA_G|SA_I)
+               AC_RW | SA_IG)
 
        /* TLB-entry for NVRAM */
        tlbentry(CONFIG_SYS_NVRAM_BASE, SZ_1M, CONFIG_SYS_NVRAM_BASE, 4,
-               AC_R|AC_W|SA_G|SA_I)
+               AC_RW | SA_IG)
 
        /* TLB-entry for UART */
        tlbentry(CONFIG_SYS_UART_BASE, SZ_16K, CONFIG_SYS_UART_BASE, 4,
-               AC_R|AC_W|SA_G|SA_I)
+               AC_RW | SA_IG)
 
        /* TLB-entry for IO */
        tlbentry(CONFIG_SYS_IO_BASE, SZ_16K, CONFIG_SYS_IO_BASE, 4,
-               AC_R|AC_W|SA_G|SA_I)
+               AC_RW | SA_IG)
 
        /* TLB-entry for OCM */
        tlbentry(CONFIG_SYS_OCM_BASE, SZ_1M, 0x00000000, 4,
-               AC_R|AC_W|AC_X|SA_I)
+               AC_RWX | SA_I)
 
        /* TLB-entry for Local Configuration registers => peripherals */
        tlbentry(CONFIG_SYS_LOCAL_CONF_REGS, SZ_16M, CONFIG_SYS_LOCAL_CONF_REGS,
-               4, AC_R|AC_W|AC_X|SA_G|SA_I)
+               4, AC_RWX | SA_IG)
 
        /* AHB: Internal USB Peripherals (USB, SATA) */
        tlbentry(CONFIG_SYS_AHB_BASE, SZ_1M, 0xbff00000, 4,
-               AC_R|AC_W|AC_X|SA_G|SA_I)
+               AC_RWX | SA_IG)
 
        tlbtab_end

diff --git a/board/korat/init.S b/board/korat/init.S
index c725bbb..bfc6bc1 100644 (file)
--- a/board/korat/init.S
+++ b/board/korat/init.S
@@ -43,7 +43,7 @@ tlbtab:
         * BOOT_CS (FLASH) must be first. Before relocation SA_I can be off to use the
         * speed up boot process. It is patched after relocation to enable SA_I
         */
-       tlbentry( 0xF0000000, SZ_256M, 0xF0000000, 1, AC_R|AC_W|AC_X|SA_G )
+       tlbentry( 0xF0000000, SZ_256M, 0xF0000000, 1, AC_RWX | SA_G )
 
        /*
         * TLB entries for SDRAM are not needed on this platform.  They are
@@ -53,37 +53,37 @@ tlbtab:
 #ifdef CONFIG_SYS_INIT_RAM_DCACHE
        /* TLB-entry for init-ram in dcache (SA_I must be turned off!) */
        tlbentry( CONFIG_SYS_INIT_RAM_ADDR, SZ_64K, CONFIG_SYS_INIT_RAM_ADDR, 0,
-                 AC_R|AC_W|AC_X|SA_G )
+                 AC_RWX | SA_G )
 #endif
 
        /* TLB-entry for PCI Memory */
        tlbentry( CONFIG_SYS_PCI_MEMBASE + 0x00000000, SZ_256M,
-                 CONFIG_SYS_PCI_MEMBASE + 0x00000000, 1, AC_R|AC_W|SA_G|SA_I )
+                 CONFIG_SYS_PCI_MEMBASE + 0x00000000, 1, AC_RW | SA_IG )
 
        tlbentry( CONFIG_SYS_PCI_MEMBASE + 0x10000000, SZ_256M,
-                 CONFIG_SYS_PCI_MEMBASE + 0x10000000, 1, AC_R|AC_W|SA_G|SA_I )
+                 CONFIG_SYS_PCI_MEMBASE + 0x10000000, 1, AC_RW | SA_IG )
 
        tlbentry( CONFIG_SYS_PCI_MEMBASE + 0x20000000, SZ_256M,
-                 CONFIG_SYS_PCI_MEMBASE + 0x20000000, 1, AC_R|AC_W|SA_G|SA_I )
+                 CONFIG_SYS_PCI_MEMBASE + 0x20000000, 1, AC_RW | SA_IG )
 
        tlbentry( CONFIG_SYS_PCI_MEMBASE + 0x30000000, SZ_256M,
-                 CONFIG_SYS_PCI_MEMBASE + 0x30000000, 1, AC_R|AC_W|SA_G|SA_I )
+                 CONFIG_SYS_PCI_MEMBASE + 0x30000000, 1, AC_RW | SA_IG )
 
        /* TLB-entry for EBC */
-       tlbentry( CONFIG_SYS_CPLD_BASE, SZ_1K, CONFIG_SYS_CPLD_BASE, 1, AC_R|AC_W|SA_G|SA_I )
+       tlbentry( CONFIG_SYS_CPLD_BASE, SZ_1K, CONFIG_SYS_CPLD_BASE, 1, AC_RW | SA_IG )
 
        /* TLB-entry for Internal Registers & OCM */
        /* I wonder why this must be executable -- lrj@acm.org 2007-10-08 */
-       tlbentry( 0xE0000000, SZ_16M, 0xE0000000, 0, AC_R|AC_W|AC_X|SA_I )
+       tlbentry( 0xE0000000, SZ_16M, 0xE0000000, 0, AC_RWX | SA_I )
 
        /*TLB-entry PCI registers*/
-       tlbentry( 0xEEC00000, SZ_1K, 0xEEC00000, 1, AC_R|AC_W|SA_G|SA_I )
+       tlbentry( 0xEEC00000, SZ_1K, 0xEEC00000, 1, AC_RW | SA_IG )
 
        /* TLB-entry for peripherals */
-       tlbentry( 0xEF000000, SZ_16M, 0xEF000000, 1, AC_R|AC_W|SA_G|SA_I)
+       tlbentry( 0xEF000000, SZ_16M, 0xEF000000, 1, AC_RW | SA_IG)
 
        /* TLB-entry PCI IO Space - from sr@denx.de */
-       tlbentry(0xE8000000, SZ_64K, 0xE8000000, 1, AC_R|AC_W|SA_G|SA_I)
+       tlbentry(0xE8000000, SZ_64K, 0xE8000000, 1, AC_RW | SA_IG)
 
        tlbtab_end
 

diff --git a/board/lwmon5/init.S b/board/lwmon5/init.S
index c714fb7..8efc8a1 100644 (file)
--- a/board/lwmon5/init.S
+++ b/board/lwmon5/init.S
@@ -47,7 +47,7 @@ tlbtab:
         * BOOT_CS (FLASH) must be first. Before relocation SA_I can be off to use the
         * speed up boot process. It is patched after relocation to enable SA_I
         */
-       tlbentry(CONFIG_SYS_BOOT_BASE_ADDR, SZ_256M, CONFIG_SYS_BOOT_BASE_ADDR, 1, AC_R|AC_W|AC_X|SA_G)
+       tlbentry(CONFIG_SYS_BOOT_BASE_ADDR, SZ_256M, CONFIG_SYS_BOOT_BASE_ADDR, 1, AC_RWX | SA_G)
 
        /*
         * TLB entries for SDRAM are not needed on this platform.
@@ -57,34 +57,34 @@ tlbtab:
 
 #ifdef CONFIG_SYS_INIT_RAM_DCACHE
        /* TLB-entry for init-ram in dcache (SA_I must be turned off!) */
-       tlbentry(CONFIG_SYS_INIT_RAM_ADDR, SZ_4K, CONFIG_SYS_INIT_RAM_ADDR, 0, AC_R|AC_W|AC_X|SA_G)
+       tlbentry(CONFIG_SYS_INIT_RAM_ADDR, SZ_4K, CONFIG_SYS_INIT_RAM_ADDR, 0, AC_RWX | SA_G)
 #endif
 
        /* TLB-entry for PCI Memory */
-       tlbentry(CONFIG_SYS_PCI_MEMBASE, SZ_256M, CONFIG_SYS_PCI_MEMBASE, 1, AC_R|AC_W|SA_G|SA_I)
-       tlbentry(CONFIG_SYS_PCI_MEMBASE1, SZ_256M, CONFIG_SYS_PCI_MEMBASE1, 1, AC_R|AC_W|SA_G|SA_I)
-       tlbentry(CONFIG_SYS_PCI_MEMBASE2, SZ_256M, CONFIG_SYS_PCI_MEMBASE2, 1, AC_R|AC_W|SA_G|SA_I)
-       tlbentry(CONFIG_SYS_PCI_MEMBASE3, SZ_256M, CONFIG_SYS_PCI_MEMBASE3, 1, AC_R|AC_W|SA_G|SA_I)
+       tlbentry(CONFIG_SYS_PCI_MEMBASE, SZ_256M, CONFIG_SYS_PCI_MEMBASE, 1, AC_RW | SA_IG)
+       tlbentry(CONFIG_SYS_PCI_MEMBASE1, SZ_256M, CONFIG_SYS_PCI_MEMBASE1, 1, AC_RW | SA_IG)
+       tlbentry(CONFIG_SYS_PCI_MEMBASE2, SZ_256M, CONFIG_SYS_PCI_MEMBASE2, 1, AC_RW | SA_IG)
+       tlbentry(CONFIG_SYS_PCI_MEMBASE3, SZ_256M, CONFIG_SYS_PCI_MEMBASE3, 1, AC_RW | SA_IG)
 
        /* TLB-entry for the FPGA Chip select 2 */
-       tlbentry(CONFIG_SYS_FPGA_BASE_0, SZ_1M, CONFIG_SYS_FPGA_BASE_0, 1, AC_R|AC_W|AC_X|SA_I|SA_G)
+       tlbentry(CONFIG_SYS_FPGA_BASE_0, SZ_1M, CONFIG_SYS_FPGA_BASE_0, 1, AC_RWX | SA_I|SA_G)
 
        /* TLB-entry for the FPGA Chip select 3 */
-       tlbentry(CONFIG_SYS_FPGA_BASE_1, SZ_1M, CONFIG_SYS_FPGA_BASE_1, 1,AC_R|AC_W|AC_X|SA_I|SA_G)
+       tlbentry(CONFIG_SYS_FPGA_BASE_1, SZ_1M, CONFIG_SYS_FPGA_BASE_1, 1,AC_RWX | SA_I|SA_G)
 
        /* TLB-entry for the LIME Controller */
-       tlbentry(CONFIG_SYS_LIME_BASE_0, SZ_16M, CONFIG_SYS_LIME_BASE_0, 1, AC_R|AC_W|AC_X|SA_I|SA_G)
-       tlbentry(CONFIG_SYS_LIME_BASE_1, SZ_16M, CONFIG_SYS_LIME_BASE_1, 1, AC_R|AC_W|AC_X|SA_I|SA_G)
-       tlbentry(CONFIG_SYS_LIME_BASE_2, SZ_16M, CONFIG_SYS_LIME_BASE_2, 1, AC_R|AC_W|AC_X|SA_I|SA_G)
-       tlbentry(CONFIG_SYS_LIME_BASE_3, SZ_16M, CONFIG_SYS_LIME_BASE_3, 1, AC_R|AC_W|AC_X|SA_I|SA_G)
+       tlbentry(CONFIG_SYS_LIME_BASE_0, SZ_16M, CONFIG_SYS_LIME_BASE_0, 1, AC_RWX | SA_I|SA_G)
+       tlbentry(CONFIG_SYS_LIME_BASE_1, SZ_16M, CONFIG_SYS_LIME_BASE_1, 1, AC_RWX | SA_I|SA_G)
+       tlbentry(CONFIG_SYS_LIME_BASE_2, SZ_16M, CONFIG_SYS_LIME_BASE_2, 1, AC_RWX | SA_I|SA_G)
+       tlbentry(CONFIG_SYS_LIME_BASE_3, SZ_16M, CONFIG_SYS_LIME_BASE_3, 1, AC_RWX | SA_I|SA_G)
 
        /* TLB-entry for Internal Registers & OCM */
-       tlbentry(0xe0000000, SZ_16M, 0xe0000000, 0,  AC_R|AC_W|AC_X|SA_I)
+       tlbentry(0xe0000000, SZ_16M, 0xe0000000, 0,  AC_RWX | SA_I)
 
        /*TLB-entry PCI registers*/
-       tlbentry(0xEEC00000, SZ_1K, 0xEEC00000, 1,  AC_R|AC_W|AC_X|SA_G|SA_I)
+       tlbentry(0xEEC00000, SZ_1K, 0xEEC00000, 1,  AC_RWX | SA_IG)
 
        /* TLB-entry for peripherals */
-       tlbentry(0xEF000000, SZ_16M, 0xEF000000, 1, AC_R|AC_W|AC_X|SA_G|SA_I)
+       tlbentry(0xEF000000, SZ_16M, 0xEF000000, 1, AC_RWX | SA_IG)
 
        tlbtab_end

diff --git a/board/netstal/hcu5/init.S b/board/netstal/hcu5/init.S
index 05b5e38..45e63dd 100644 (file)
--- a/board/netstal/hcu5/init.S
+++ b/board/netstal/hcu5/init.S
@@ -40,13 +40,13 @@ tlbtab:
        tlbtab_start
 
        /* TLB#0: vxWorks needs this entry for the Machine Check interrupt, */
-       tlbentry( 0x40000000, SZ_256M, 0, 0, AC_R|AC_W|AC_X|SA_G|SA_I )
+       tlbentry( 0x40000000, SZ_256M, 0, 0, AC_RWX | SA_IG )
        /* TLB#1: TLB-entry for DDR SDRAM (Up to 2GB) */
        tlbentry( CONFIG_SYS_SDRAM_BASE, SZ_256M, CONFIG_SYS_SDRAM_BASE, 0,
-               AC_R|AC_W|AC_X|SA_G|SA_I )
+               AC_RWX | SA_IG )
 
        /* TLB#2: TLB-entry for EBC */
-       tlbentry( 0x80000000, SZ_256M, 0x80000000, 1, AC_R|AC_W|AC_X|SA_G|SA_I)
+       tlbentry( 0x80000000, SZ_256M, 0x80000000, 1, AC_RWX | SA_IG)
 
        /*
         * TLB#3: BOOT_CS (FLASH) must be forth. Before relocation SA_I can be
@@ -54,7 +54,7 @@ tlbtab:
         * to enable SA_I
         */
        tlbentry( CONFIG_SYS_BOOT_BASE_ADDR, SZ_1M, CONFIG_SYS_BOOT_BASE_ADDR, 1,
-               AC_R|AC_W|AC_X|SA_G)
+               AC_RWX | SA_G)
 
        /*
         * TLB entries for SDRAM are not needed on this platform.
@@ -64,43 +64,43 @@ tlbtab:
 
        /* TLB#4: */
        tlbentry( CONFIG_SYS_PCI_MEMBASE1, SZ_256M, CONFIG_SYS_PCI_MEMBASE1, 1,
-               AC_R|AC_W|SA_G|SA_I )
+               AC_RW | SA_IG )
        /* TLB#5: */
        tlbentry( CONFIG_SYS_PCI_MEMBASE2, SZ_256M, CONFIG_SYS_PCI_MEMBASE2, 1,
-               AC_R|AC_W|SA_G|SA_I )
+               AC_RW | SA_IG )
        /* TLB#6: */
        tlbentry( CONFIG_SYS_PCI_MEMBASE3, SZ_256M, CONFIG_SYS_PCI_MEMBASE3, 1,
-               AC_R|AC_W|SA_G|SA_I )
+               AC_RW | SA_IG )
 
        /* TLB-entry for Internal Registers & OCM */
        /* TLB#7: */
        tlbentry( 0xe0000000, SZ_16M, 0xe0000000, 0,
-               AC_R|AC_W|AC_X|SA_G|SA_I )
+               AC_RWX | SA_IG )
 
        /*TLB-entry PCI registers*/
        /* TLB#8: */
-       tlbentry( 0xEEC00000, SZ_1K, 0xEEC00000, 1,  AC_R|AC_W|AC_X|SA_G|SA_I )
+       tlbentry( 0xEEC00000, SZ_1K, 0xEEC00000, 1,  AC_RWX | SA_IG )
 
        /* TLB-entry for peripherals */
        /* TLB#9: */
-       tlbentry( 0xEF000000, SZ_16M, 0xEF000000, 1, AC_R|AC_W|AC_X|SA_G|SA_I)
+       tlbentry( 0xEF000000, SZ_16M, 0xEF000000, 1, AC_RWX | SA_IG)
 
        /*              CAN */
        /* TLB#10: */
-       tlbentry( CONFIG_SYS_CS_1, SZ_1K, CONFIG_SYS_CS_1, 1, AC_R|AC_W|AC_X|SA_G|SA_I )
+       tlbentry( CONFIG_SYS_CS_1, SZ_1K, CONFIG_SYS_CS_1, 1, AC_RWX | SA_IG )
 
        /* TLB#11:  CPLD and IMC-Standard 32 MB */
-       tlbentry( CONFIG_SYS_CS_2, SZ_16M, CONFIG_SYS_CS_2, 1, AC_R|AC_W|AC_X|SA_G|SA_I )
+       tlbentry( CONFIG_SYS_CS_2, SZ_16M, CONFIG_SYS_CS_2, 1, AC_RWX | SA_IG )
 
        /* TLB#12: */
        tlbentry( CONFIG_SYS_CS_2 + 0x1000000, SZ_16M, CONFIG_SYS_CS_2 + 0x1000000, 1,
-               AC_R|AC_W|AC_X|SA_G|SA_I )
+               AC_RWX | SA_IG )
 
         /*             IMC-Fast 32 MB */
        /* TLB#13: */
-       tlbentry( CONFIG_SYS_CS_3, SZ_16M, CONFIG_SYS_CS_3, 1, AC_R|AC_W|AC_X|SA_G|SA_I )
+       tlbentry( CONFIG_SYS_CS_3, SZ_16M, CONFIG_SYS_CS_3, 1, AC_RWX | SA_IG )
        /* TLB#14: */
        tlbentry( CONFIG_SYS_CS_3 + 0x1000000, SZ_16M, CONFIG_SYS_CS_3, 1,
-               AC_R|AC_W|AC_X|SA_G|SA_I )
+               AC_RWX | SA_IG )
 
        tlbtab_end

diff --git a/board/pcs440ep/init.S b/board/pcs440ep/init.S
index 25e7f4f..9745c14 100644 (file)
--- a/board/pcs440ep/init.S
+++ b/board/pcs440ep/init.S
@@ -22,56 +22,9 @@
  */
 
 #include <ppc_asm.tmpl>
+#include <asm/mmu.h>
 #include <config.h>
 
-/* General */
-#define TLB_VALID   0x00000200
-
-/* Supported page sizes */
-
-#define SZ_1K      0x00000000
-#define SZ_4K      0x00000010
-#define SZ_16K     0x00000020
-#define SZ_64K     0x00000030
-#define SZ_256K            0x00000040
-#define SZ_1M      0x00000050
-#define SZ_8M       0x00000060
-#define SZ_16M     0x00000070
-#define SZ_256M            0x00000090
-
-/* Storage attributes */
-#define SA_W       0x00000800      /* Write-through */
-#define SA_I       0x00000400      /* Caching inhibited */
-#define SA_M       0x00000200      /* Memory coherence */
-#define SA_G       0x00000100      /* Guarded */
-#define SA_E       0x00000080      /* Endian */
-
-/* Access control */
-#define AC_X       0x00000024      /* Execute */
-#define AC_W       0x00000012      /* Write */
-#define AC_R       0x00000009      /* Read */
-
-/* Some handy macros */
-
-#define EPN(e)         ((e) & 0xfffffc00)
-#define TLB0(epn,sz)   ( (EPN((epn)) | (sz) | TLB_VALID ) )
-#define TLB1(rpn,erpn) ( ((rpn)&0xfffffc00) | (erpn) )
-#define TLB2(a)                ( (a)&0x00000fbf )
-
-#define tlbtab_start\
-       mflr    r1  ;\
-       bl 0f       ;
-
-#define tlbtab_end\
-       .long 0, 0, 0   ;   \
-0:     mflr    r0      ;   \
-       mtlr    r1      ;   \
-       blr             ;
-
-#define tlbentry(epn,sz,rpn,erpn,attr)\
-       .long TLB0(epn,sz),TLB1(rpn,erpn),TLB2(attr)
-
-
 /**************************************************************************
  * TLB TABLE
  *
@@ -93,10 +46,10 @@ tlbtab:
         * BOOT_CS (FLASH) must be first. Before relocation SA_I can be off to use the
         * speed up boot process. It is patched after relocation to enable SA_I
         */
-       tlbentry( CONFIG_SYS_BOOT_BASE_ADDR, SZ_256M, CONFIG_SYS_BOOT_BASE_ADDR, 0, AC_R|AC_W|AC_X|SA_G/*|SA_I*/)
+       tlbentry( CONFIG_SYS_BOOT_BASE_ADDR, SZ_256M, CONFIG_SYS_BOOT_BASE_ADDR, 0, AC_RWX | SA_G/*|SA_I*/)
 
        /* TLB-entry for init-ram in dcache (SA_I must be turned off!) */
-       tlbentry( CONFIG_SYS_INIT_RAM_ADDR, SZ_64K, CONFIG_SYS_INIT_RAM_ADDR, 0, AC_R|AC_W|AC_X|SA_G )
+       tlbentry( CONFIG_SYS_INIT_RAM_ADDR, SZ_64K, CONFIG_SYS_INIT_RAM_ADDR, 0, AC_RWX | SA_G )
 
        /*
         * TLB entries for SDRAM are not needed on this platform.
@@ -104,15 +57,15 @@ tlbtab:
         * routine.
         */
 
-       tlbentry( CONFIG_SYS_PCI_BASE, SZ_256M, CONFIG_SYS_PCI_BASE, 0, AC_R|AC_W|SA_G|SA_I )
+       tlbentry( CONFIG_SYS_PCI_BASE, SZ_256M, CONFIG_SYS_PCI_BASE, 0, AC_RW | SA_IG )
 
        /* PCI */
-       tlbentry( CONFIG_SYS_PCI_MEMBASE, SZ_256M, CONFIG_SYS_PCI_MEMBASE, 0, AC_R|AC_W|SA_G|SA_I )
-       tlbentry( CONFIG_SYS_PCI_MEMBASE1, SZ_256M, CONFIG_SYS_PCI_MEMBASE1, 0, AC_R|AC_W|SA_G|SA_I )
-       tlbentry( CONFIG_SYS_PCI_MEMBASE2, SZ_256M, CONFIG_SYS_PCI_MEMBASE2, 0, AC_R|AC_W|SA_G|SA_I )
-       tlbentry( CONFIG_SYS_PCI_MEMBASE3, SZ_256M, CONFIG_SYS_PCI_MEMBASE3, 0, AC_R|AC_W|SA_G|SA_I )
+       tlbentry( CONFIG_SYS_PCI_MEMBASE, SZ_256M, CONFIG_SYS_PCI_MEMBASE, 0, AC_RW | SA_IG )
+       tlbentry( CONFIG_SYS_PCI_MEMBASE1, SZ_256M, CONFIG_SYS_PCI_MEMBASE1, 0, AC_RW | SA_IG )
+       tlbentry( CONFIG_SYS_PCI_MEMBASE2, SZ_256M, CONFIG_SYS_PCI_MEMBASE2, 0, AC_RW | SA_IG )
+       tlbentry( CONFIG_SYS_PCI_MEMBASE3, SZ_256M, CONFIG_SYS_PCI_MEMBASE3, 0, AC_RW | SA_IG )
 
        /* USB 2.0 Device */
-       tlbentry( CONFIG_SYS_USB_DEVICE, SZ_1K, 0x50000000, 0, AC_R|AC_W|SA_G|SA_I )
+       tlbentry( CONFIG_SYS_USB_DEVICE, SZ_1K, 0x50000000, 0, AC_RW | SA_IG )
 
        tlbtab_end

diff --git a/board/prodrive/alpr/init.S b/board/prodrive/alpr/init.S
index 4af7d13..9f9812a 100644 (file)
--- a/board/prodrive/alpr/init.S
+++ b/board/prodrive/alpr/init.S
@@ -22,54 +22,9 @@
  */
 
 #include <ppc_asm.tmpl>
+#include <asm/mmu.h>
 #include <config.h>
 
-/* General */
-#define TLB_VALID   0x00000200
-
-/* Supported page sizes */
-#define SZ_1K      0x00000000
-#define SZ_4K      0x00000010
-#define SZ_16K     0x00000020
-#define SZ_64K     0x00000030
-#define SZ_256K            0x00000040
-#define SZ_1M      0x00000050
-#define SZ_16M     0x00000070
-#define SZ_256M            0x00000090
-
-/* Storage attributes */
-#define SA_W       0x00000800      /* Write-through */
-#define SA_I       0x00000400      /* Caching inhibited */
-#define SA_M       0x00000200      /* Memory coherence */
-#define SA_G       0x00000100      /* Guarded */
-#define SA_E       0x00000080      /* Endian */
-
-/* Access control */
-#define AC_X       0x00000024      /* Execute */
-#define AC_W       0x00000012      /* Write */
-#define AC_R       0x00000009      /* Read */
-
-/* Some handy macros */
-
-#define EPN(e)         ((e) & 0xfffffc00)
-#define TLB0(epn,sz)   ( (EPN((epn)) | (sz) | TLB_VALID ) )
-#define TLB1(rpn,erpn) ( ((rpn)&0xfffffc00) | (erpn) )
-#define TLB2(a)        ( (a)&0x00000fbf )
-
-#define tlbtab_start\
-       mflr    r1  ;\
-       bl 0f       ;
-
-#define tlbtab_end\
-       .long 0, 0, 0   ;   \
-0:     mflr    r0      ;   \
-       mtlr    r1      ;   \
-       blr             ;
-
-#define tlbentry(epn,sz,rpn,erpn,attr)\
-       .long TLB0(epn,sz),TLB1(rpn,erpn),TLB2(attr)
-
-
 /**************************************************************************
  * TLB TABLE
  *
@@ -86,27 +41,27 @@
 
 tlbtab:
        tlbtab_start
-       tlbentry( 0xff000000, SZ_16M, 0xff000000, 1, AC_R|AC_W|AC_X|SA_G|SA_I )
-       tlbentry( CONFIG_SYS_PERIPHERAL_BASE, SZ_256M, 0x40000000, 1, AC_R|AC_W|SA_G|SA_I )
-       tlbentry( CONFIG_SYS_ISRAM_BASE, SZ_4K, 0x80000000, 0, AC_R|AC_W|AC_X )
-       tlbentry( CONFIG_SYS_ISRAM_BASE + 0x1000, SZ_4K, 0x80001000, 0, AC_R|AC_W|AC_X )
+       tlbentry(0xff000000, SZ_16M, 0xff000000, 1, AC_RWX | SA_IG )
+       tlbentry(CONFIG_SYS_PERIPHERAL_BASE, SZ_256M, 0x40000000, 1, AC_RW | SA_IG)
+       tlbentry(CONFIG_SYS_ISRAM_BASE, SZ_4K, 0x80000000, 0, AC_RWX)
+       tlbentry(CONFIG_SYS_ISRAM_BASE + 0x1000, SZ_4K, 0x80001000, 0, AC_RWX)
 #ifdef CONFIG_4xx_DCACHE
-       tlbentry( CONFIG_SYS_SDRAM_BASE, SZ_256M, 0x00000000, 0, AC_R|AC_W|AC_X|SA_G)
+       tlbentry(CONFIG_SYS_SDRAM_BASE, SZ_256M, 0x00000000, 0, AC_RWX | SA_G)
 #else
-       tlbentry( CONFIG_SYS_SDRAM_BASE, SZ_256M, 0x00000000, 0, AC_R|AC_W|AC_X|SA_G|SA_I )
+       tlbentry(CONFIG_SYS_SDRAM_BASE, SZ_256M, 0x00000000, 0, AC_RWX | SA_IG)
 #endif
 
 #ifdef CONFIG_SYS_INIT_RAM_DCACHE
        /* TLB-entry for init-ram in dcache (SA_I must be turned off!) */
-       tlbentry( CONFIG_SYS_INIT_RAM_ADDR, SZ_64K, CONFIG_SYS_INIT_RAM_ADDR, 0, AC_R|AC_W|AC_X|SA_G )
+       tlbentry(CONFIG_SYS_INIT_RAM_ADDR, SZ_64K, CONFIG_SYS_INIT_RAM_ADDR, 0, AC_RWX | SA_G)
 #endif
-       tlbentry( CONFIG_SYS_PCI_BASE, SZ_256M, 0x00000000, 2, AC_R|AC_W|SA_G|SA_I )
+       tlbentry(CONFIG_SYS_PCI_BASE, SZ_256M, 0x00000000, 2, AC_RW | SA_IG)
 
        /* PCI */
-       tlbentry( CONFIG_SYS_PCI_MEMBASE, SZ_256M, CONFIG_SYS_PCI_MEMBASE, 3, AC_R|AC_W|SA_G|SA_I )
-       tlbentry( CONFIG_SYS_PCI_MEMBASE1, SZ_256M, CONFIG_SYS_PCI_MEMBASE1, 3, AC_R|AC_W|SA_G|SA_I )
-       tlbentry( CONFIG_SYS_PCI_MEMBASE2, SZ_256M, CONFIG_SYS_PCI_MEMBASE2, 3, AC_R|AC_W|SA_G|SA_I )
+       tlbentry(CONFIG_SYS_PCI_MEMBASE, SZ_256M, CONFIG_SYS_PCI_MEMBASE, 3, AC_RW | SA_IG)
+       tlbentry(CONFIG_SYS_PCI_MEMBASE1, SZ_256M, CONFIG_SYS_PCI_MEMBASE1, 3, AC_RW | SA_IG)
+       tlbentry(CONFIG_SYS_PCI_MEMBASE2, SZ_256M, CONFIG_SYS_PCI_MEMBASE2, 3, AC_RW | SA_IG)
 
        /* NAND */
-       tlbentry( CONFIG_SYS_NAND_BASE, SZ_4K, CONFIG_SYS_NAND_BASE, 1, AC_R|AC_W|AC_X|SA_G|SA_I )
+       tlbentry(CONFIG_SYS_NAND_BASE, SZ_4K, CONFIG_SYS_NAND_BASE, 1, AC_RWX | SA_IG)
        tlbtab_end

diff --git a/board/prodrive/p3p440/init.S b/board/prodrive/p3p440/init.S
index 8c1a79c..66acaf2 100644 (file)
--- a/board/prodrive/p3p440/init.S
+++ b/board/prodrive/p3p440/init.S
@@ -24,55 +24,9 @@
  */
 
 #include <ppc_asm.tmpl>
+#include <asm/mmu.h>
 #include <config.h>
 
-/* General */
-#define TLB_VALID   0x00000200
-
-/* Supported page sizes */
-
-#define SZ_1K      0x00000000
-#define SZ_4K      0x00000010
-#define SZ_16K     0x00000020
-#define SZ_64K     0x00000030
-#define SZ_256K            0x00000040
-#define SZ_1M      0x00000050
-#define SZ_16M     0x00000070
-#define SZ_256M            0x00000090
-
-/* Storage attributes */
-#define SA_W       0x00000800      /* Write-through */
-#define SA_I       0x00000400      /* Caching inhibited */
-#define SA_M       0x00000200      /* Memory coherence */
-#define SA_G       0x00000100      /* Guarded */
-#define SA_E       0x00000080      /* Endian */
-
-/* Access control */
-#define AC_X       0x00000024      /* Execute */
-#define AC_W       0x00000012      /* Write */
-#define AC_R       0x00000009      /* Read */
-
-/* Some handy macros */
-
-#define EPN(e)         ((e) & 0xfffffc00)
-#define TLB0(epn,sz)   ( (EPN((epn)) | (sz) | TLB_VALID ) )
-#define TLB1(rpn,erpn) ( ((rpn)&0xfffffc00) | (erpn) )
-#define TLB2(a)                ( (a)&0x00000fbf )
-
-#define tlbtab_start\
-       mflr    r1  ;\
-       bl 0f       ;
-
-#define tlbtab_end\
-       .long 0, 0, 0   ;   \
-0:     mflr    r0      ;   \
-       mtlr    r1      ;   \
-       blr             ;
-
-#define tlbentry(epn,sz,rpn,erpn,attr)\
-       .long TLB0(epn,sz),TLB1(rpn,erpn),TLB2(attr)
-
-
 /**************************************************************************
  * TLB TABLE
  *
@@ -89,11 +43,11 @@
 
 tlbtab:
     tlbtab_start
-    tlbentry( 0xf0000000, SZ_256M, 0xf0000000, 1, AC_R|AC_W|AC_X|SA_G|SA_I)
-    tlbentry( CONFIG_SYS_PERIPHERAL_BASE, SZ_256M, 0x40000000, 1, AC_R|AC_W|SA_G|SA_I)
-    tlbentry( CONFIG_SYS_ISRAM_BASE, SZ_4K, 0x80000000, 0, AC_R|AC_W|AC_X )
-    tlbentry( CONFIG_SYS_ISRAM_BASE + 0x1000, SZ_4K, 0x80001000, 0, AC_R|AC_W|AC_X )
-    tlbentry( CONFIG_SYS_SDRAM_BASE, SZ_256M, 0x00000000, 0, AC_R|AC_W|AC_X|SA_G|SA_I )
-    tlbentry( CONFIG_SYS_PCI_BASE, SZ_256M, 0x00000000, 2, AC_R|AC_W|SA_G|SA_I )
-    tlbentry( CONFIG_SYS_PCI_MEMBASE, SZ_256M, 0x00000000, 3, AC_R|AC_W|SA_G|SA_I )
+    tlbentry( 0xf0000000, SZ_256M, 0xf0000000, 1, AC_RWX | SA_IG)
+    tlbentry( CONFIG_SYS_PERIPHERAL_BASE, SZ_256M, 0x40000000, 1, AC_RW | SA_IG)
+    tlbentry( CONFIG_SYS_ISRAM_BASE, SZ_4K, 0x80000000, 0, AC_RWX )
+    tlbentry( CONFIG_SYS_ISRAM_BASE + 0x1000, SZ_4K, 0x80001000, 0, AC_RWX )
+    tlbentry( CONFIG_SYS_SDRAM_BASE, SZ_256M, 0x00000000, 0, AC_RWX | SA_IG )
+    tlbentry( CONFIG_SYS_PCI_BASE, SZ_256M, 0x00000000, 2, AC_RW | SA_IG )
+    tlbentry( CONFIG_SYS_PCI_MEMBASE, SZ_256M, 0x00000000, 3, AC_RW | SA_IG )
     tlbtab_end

diff --git a/board/sandburst/karef/init.S b/board/sandburst/karef/init.S
index 3198dfd..2bdae06 100644 (file)
--- a/board/sandburst/karef/init.S
+++ b/board/sandburst/karef/init.S
@@ -24,55 +24,9 @@
  */
 
 #include <ppc_asm.tmpl>
+#include <asm/mmu.h>
 #include <config.h>
 
-/* General */
-#define TLB_VALID   0x00000200
-
-/* Supported page sizes */
-
-#define SZ_1K      0x00000000
-#define SZ_4K      0x00000010
-#define SZ_16K     0x00000020
-#define SZ_64K     0x00000030
-#define SZ_256K            0x00000040
-#define SZ_1M      0x00000050
-#define SZ_16M     0x00000070
-#define SZ_256M            0x00000090
-
-/* Storage attributes */
-#define SA_W       0x00000800      /* Write-through */
-#define SA_I       0x00000400      /* Caching inhibited */
-#define SA_M       0x00000200      /* Memory coherence */
-#define SA_G       0x00000100      /* Guarded */
-#define SA_E       0x00000080      /* Endian */
-
-/* Access control */
-#define AC_X       0x00000024      /* Execute */
-#define AC_W       0x00000012      /* Write */
-#define AC_R       0x00000009      /* Read */
-
-/* Some handy macros */
-
-#define EPN(e)         ((e) & 0xfffffc00)
-#define TLB0(epn,sz)   ( (EPN((epn)) | (sz) | TLB_VALID ) )
-#define TLB1(rpn,erpn) ( ((rpn)&0xfffffc00) | (erpn) )
-#define TLB2(a)                ( (a)&0x00000fbf )
-
-#define tlbtab_start\
-       mflr    r1  ;\
-       bl 0f       ;
-
-#define tlbtab_end\
-       .long 0, 0, 0   ;   \
-0:     mflr    r0      ;   \
-       mtlr    r1      ;   \
-       blr             ;
-
-#define tlbentry(epn,sz,rpn,erpn,attr)\
-       .long TLB0(epn,sz),TLB1(rpn,erpn),TLB2(attr)
-
-
 /**************************************************************************
  * TLB TABLE
  *
@@ -89,13 +43,13 @@
 
 tlbtab:
        tlbtab_start
-       tlbentry( 0xf0000000, SZ_256M, 0xf0000000, 1, AC_R|AC_W|AC_X|SA_G|SA_I)
-       tlbentry( CONFIG_SYS_PERIPHERAL_BASE, SZ_256M, 0x40000000, 1, AC_R|AC_W|SA_G|SA_I)
-       tlbentry( CONFIG_SYS_ISRAM_BASE, SZ_256K, 0x80000000, 0, AC_R|AC_W|AC_X|SA_G|SA_I)
-       tlbentry( CONFIG_SYS_SDRAM_BASE, SZ_256M, 0x00000000, 0, AC_R|AC_W|AC_X|SA_G|SA_I )
-       tlbentry( CONFIG_SYS_SDRAM_BASE+0x10000000, SZ_256M, 0x10000000, 0, AC_R|AC_W|AC_X|SA_G|SA_I )
-       tlbentry( CONFIG_SYS_SDRAM_BASE+0x20000000, SZ_256M, 0x20000000, 0, AC_R|AC_W|AC_X|SA_G|SA_I )
-       tlbentry( CONFIG_SYS_SDRAM_BASE+0x30000000, SZ_256M, 0x30000000, 0, AC_R|AC_W|AC_X|SA_G|SA_I )
-       tlbentry( CONFIG_SYS_PCI_BASE, SZ_256M, 0x00000000, 2, AC_R|AC_W|SA_G|SA_I )
-       tlbentry( CONFIG_SYS_PCI_MEMBASE, SZ_256M, 0x00000000, 3, AC_R|AC_W|SA_G|SA_I )
+       tlbentry( 0xf0000000, SZ_256M, 0xf0000000, 1, AC_RWX | SA_IG)
+       tlbentry( CONFIG_SYS_PERIPHERAL_BASE, SZ_256M, 0x40000000, 1, AC_RW | SA_IG)
+       tlbentry( CONFIG_SYS_ISRAM_BASE, SZ_256K, 0x80000000, 0, AC_RWX | SA_IG)
+       tlbentry( CONFIG_SYS_SDRAM_BASE, SZ_256M, 0x00000000, 0, AC_RWX | SA_IG )
+       tlbentry( CONFIG_SYS_SDRAM_BASE+0x10000000, SZ_256M, 0x10000000, 0, AC_RWX | SA_IG )
+       tlbentry( CONFIG_SYS_SDRAM_BASE+0x20000000, SZ_256M, 0x20000000, 0, AC_RWX | SA_IG )
+       tlbentry( CONFIG_SYS_SDRAM_BASE+0x30000000, SZ_256M, 0x30000000, 0, AC_RWX | SA_IG )
+       tlbentry( CONFIG_SYS_PCI_BASE, SZ_256M, 0x00000000, 2, AC_RW | SA_IG )
+       tlbentry( CONFIG_SYS_PCI_MEMBASE, SZ_256M, 0x00000000, 3, AC_RW | SA_IG )
        tlbtab_end

diff --git a/board/sandburst/metrobox/init.S b/board/sandburst/metrobox/init.S
index ccdec46..fa78a3f 100644 (file)
--- a/board/sandburst/metrobox/init.S
+++ b/board/sandburst/metrobox/init.S
@@ -22,55 +22,9 @@
 */
 
 #include <ppc_asm.tmpl>
+#include <asm/mmu.h>
 #include <config.h>
 
-/* General */
-#define TLB_VALID   0x00000200
-
-/* Supported page sizes */
-
-#define SZ_1K      0x00000000
-#define SZ_4K      0x00000010
-#define SZ_16K     0x00000020
-#define SZ_64K     0x00000030
-#define SZ_256K            0x00000040
-#define SZ_1M      0x00000050
-#define SZ_16M     0x00000070
-#define SZ_256M            0x00000090
-
-/* Storage attributes */
-#define SA_W       0x00000800      /* Write-through */
-#define SA_I       0x00000400      /* Caching inhibited */
-#define SA_M       0x00000200      /* Memory coherence */
-#define SA_G       0x00000100      /* Guarded */
-#define SA_E       0x00000080      /* Endian */
-
-/* Access control */
-#define AC_X       0x00000024      /* Execute */
-#define AC_W       0x00000012      /* Write */
-#define AC_R       0x00000009      /* Read */
-
-/* Some handy macros */
-
-#define EPN(e)         ((e) & 0xfffffc00)
-#define TLB0(epn,sz)   ( (EPN((epn)) | (sz) | TLB_VALID ) )
-#define TLB1(rpn,erpn) ( ((rpn)&0xfffffc00) | (erpn) )
-#define TLB2(a)                ( (a)&0x00000fbf )
-
-#define tlbtab_start\
-       mflr    r1  ;\
-       bl 0f       ;
-
-#define tlbtab_end\
-       .long 0, 0, 0   ;   \
-0:     mflr    r0      ;   \
-       mtlr    r1      ;   \
-       blr             ;
-
-#define tlbentry(epn,sz,rpn,erpn,attr)\
-       .long TLB0(epn,sz),TLB1(rpn,erpn),TLB2(attr)
-
-
 /**************************************************************************
  * TLB TABLE
  *
@@ -87,13 +41,13 @@
 
 tlbtab:
        tlbtab_start
-       tlbentry( 0xf0000000, SZ_256M, 0xf0000000, 1, AC_R|AC_W|AC_X|SA_G|SA_I)
-       tlbentry( CONFIG_SYS_PERIPHERAL_BASE, SZ_256M, 0x40000000, 1, AC_R|AC_W|SA_G|SA_I)
-       tlbentry( CONFIG_SYS_ISRAM_BASE, SZ_256K, 0x80000000, 0, AC_R|AC_W|AC_X|SA_G|SA_I)
-       tlbentry( CONFIG_SYS_SDRAM_BASE, SZ_256M, 0x00000000, 0, AC_R|AC_W|AC_X|SA_G|SA_I )
-       tlbentry( CONFIG_SYS_SDRAM_BASE+0x10000000, SZ_256M, 0x10000000, 0, AC_R|AC_W|AC_X|SA_G|SA_I )
-       tlbentry( CONFIG_SYS_SDRAM_BASE+0x20000000, SZ_256M, 0x20000000, 0, AC_R|AC_W|AC_X|SA_G|SA_I )
-       tlbentry( CONFIG_SYS_SDRAM_BASE+0x30000000, SZ_256M, 0x30000000, 0, AC_R|AC_W|AC_X|SA_G|SA_I )
-       tlbentry( CONFIG_SYS_PCI_BASE, SZ_256M, 0x00000000, 2, AC_R|AC_W|SA_G|SA_I )
-       tlbentry( CONFIG_SYS_PCI_MEMBASE, SZ_256M, 0x00000000, 3, AC_R|AC_W|SA_G|SA_I )
+       tlbentry( 0xf0000000, SZ_256M, 0xf0000000, 1, AC_RWX | SA_IG)
+       tlbentry( CONFIG_SYS_PERIPHERAL_BASE, SZ_256M, 0x40000000, 1, AC_RW | SA_IG)
+       tlbentry( CONFIG_SYS_ISRAM_BASE, SZ_256K, 0x80000000, 0, AC_RWX | SA_IG)
+       tlbentry( CONFIG_SYS_SDRAM_BASE, SZ_256M, 0x00000000, 0, AC_RWX | SA_IG )
+       tlbentry( CONFIG_SYS_SDRAM_BASE+0x10000000, SZ_256M, 0x10000000, 0, AC_RWX | SA_IG )
+       tlbentry( CONFIG_SYS_SDRAM_BASE+0x20000000, SZ_256M, 0x20000000, 0, AC_RWX | SA_IG )
+       tlbentry( CONFIG_SYS_SDRAM_BASE+0x30000000, SZ_256M, 0x30000000, 0, AC_RWX | SA_IG )
+       tlbentry( CONFIG_SYS_PCI_BASE, SZ_256M, 0x00000000, 2, AC_RW | SA_IG )
+       tlbentry( CONFIG_SYS_PCI_MEMBASE, SZ_256M, 0x00000000, 3, AC_RW | SA_IG )
        tlbtab_end

diff --git a/board/xes/xpedite1000/init.S b/board/xes/xpedite1000/init.S
index 54371e2..fa50c8e 100644 (file)
--- a/board/xes/xpedite1000/init.S
+++ b/board/xes/xpedite1000/init.S
@@ -21,53 +21,9 @@
 */
 
 #include <ppc_asm.tmpl>
+#include <asm/mmu.h>
 #include <config.h>
 
-/* General */
-#define TLB_VALID      0x00000200
-
-/* Supported page sizes */
-#define SZ_1K          0x00000000
-#define SZ_4K          0x00000010
-#define SZ_16K         0x00000020
-#define SZ_64K         0x00000030
-#define SZ_256K                0x00000040
-#define SZ_1M          0x00000050
-#define SZ_16M         0x00000070
-#define SZ_256M                0x00000090
-
-/* Storage attributes */
-#define SA_W           0x00000800      /* Write-through */
-#define SA_I           0x00000400      /* Caching inhibited */
-#define SA_M           0x00000200      /* Memory coherence */
-#define SA_G           0x00000100      /* Guarded */
-#define SA_E           0x00000080      /* Endian */
-
-/* Access control */
-#define AC_X           0x00000024      /* Execute */
-#define AC_W           0x00000012      /* Write */
-#define AC_R           0x00000009      /* Read */
-
-/* Some handy macros */
-#define EPN(e)         ((e) & 0xfffffc00)
-#define TLB0(epn,sz)   ((EPN((epn)) | (sz) | TLB_VALID ))
-#define TLB1(rpn,erpn) (((rpn)&0xfffffc00) | (erpn))
-#define TLB2(a)                ((a)&0x00000fbf)
-
-#define tlbtab_start   \
-       mflr    r1;     \
-       bl 0f;
-
-#define tlbtab_end     \
-       .long 0, 0, 0;  \
-0:     mflr    r0;     \
-       mtlr    r1;     \
-       blr;
-
-#define tlbentry(epn,sz,rpn,erpn,attr)\
-       .long TLB0(epn,sz),TLB1(rpn,erpn),TLB2(attr)
-
-
 /*
  * TLB TABLE
  *
@@ -83,11 +39,11 @@
 
 tlbtab:
        tlbtab_start
-       tlbentry( 0xf0000000, SZ_256M, 0xf0000000, 1, AC_R|AC_W|AC_X|SA_G|SA_I)
-       tlbentry( CONFIG_SYS_PERIPHERAL_BASE, SZ_256M, 0x40000000, 1, AC_R|AC_W|SA_G|SA_I)
-       tlbentry( CONFIG_SYS_ISRAM_BASE, SZ_256K, 0x80000000, 0, AC_R|AC_W|AC_X|SA_G|SA_I)
-       tlbentry( CONFIG_SYS_SDRAM_BASE, SZ_256M, 0x00000000, 0, AC_R|AC_W|AC_X|SA_G|SA_I )
-       tlbentry( CONFIG_SYS_SDRAM_BASE+0x10000000, SZ_256M, 0x10000000, 0, AC_R|AC_W|AC_X|SA_G|SA_I )
-       tlbentry( CONFIG_SYS_PCI_BASE, SZ_256M, 0x00000000, 2, AC_R|AC_W|SA_G|SA_I )
-       tlbentry( CONFIG_SYS_PCI_MEMBASE, SZ_256M, 0x00000000, 3, AC_R|AC_W|SA_G|SA_I )
+       tlbentry( 0xf0000000, SZ_256M, 0xf0000000, 1, AC_RWX | SA_IG)
+       tlbentry( CONFIG_SYS_PERIPHERAL_BASE, SZ_256M, 0x40000000, 1, AC_RW | SA_IG)
+       tlbentry( CONFIG_SYS_ISRAM_BASE, SZ_256K, 0x80000000, 0, AC_RWX | SA_IG)
+       tlbentry( CONFIG_SYS_SDRAM_BASE, SZ_256M, 0x00000000, 0, AC_RWX | SA_IG )
+       tlbentry( CONFIG_SYS_SDRAM_BASE+0x10000000, SZ_256M, 0x10000000, 0, AC_RWX | SA_IG )
+       tlbentry( CONFIG_SYS_PCI_BASE, SZ_256M, 0x00000000, 2, AC_RW | SA_IG )
+       tlbentry( CONFIG_SYS_PCI_MEMBASE, SZ_256M, 0x00000000, 3, AC_RW | SA_IG )
        tlbtab_end