freedreno/a6xx: Emit const and texture state for HS/DS/GS

Signed-off-by: Kristian H. Kristensen <hoegsberg@google.com>

diff --git a/src/gallium/drivers/freedreno/a6xx/fd6_draw.c b/src/gallium/drivers/freedreno/a6xx/fd6_draw.c
index 8cabce9..1d5df60 100644 (file)
--- a/src/gallium/drivers/freedreno/a6xx/fd6_draw.c
+++ b/src/gallium/drivers/freedreno/a6xx/fd6_draw.c
@@ -129,6 +129,9 @@ fd6_draw_vbo(struct fd_context *ctx, const struct pipe_draw_info *info,
                .info = info,
                .key = {
                        .vs = ctx->prog.vs,
+                       .hs = ctx->prog.hs,
+                       .ds = ctx->prog.ds,
+                       .gs = ctx->prog.gs,
                        .fs = ctx->prog.fs,
                        .key = {
                                .color_two_side = ctx->rasterizer->light_twoside,
@@ -169,18 +172,21 @@ fd6_draw_vbo(struct fd_context *ctx, const struct pipe_draw_info *info,
        emit.dirty = ctx->dirty;      /* *after* fixup_shader_state() */
        emit.bs = fd6_emit_get_prog(&emit)->bs;
        emit.vs = fd6_emit_get_prog(&emit)->vs;
+       emit.hs = fd6_emit_get_prog(&emit)->hs;
+       emit.ds = fd6_emit_get_prog(&emit)->ds;
+       emit.gs = fd6_emit_get_prog(&emit)->gs;
        emit.fs = fd6_emit_get_prog(&emit)->fs;
 
-       const struct ir3_shader_variant *vp = emit.vs;
-       const struct ir3_shader_variant *fp = emit.fs;
-
-       ctx->stats.vs_regs += ir3_shader_halfregs(vp);
-       ctx->stats.fs_regs += ir3_shader_halfregs(fp);
+       ctx->stats.vs_regs += ir3_shader_halfregs(emit.vs);
+       ctx->stats.hs_regs += COND(emit.hs, ir3_shader_halfregs(emit.hs));
+       ctx->stats.ds_regs += COND(emit.ds, ir3_shader_halfregs(emit.ds));
+       ctx->stats.gs_regs += COND(emit.gs, ir3_shader_halfregs(emit.gs));
+       ctx->stats.fs_regs += ir3_shader_halfregs(emit.fs);
 
        /* figure out whether we need to disable LRZ write for binning
-        * pass using draw pass's fp:
+        * pass using draw pass's fs:
         */
-       emit.no_lrz_write = fp->writes_pos || fp->no_earlyz;
+       emit.no_lrz_write = emit.fs->writes_pos || emit.fs->no_earlyz;
 
        struct fd_ringbuffer *ring = ctx->batch->draw;
        enum pc_di_primtype primtype = ctx->primtypes[info->mode];

diff --git a/src/gallium/drivers/freedreno/a6xx/fd6_emit.c b/src/gallium/drivers/freedreno/a6xx/fd6_emit.c
index 0db32ff..a0d2259 100644 (file)
--- a/src/gallium/drivers/freedreno/a6xx/fd6_emit.c
+++ b/src/gallium/drivers/freedreno/a6xx/fd6_emit.c
@@ -380,6 +380,27 @@ fd6_emit_textures(struct fd_pipe *pipe, struct fd_ringbuffer *ring,
                tex_const_reg = REG_A6XX_SP_VS_TEX_CONST_LO;
                tex_count_reg = REG_A6XX_SP_VS_TEX_COUNT;
                break;
+       case PIPE_SHADER_TESS_CTRL:
+               sb = SB6_HS_TEX;
+               opcode = CP_LOAD_STATE6_GEOM;
+               tex_samp_reg = REG_A6XX_SP_HS_TEX_SAMP_LO;
+               tex_const_reg = REG_A6XX_SP_HS_TEX_CONST_LO;
+               tex_count_reg = REG_A6XX_SP_HS_TEX_COUNT;
+               break;
+       case PIPE_SHADER_TESS_EVAL:
+               sb = SB6_DS_TEX;
+               opcode = CP_LOAD_STATE6_GEOM;
+               tex_samp_reg = REG_A6XX_SP_DS_TEX_SAMP_LO;
+               tex_const_reg = REG_A6XX_SP_DS_TEX_CONST_LO;
+               tex_count_reg = REG_A6XX_SP_DS_TEX_COUNT;
+               break;
+       case PIPE_SHADER_GEOMETRY:
+               sb = SB6_GS_TEX;
+               opcode = CP_LOAD_STATE6_GEOM;
+               tex_samp_reg = REG_A6XX_SP_GS_TEX_SAMP_LO;
+               tex_const_reg = REG_A6XX_SP_GS_TEX_CONST_LO;
+               tex_count_reg = REG_A6XX_SP_GS_TEX_COUNT;
+               break;
        case PIPE_SHADER_FRAGMENT:
                sb = SB6_FS_TEX;
                opcode = CP_LOAD_STATE6_FRAG;
@@ -554,6 +575,9 @@ fd6_emit_combined_textures(struct fd_ringbuffer *ring, struct fd6_emit *emit,
                unsigned enable_mask;
        } s[PIPE_SHADER_TYPES] = {
                [PIPE_SHADER_VERTEX]    = { FD6_GROUP_VS_TEX, 0x7 },
+               [PIPE_SHADER_TESS_CTRL]  = { FD6_GROUP_HS_TEX, 0x7 },
+               [PIPE_SHADER_TESS_EVAL]  = { FD6_GROUP_DS_TEX, 0x7 },
+               [PIPE_SHADER_GEOMETRY]  = { FD6_GROUP_GS_TEX, 0x7 },
                [PIPE_SHADER_FRAGMENT]  = { FD6_GROUP_FS_TEX, 0x6 },
        };
 
@@ -791,6 +815,9 @@ fd6_emit_state(struct fd_ringbuffer *ring, struct fd6_emit *emit)
        struct pipe_framebuffer_state *pfb = &ctx->batch->framebuffer;
        const struct fd6_program_state *prog = fd6_emit_get_prog(emit);
        const struct ir3_shader_variant *vs = emit->vs;
+       const struct ir3_shader_variant *hs = emit->hs;
+       const struct ir3_shader_variant *ds = emit->ds;
+       const struct ir3_shader_variant *gs = emit->gs;
        const struct ir3_shader_variant *fs = emit->fs;
        const enum fd_dirty_3d_state dirty = emit->dirty;
        bool needs_border = false;
@@ -936,6 +963,9 @@ fd6_emit_state(struct fd_ringbuffer *ring, struct fd6_emit *emit)
        }
 
        fd6_emit_consts(emit, vs, PIPE_SHADER_VERTEX, FD6_GROUP_VS_CONST, 0x7);
+       fd6_emit_consts(emit, hs, PIPE_SHADER_TESS_CTRL, FD6_GROUP_HS_CONST, 0x7);
+       fd6_emit_consts(emit, ds, PIPE_SHADER_TESS_EVAL, FD6_GROUP_DS_CONST, 0x7);
+       fd6_emit_consts(emit, gs, PIPE_SHADER_GEOMETRY, FD6_GROUP_GS_CONST, 0x7);
        fd6_emit_consts(emit, fs, PIPE_SHADER_FRAGMENT, FD6_GROUP_FS_CONST, 0x6);
 
        /* if driver-params are needed, emit each time: */
@@ -1008,11 +1038,26 @@ fd6_emit_state(struct fd_ringbuffer *ring, struct fd6_emit *emit)
        }
 
        needs_border |= fd6_emit_combined_textures(ring, emit, PIPE_SHADER_VERTEX, vs);
+       if (hs) {
+               needs_border |= fd6_emit_combined_textures(ring, emit, PIPE_SHADER_TESS_CTRL, hs);
+               needs_border |= fd6_emit_combined_textures(ring, emit, PIPE_SHADER_TESS_EVAL, ds);
+       }
+       if (gs) {
+               needs_border |= fd6_emit_combined_textures(ring, emit, PIPE_SHADER_GEOMETRY, gs);
+       }
        needs_border |= fd6_emit_combined_textures(ring, emit, PIPE_SHADER_FRAGMENT, fs);
 
        if (needs_border)
                emit_border_color(ctx, ring);
 
+       if (hs) {
+               debug_assert(hs->image_mapping.num_ibo == 0);
+               debug_assert(ds->image_mapping.num_ibo == 0);
+       }
+       if (gs) {
+               debug_assert(gs->image_mapping.num_ibo == 0);
+       }
+
 #define DIRTY_IBO (FD_DIRTY_SHADER_SSBO | FD_DIRTY_SHADER_IMAGE | \
                                   FD_DIRTY_SHADER_PROG)
        if (ctx->dirty_shader[PIPE_SHADER_FRAGMENT] & DIRTY_IBO) {

diff --git a/src/gallium/drivers/freedreno/a6xx/fd6_emit.h b/src/gallium/drivers/freedreno/a6xx/fd6_emit.h
index 490cffb..107723f 100644 (file)
--- a/src/gallium/drivers/freedreno/a6xx/fd6_emit.h
+++ b/src/gallium/drivers/freedreno/a6xx/fd6_emit.h
@@ -50,9 +50,15 @@ enum fd6_state_id {
        FD6_GROUP_LRZ_BINNING,
        FD6_GROUP_VBO,
        FD6_GROUP_VS_CONST,
+       FD6_GROUP_HS_CONST,
+       FD6_GROUP_DS_CONST,
+       FD6_GROUP_GS_CONST,
        FD6_GROUP_FS_CONST,
        FD6_GROUP_VS_DRIVER_PARAMS,
        FD6_GROUP_VS_TEX,
+       FD6_GROUP_HS_TEX,
+       FD6_GROUP_DS_TEX,
+       FD6_GROUP_GS_TEX,
        FD6_GROUP_FS_TEX,
        FD6_GROUP_IBO,
        FD6_GROUP_RASTERIZER,
@@ -92,6 +98,9 @@ struct fd6_emit {
 
        struct ir3_shader_variant *bs;
        struct ir3_shader_variant *vs;
+       struct ir3_shader_variant *hs;
+       struct ir3_shader_variant *ds;
+       struct ir3_shader_variant *gs;
        struct ir3_shader_variant *fs;
 
        unsigned streamout_mask;
@@ -218,6 +227,12 @@ fd6_stage2shadersb(gl_shader_stage type)
        switch (type) {
        case MESA_SHADER_VERTEX:
                return SB6_VS_SHADER;
+       case MESA_SHADER_TESS_CTRL:
+               return SB6_HS_SHADER;
+       case MESA_SHADER_TESS_EVAL:
+               return SB6_DS_SHADER;
+       case MESA_SHADER_GEOMETRY:
+               return SB6_GS_SHADER;
        case MESA_SHADER_FRAGMENT:
                return SB6_FS_SHADER;
        case MESA_SHADER_COMPUTE:

diff --git a/src/gallium/drivers/freedreno/freedreno_context.h b/src/gallium/drivers/freedreno/freedreno_context.h
index f17797a..12aaba1 100644 (file)
--- a/src/gallium/drivers/freedreno/freedreno_context.h
+++ b/src/gallium/drivers/freedreno/freedreno_context.h
@@ -215,7 +215,7 @@ struct fd_context {
                uint64_t draw_calls;
                uint64_t batch_total, batch_sysmem, batch_gmem, batch_nondraw, batch_restore;
                uint64_t staging_uploads, shadow_uploads;
-               uint64_t vs_regs, fs_regs;
+               uint64_t vs_regs, hs_regs, ds_regs, gs_regs, fs_regs;
        } stats;
 
        /* Current batch.. the rule here is that you can deref ctx->batch