pinctrl: renesas: r8a779g0: Add missing HSCIF1_X

This patch adds missing HSCIF1.
Because Document (Rev.0.51) has 2x HSCIF1 with no suffix (_A, _B),
this patch names it as _X.

Signed-off-by: Kuninori Morimoto <kuninori.morimoto.gx@renesas.com>
Link: https://lore.kernel.org/r/87wncxsjah.wl-kuninori.morimoto.gx@renesas.com
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>

diff --git a/drivers/pinctrl/renesas/pfc-r8a779g0.c b/drivers/pinctrl/renesas/pfc-r8a779g0.c
index b7ebf6f..e733897 100644 (file)
--- a/drivers/pinctrl/renesas/pfc-r8a779g0.c
+++ b/drivers/pinctrl/renesas/pfc-r8a779g0.c
@@ -301,13 +301,13 @@
 #define IP0SR1_15_12   FM(MSIOF1_SCK)          FM(HSCK3_A)             F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 #define IP0SR1_19_16   FM(MSIOF1_TXD)          FM(HRX3_A)              F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 #define IP0SR1_23_20   FM(MSIOF1_RXD)          F_(0, 0)                F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
-#define IP0SR1_27_24   FM(MSIOF0_SS2)          F_(0, 0)                F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
-#define IP0SR1_31_28   FM(MSIOF0_SS1)          F_(0, 0)                F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
+#define IP0SR1_27_24   FM(MSIOF0_SS2)          FM(HTX1_X)              F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
+#define IP0SR1_31_28   FM(MSIOF0_SS1)          FM(HRX1_X)              F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 
 /* IP1SR1 */           /* 0 */                 /* 1 */                 /* 2 */         /* 3            4        5        6        7        8        9        A        B        C        D        E        F */
-#define IP1SR1_3_0     FM(MSIOF0_SYNC)         F_(0, 0)                F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
-#define IP1SR1_7_4     FM(MSIOF0_TXD)          F_(0, 0)                F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
-#define IP1SR1_11_8    FM(MSIOF0_SCK)          F_(0, 0)                F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
+#define IP1SR1_3_0     FM(MSIOF0_SYNC)         FM(HCTS1_N_X)           F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
+#define IP1SR1_7_4     FM(MSIOF0_TXD)          FM(HRTS1_N_X)           F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
+#define IP1SR1_11_8    FM(MSIOF0_SCK)          FM(HSCK1_X)             F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 #define IP1SR1_15_12   FM(MSIOF0_RXD)          F_(0, 0)                F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 #define IP1SR1_19_16   FM(HTX0)                FM(TX0)                 F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 #define IP1SR1_23_20   FM(HCTS0_N)             FM(CTS0_N)              FM(PWM8)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
@@ -809,15 +809,22 @@ static const u16 pinmux_data[] = {
        PINMUX_IPSR_GPSR(IP0SR1_19_16,  HRX3_A),
 
        PINMUX_IPSR_GPSR(IP0SR1_23_20,  MSIOF1_RXD),
+
        PINMUX_IPSR_GPSR(IP0SR1_27_24,  MSIOF0_SS2),
+       PINMUX_IPSR_GPSR(IP0SR1_27_24,  HTX1_X),
+
        PINMUX_IPSR_GPSR(IP0SR1_31_28,  MSIOF0_SS1),
+       PINMUX_IPSR_GPSR(IP0SR1_31_28,  HRX1_X),
 
        /* IP1SR1 */
        PINMUX_IPSR_GPSR(IP1SR1_3_0,    MSIOF0_SYNC),
+       PINMUX_IPSR_GPSR(IP1SR1_3_0,    HCTS1_N_X),
 
        PINMUX_IPSR_GPSR(IP1SR1_7_4,    MSIOF0_TXD),
+       PINMUX_IPSR_GPSR(IP1SR1_7_4,    HRTS1_N_X),
 
        PINMUX_IPSR_GPSR(IP1SR1_11_8,   MSIOF0_SCK),
+       PINMUX_IPSR_GPSR(IP1SR1_11_8,   HSCK1_X),
 
        PINMUX_IPSR_GPSR(IP1SR1_15_12,  MSIOF0_RXD),
 
@@ -1524,6 +1531,29 @@ static const unsigned int hscif1_ctrl_mux[] = {
        HRTS1_N_MARK, HCTS1_N_MARK,
 };
 
+/* - HSCIF1_X---------------------------------------------------------------- */
+static const unsigned int hscif1_data_x_pins[] = {
+       /* HRX1_X, HTX1_X */
+       RCAR_GP_PIN(1, 7), RCAR_GP_PIN(1, 6),
+};
+static const unsigned int hscif1_data_x_mux[] = {
+       HRX1_X_MARK, HTX1_X_MARK,
+};
+static const unsigned int hscif1_clk_x_pins[] = {
+       /* HSCK1_X */
+       RCAR_GP_PIN(1, 10),
+};
+static const unsigned int hscif1_clk_x_mux[] = {
+       HSCK1_X_MARK,
+};
+static const unsigned int hscif1_ctrl_x_pins[] = {
+       /* HRTS1_N_X, HCTS1_N_X */
+       RCAR_GP_PIN(1, 9), RCAR_GP_PIN(1, 8),
+};
+static const unsigned int hscif1_ctrl_x_mux[] = {
+       HRTS1_N_X_MARK, HCTS1_N_X_MARK,
+};
+
 /* - HSCIF2 ----------------------------------------------------------------- */
 static const unsigned int hscif2_data_pins[] = {
        /* HRX2, HTX2 */
@@ -2345,9 +2375,12 @@ static const struct sh_pfc_pin_group pinmux_groups[] = {
        SH_PFC_PIN_GROUP(hscif0_data),
        SH_PFC_PIN_GROUP(hscif0_clk),
        SH_PFC_PIN_GROUP(hscif0_ctrl),
-       SH_PFC_PIN_GROUP(hscif1_data),
-       SH_PFC_PIN_GROUP(hscif1_clk),
-       SH_PFC_PIN_GROUP(hscif1_ctrl),
+       SH_PFC_PIN_GROUP(hscif1_data),          /* suffix might be updated */
+       SH_PFC_PIN_GROUP(hscif1_clk),           /* suffix might be updated */
+       SH_PFC_PIN_GROUP(hscif1_ctrl),          /* suffix might be updated */
+       SH_PFC_PIN_GROUP(hscif1_data_x),        /* suffix might be updated */
+       SH_PFC_PIN_GROUP(hscif1_clk_x),         /* suffix might be updated */
+       SH_PFC_PIN_GROUP(hscif1_ctrl_x),        /* suffix might be updated */
        SH_PFC_PIN_GROUP(hscif2_data),
        SH_PFC_PIN_GROUP(hscif2_clk),
        SH_PFC_PIN_GROUP(hscif2_ctrl),
@@ -2544,9 +2577,13 @@ static const char * const hscif0_groups[] = {
 };
 
 static const char * const hscif1_groups[] = {
+       /* suffix might be updated */
        "hscif1_data",
        "hscif1_clk",
        "hscif1_ctrl",
+       "hscif1_data_x",
+       "hscif1_clk_x",
+       "hscif1_ctrl_x",
 };
 
 static const char * const hscif2_groups[] = {