.clkr.hw.init = &(struct clk_init_data){
.name = "cam_cc_bps_clk_src",
.parent_names = cam_cc_parent_names_0,
- .num_parents = 6,
+ .num_parents = ARRAY_SIZE(cam_cc_parent_names_0),
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_rcg2_shared_ops,
},
.clkr.hw.init = &(struct clk_init_data){
.name = "cam_cc_cci_clk_src",
.parent_names = cam_cc_parent_names_0,
- .num_parents = 6,
+ .num_parents = ARRAY_SIZE(cam_cc_parent_names_0),
.ops = &clk_rcg2_ops,
},
};
.clkr.hw.init = &(struct clk_init_data){
.name = "cam_cc_cphy_rx_clk_src",
.parent_names = cam_cc_parent_names_0,
- .num_parents = 6,
+ .num_parents = ARRAY_SIZE(cam_cc_parent_names_0),
.ops = &clk_rcg2_ops,
},
};
.clkr.hw.init = &(struct clk_init_data){
.name = "cam_cc_csi0phytimer_clk_src",
.parent_names = cam_cc_parent_names_0,
- .num_parents = 6,
+ .num_parents = ARRAY_SIZE(cam_cc_parent_names_0),
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_rcg2_ops,
},
.clkr.hw.init = &(struct clk_init_data){
.name = "cam_cc_csi1phytimer_clk_src",
.parent_names = cam_cc_parent_names_0,
- .num_parents = 6,
+ .num_parents = ARRAY_SIZE(cam_cc_parent_names_0),
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_rcg2_ops,
},
.clkr.hw.init = &(struct clk_init_data){
.name = "cam_cc_csi2phytimer_clk_src",
.parent_names = cam_cc_parent_names_0,
- .num_parents = 6,
+ .num_parents = ARRAY_SIZE(cam_cc_parent_names_0),
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_rcg2_ops,
},
.clkr.hw.init = &(struct clk_init_data){
.name = "cam_cc_csi3phytimer_clk_src",
.parent_names = cam_cc_parent_names_0,
- .num_parents = 6,
+ .num_parents = ARRAY_SIZE(cam_cc_parent_names_0),
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_rcg2_ops,
},
.clkr.hw.init = &(struct clk_init_data){
.name = "cam_cc_fast_ahb_clk_src",
.parent_names = cam_cc_parent_names_0,
- .num_parents = 6,
+ .num_parents = ARRAY_SIZE(cam_cc_parent_names_0),
.ops = &clk_rcg2_ops,
},
};
.clkr.hw.init = &(struct clk_init_data){
.name = "cam_cc_fd_core_clk_src",
.parent_names = cam_cc_parent_names_0,
- .num_parents = 6,
+ .num_parents = ARRAY_SIZE(cam_cc_parent_names_0),
.ops = &clk_rcg2_shared_ops,
},
};
.clkr.hw.init = &(struct clk_init_data){
.name = "cam_cc_icp_clk_src",
.parent_names = cam_cc_parent_names_0,
- .num_parents = 6,
+ .num_parents = ARRAY_SIZE(cam_cc_parent_names_0),
.ops = &clk_rcg2_shared_ops,
},
};
.clkr.hw.init = &(struct clk_init_data){
.name = "cam_cc_ife_0_clk_src",
.parent_names = cam_cc_parent_names_0,
- .num_parents = 6,
+ .num_parents = ARRAY_SIZE(cam_cc_parent_names_0),
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_rcg2_shared_ops,
},
.clkr.hw.init = &(struct clk_init_data){
.name = "cam_cc_ife_0_csid_clk_src",
.parent_names = cam_cc_parent_names_0,
- .num_parents = 6,
+ .num_parents = ARRAY_SIZE(cam_cc_parent_names_0),
.ops = &clk_rcg2_shared_ops,
},
};
.clkr.hw.init = &(struct clk_init_data){
.name = "cam_cc_ife_1_clk_src",
.parent_names = cam_cc_parent_names_0,
- .num_parents = 6,
+ .num_parents = ARRAY_SIZE(cam_cc_parent_names_0),
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_rcg2_shared_ops,
},
.clkr.hw.init = &(struct clk_init_data){
.name = "cam_cc_ife_1_csid_clk_src",
.parent_names = cam_cc_parent_names_0,
- .num_parents = 6,
+ .num_parents = ARRAY_SIZE(cam_cc_parent_names_0),
.ops = &clk_rcg2_shared_ops,
},
};
.clkr.hw.init = &(struct clk_init_data){
.name = "cam_cc_ife_lite_clk_src",
.parent_names = cam_cc_parent_names_0,
- .num_parents = 6,
+ .num_parents = ARRAY_SIZE(cam_cc_parent_names_0),
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_rcg2_shared_ops,
},
.clkr.hw.init = &(struct clk_init_data){
.name = "cam_cc_ife_lite_csid_clk_src",
.parent_names = cam_cc_parent_names_0,
- .num_parents = 6,
+ .num_parents = ARRAY_SIZE(cam_cc_parent_names_0),
.ops = &clk_rcg2_shared_ops,
},
};
.clkr.hw.init = &(struct clk_init_data){
.name = "cam_cc_ipe_0_clk_src",
.parent_names = cam_cc_parent_names_0,
- .num_parents = 6,
+ .num_parents = ARRAY_SIZE(cam_cc_parent_names_0),
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_rcg2_shared_ops,
},
.clkr.hw.init = &(struct clk_init_data){
.name = "cam_cc_ipe_1_clk_src",
.parent_names = cam_cc_parent_names_0,
- .num_parents = 6,
+ .num_parents = ARRAY_SIZE(cam_cc_parent_names_0),
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_rcg2_shared_ops,
},
.clkr.hw.init = &(struct clk_init_data){
.name = "cam_cc_jpeg_clk_src",
.parent_names = cam_cc_parent_names_0,
- .num_parents = 6,
+ .num_parents = ARRAY_SIZE(cam_cc_parent_names_0),
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_rcg2_shared_ops,
},
.clkr.hw.init = &(struct clk_init_data){
.name = "cam_cc_lrme_clk_src",
.parent_names = cam_cc_parent_names_0,
- .num_parents = 6,
+ .num_parents = ARRAY_SIZE(cam_cc_parent_names_0),
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_rcg2_shared_ops,
},
.clkr.hw.init = &(struct clk_init_data){
.name = "cam_cc_mclk0_clk_src",
.parent_names = cam_cc_parent_names_0,
- .num_parents = 6,
+ .num_parents = ARRAY_SIZE(cam_cc_parent_names_0),
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_rcg2_ops,
},
.clkr.hw.init = &(struct clk_init_data){
.name = "cam_cc_mclk1_clk_src",
.parent_names = cam_cc_parent_names_0,
- .num_parents = 6,
+ .num_parents = ARRAY_SIZE(cam_cc_parent_names_0),
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_rcg2_ops,
},
.clkr.hw.init = &(struct clk_init_data){
.name = "cam_cc_mclk2_clk_src",
.parent_names = cam_cc_parent_names_0,
- .num_parents = 6,
+ .num_parents = ARRAY_SIZE(cam_cc_parent_names_0),
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_rcg2_ops,
},
.clkr.hw.init = &(struct clk_init_data){
.name = "cam_cc_mclk3_clk_src",
.parent_names = cam_cc_parent_names_0,
- .num_parents = 6,
+ .num_parents = ARRAY_SIZE(cam_cc_parent_names_0),
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_rcg2_ops,
},
.clkr.hw.init = &(struct clk_init_data){
.name = "cam_cc_slow_ahb_clk_src",
.parent_names = cam_cc_parent_names_0,
- .num_parents = 6,
+ .num_parents = ARRAY_SIZE(cam_cc_parent_names_0),
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_rcg2_ops,
},