#define CONTEXT_EXCEPTION_REQUEST 0x40000000
#define CONTEXT_EXCEPTION_REPORTING 0x80000000
-typedef struct DECLSPEC_ALIGN(16) _M128A {
+typedef struct _M128U {
ULONGLONG Low;
LONGLONG High;
-} M128A, *PM128A;
+} M128U, *PM128U;
+
+// Same as _M128U but aligned to a 16-byte boundary
+typedef DECLSPEC_ALIGN(16) M128U M128A, *PM128A;
typedef struct _XMM_SAVE_AREA32 {
WORD ControlWord;
for (int i = 0; i < 8; i++)
{
- FPREG_St(native, i) = lpContext->FltSave.FloatRegisters[i];
+ FPREG_St(native, i) = ((M128U*)lpContext->FltSave.FloatRegisters)[i];
}
for (int i = 0; i < 16; i++)
{
- FPREG_Xmm(native, i) = lpContext->FltSave.XmmRegisters[i];
- }
+ FPREG_Xmm(native, i) = ((M128U*)lpContext->FltSave.XmmRegisters)[i];
+ }
}
}
for (int i = 0; i < 8; i++)
{
- lpContext->FltSave.FloatRegisters[i] = FPREG_St(native, i);
+ ((M128U*)lpContext->FltSave.FloatRegisters)[i] = FPREG_St(native, i);
}
for (int i = 0; i < 16; i++)
{
- lpContext->FltSave.XmmRegisters[i] = FPREG_Xmm(native, i);
- }
+ ((M128U*)lpContext->FltSave.XmmRegisters)[i] = FPREG_Xmm(native, i);
+ }
}
}
#define MCREG_R14(mc) ((mc).gregs[REG_R14])
#define MCREG_R15(mc) ((mc).gregs[REG_R15])
-#define FPREG_Xmm(uc, index) *(M128A*)&((uc)->__fpregs_mem._xmm[index])
+#define FPREG_Xmm(uc, index) *(M128U*)&((uc)->__fpregs_mem._xmm[index])
-#define FPREG_St(uc, index) *(M128A*)&((uc)->__fpregs_mem._st[index])
+#define FPREG_St(uc, index) *(M128U*)&((uc)->__fpregs_mem._st[index])
#define FPREG_ControlWord(uc) ((uc)->__fpregs_mem.cwd)
#define FPREG_StatusWord(uc) ((uc)->__fpregs_mem.swd)