drm/amd: Update GFXv9 SDMA MQD structure

This matches what the HWS firmware expects on GFXv9 chips.

Signed-off-by: Felix Kuehling <Felix.Kuehling@amd.com>
Reviewed-by: Oded Gabbay <oded.gabbay@gmail.com>
Signed-off-by: Oded Gabbay <oded.gabbay@gmail.com>

diff --git a/MAINTAINERS b/MAINTAINERS
index 92be777..dc929dc 100644 (file)
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -772,6 +772,7 @@ F:  drivers/gpu/drm/amd/amdkfd/
 F:     drivers/gpu/drm/amd/include/cik_structs.h
 F:     drivers/gpu/drm/amd/include/kgd_kfd_interface.h
 F:     drivers/gpu/drm/amd/include/vi_structs.h
+F:     drivers/gpu/drm/amd/include/v9_structs.h
 F:     include/uapi/linux/kfd_ioctl.h
 
 AMD SEATTLE DEVICE TREE SUPPORT

diff --git a/drivers/gpu/drm/amd/include/v9_structs.h b/drivers/gpu/drm/amd/include/v9_structs.h
index 2fb25ab..ceaf493 100644 (file)
--- a/drivers/gpu/drm/amd/include/v9_structs.h
+++ b/drivers/gpu/drm/amd/include/v9_structs.h
@@ -29,10 +29,10 @@ struct v9_sdma_mqd {
        uint32_t sdmax_rlcx_rb_base;
        uint32_t sdmax_rlcx_rb_base_hi;
        uint32_t sdmax_rlcx_rb_rptr;
+       uint32_t sdmax_rlcx_rb_rptr_hi;
        uint32_t sdmax_rlcx_rb_wptr;
+       uint32_t sdmax_rlcx_rb_wptr_hi;
        uint32_t sdmax_rlcx_rb_wptr_poll_cntl;
-       uint32_t sdmax_rlcx_rb_wptr_poll_addr_hi;
-       uint32_t sdmax_rlcx_rb_wptr_poll_addr_lo;
        uint32_t sdmax_rlcx_rb_rptr_addr_hi;
        uint32_t sdmax_rlcx_rb_rptr_addr_lo;
        uint32_t sdmax_rlcx_ib_cntl;
@@ -44,29 +44,29 @@ struct v9_sdma_mqd {
        uint32_t sdmax_rlcx_skip_cntl;
        uint32_t sdmax_rlcx_context_status;
        uint32_t sdmax_rlcx_doorbell;
-       uint32_t sdmax_rlcx_virtual_addr;
-       uint32_t sdmax_rlcx_ape1_cntl;
+       uint32_t sdmax_rlcx_status;
        uint32_t sdmax_rlcx_doorbell_log;
-       uint32_t reserved_22;
-       uint32_t reserved_23;
-       uint32_t reserved_24;
-       uint32_t reserved_25;
-       uint32_t reserved_26;
-       uint32_t reserved_27;
-       uint32_t reserved_28;
-       uint32_t reserved_29;
-       uint32_t reserved_30;
-       uint32_t reserved_31;
-       uint32_t reserved_32;
-       uint32_t reserved_33;
-       uint32_t reserved_34;
-       uint32_t reserved_35;
-       uint32_t reserved_36;
-       uint32_t reserved_37;
-       uint32_t reserved_38;
-       uint32_t reserved_39;
-       uint32_t reserved_40;
-       uint32_t reserved_41;
+       uint32_t sdmax_rlcx_watermark;
+       uint32_t sdmax_rlcx_doorbell_offset;
+       uint32_t sdmax_rlcx_csa_addr_lo;
+       uint32_t sdmax_rlcx_csa_addr_hi;
+       uint32_t sdmax_rlcx_ib_sub_remain;
+       uint32_t sdmax_rlcx_preempt;
+       uint32_t sdmax_rlcx_dummy_reg;
+       uint32_t sdmax_rlcx_rb_wptr_poll_addr_hi;
+       uint32_t sdmax_rlcx_rb_wptr_poll_addr_lo;
+       uint32_t sdmax_rlcx_rb_aql_cntl;
+       uint32_t sdmax_rlcx_minor_ptr_update;
+       uint32_t sdmax_rlcx_midcmd_data0;
+       uint32_t sdmax_rlcx_midcmd_data1;
+       uint32_t sdmax_rlcx_midcmd_data2;
+       uint32_t sdmax_rlcx_midcmd_data3;
+       uint32_t sdmax_rlcx_midcmd_data4;
+       uint32_t sdmax_rlcx_midcmd_data5;
+       uint32_t sdmax_rlcx_midcmd_data6;
+       uint32_t sdmax_rlcx_midcmd_data7;
+       uint32_t sdmax_rlcx_midcmd_data8;
+       uint32_t sdmax_rlcx_midcmd_cntl;
        uint32_t reserved_42;
        uint32_t reserved_43;
        uint32_t reserved_44;