ARM: at91: pm: avoid soft resetting AC DLL

Do not soft reset AC DLL as controller is buggy and this operation my
introduce glitches in the controller leading to undefined behavior.

Fixes: f0bbf17958e8 ("ARM: at91: pm: add self-refresh support for sama7g5")
Depends-on: a02875c4cbd6 ("ARM: at91: pm: fix self-refresh for sama7g5")
Signed-off-by: Claudiu Beznea <claudiu.beznea@microchip.com>
Link: https://lore.kernel.org/r/20221026124114.985876-2-claudiu.beznea@microchip.com

diff --git a/arch/arm/mach-at91/pm_suspend.S b/arch/arm/mach-at91/pm_suspend.S
index ffed4d9..e4904fa 100644 (file)
--- a/arch/arm/mach-at91/pm_suspend.S
+++ b/arch/arm/mach-at91/pm_suspend.S
@@ -169,10 +169,15 @@ sr_ena_2:
        cmp     tmp1, #UDDRC_STAT_SELFREF_TYPE_SW
        bne     sr_ena_2
 
-       /* Put DDR PHY's DLL in bypass mode for non-backup modes. */
+       /* Disable DX DLLs for non-backup modes. */
        cmp     r7, #AT91_PM_BACKUP
        beq     sr_ena_3
 
+       /* Do not soft reset the AC DLL. */
+       ldr     tmp1, [r3, DDR3PHY_ACDLLCR]
+       bic     tmp1, tmp1, DDR3PHY_ACDLLCR_DLLSRST
+       str     tmp1, [r3, DDR3PHY_ACDLLCR]
+
        /* Disable DX DLLs. */
        ldr     tmp1, [r3, #DDR3PHY_DX0DLLCR]
        orr     tmp1, tmp1, #DDR3PHY_DXDLLCR_DLLDIS

diff --git a/include/soc/at91/sama7-ddr.h b/include/soc/at91/sama7-ddr.h
index 6ce3bd2..5ad7ac2 100644 (file)
--- a/include/soc/at91/sama7-ddr.h
+++ b/include/soc/at91/sama7-ddr.h
@@ -26,7 +26,10 @@
 #define        DDR3PHY_PGSR                            (0x0C)          /* DDR3PHY PHY General Status Register */
 #define                DDR3PHY_PGSR_IDONE              (1 << 0)        /* Initialization Done */
 
-#define DDR3PHY_ACIOCR                         (0x24)          /*  DDR3PHY AC I/O Configuration Register */
+#define        DDR3PHY_ACDLLCR                         (0x14)          /* DDR3PHY AC DLL Control Register */
+#define                DDR3PHY_ACDLLCR_DLLSRST         (1 << 30)       /* DLL Soft Reset */
+
+#define DDR3PHY_ACIOCR                         (0x24)          /* DDR3PHY AC I/O Configuration Register */
 #define                DDR3PHY_ACIOCR_CSPDD_CS0        (1 << 18)       /* CS#[0] Power Down Driver */
 #define                DDR3PHY_ACIOCR_CKPDD_CK0        (1 << 8)        /* CK[0] Power Down Driver */
 #define                DDR3PHY_ACIORC_ACPDD            (1 << 3)        /* AC Power Down Driver */