reg = <0x10010000 0x400>;
};
+ cache-controller@0x10502000 {
+ compatible = "arm,pl310-cache";
+ reg = <0x10502000 0x1000>;
+ arm,tag-latency = <1 1 0>;
+ };
+
watchdog@10060000 {
compatible = "samsung,s3c2410-wdt";
reg = <0x10060000 0x100>;
<0 12 0>, <0 13 0>, <0 14 0>, <0 15 0>;
};
+ cache-controller@0x10502000 {
+ arm,data-latency = <1 1 0>;
+ };
+
mct@10050000 {
compatible = "samsung,exynos4210-mct";
reg = <0x10050000 0x800>;
<0 16 0>, <0 17 0>, <0 18 0>, <0 19 0>;
};
+ cache-controller@0x10502000 {
+ arm,data-latency = <1 2 0>;
+ };
+
clock: clock-controller@0x10030000 {
compatible = "samsung,exynos4412-clock";
reg = <0x10030000 0x20000>;