ARM: dts: exynos: Add support ARM architected timers on Exynos5

All CortexA7/A15 based Exynos5 SoCs have ARM architected timers, so enable
support for them directly in the base dtsi. None of the known firmware
properly configures CNTFRQ arch timer register, so force clock frequency
to 24MHz, which is the only configuration supported by the remaining
clock drivers so far.

Stock firmware for Peach Pit and Pi Chromebooks also doesn't reset
properly other arch timer registers, so add respective properties
indicating that. Other Exynos5-based boards behaves correctly in this area,
what finally allows to enable support for KVM-based virtualization.

Signed-off-by: Marek Szyprowski <m.szyprowski@samsung.com>

diff --git a/arch/arm/boot/dts/exynos5420-peach-pit.dts b/arch/arm/boot/dts/exynos5420-peach-pit.dts
index 14225f7ecd17288376cde7535c5a9cbddd9cc1f3..497d6b0a026e82aeaf33fa0e3e648f2124ffb487 100644 (file)
--- a/arch/arm/boot/dts/exynos5420-peach-pit.dts
+++ b/arch/arm/boot/dts/exynos5420-peach-pit.dts
@@ -1047,6 +1047,10 @@
        status = "okay";
 };
 
+&timer {
+       arm,cpu-registers-not-fw-configured;
+};
+
 &tmu_cpu0 {
        vtmu-supply = <&ldo10_reg>;
 };

diff --git a/arch/arm/boot/dts/exynos54xx.dtsi b/arch/arm/boot/dts/exynos54xx.dtsi
index 8f87ab1dd9e3aee2903924e84ddd38a167424df6..8ae2bfde6486d3374bd7c97fd1388a442d85ed8e 100644 (file)
--- a/arch/arm/boot/dts/exynos54xx.dtsi
+++ b/arch/arm/boot/dts/exynos54xx.dtsi
@@ -28,6 +28,15 @@
                usbdrdphy1 = &usbdrd_phy1;
        };
 
+       timer: timer {
+               compatible = "arm,armv7-timer";
+               interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
+                            <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
+                            <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
+                            <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>;
+               clock-frequency = <24000000>;
+       };
+
        soc: soc {
                arm_a7_pmu: arm-a7-pmu {
                        compatible = "arm,cortex-a7-pmu";

diff --git a/arch/arm/boot/dts/exynos5800-peach-pi.dts b/arch/arm/boot/dts/exynos5800-peach-pi.dts
index 50c515306f08d8caa1c311728af97c05a1bc2015..59e674ff16724c46d031fbcc10b1dfe5568ff4f1 100644 (file)
--- a/arch/arm/boot/dts/exynos5800-peach-pi.dts
+++ b/arch/arm/boot/dts/exynos5800-peach-pi.dts
@@ -1025,6 +1025,10 @@
        status = "okay";
 };
 
+&timer {
+       arm,cpu-registers-not-fw-configured;
+};
+
 &tmu_cpu0 {
        vtmu-supply = <&ldo10_reg>;
 };