#include <asm/kvm_host.h>
-u64 get_pvm_id_aa64pfr0(const struct kvm_vcpu *vcpu);
-u64 get_pvm_id_aa64pfr1(const struct kvm_vcpu *vcpu);
-u64 get_pvm_id_aa64zfr0(const struct kvm_vcpu *vcpu);
-u64 get_pvm_id_aa64dfr0(const struct kvm_vcpu *vcpu);
-u64 get_pvm_id_aa64dfr1(const struct kvm_vcpu *vcpu);
-u64 get_pvm_id_aa64afr0(const struct kvm_vcpu *vcpu);
-u64 get_pvm_id_aa64afr1(const struct kvm_vcpu *vcpu);
-u64 get_pvm_id_aa64isar0(const struct kvm_vcpu *vcpu);
-u64 get_pvm_id_aa64isar1(const struct kvm_vcpu *vcpu);
-u64 get_pvm_id_aa64mmfr0(const struct kvm_vcpu *vcpu);
-u64 get_pvm_id_aa64mmfr1(const struct kvm_vcpu *vcpu);
-u64 get_pvm_id_aa64mmfr2(const struct kvm_vcpu *vcpu);
-
+u64 pvm_read_id_reg(const struct kvm_vcpu *vcpu, u32 id);
bool kvm_handle_pvm_sysreg(struct kvm_vcpu *vcpu, u64 *exit_code);
int kvm_check_pvm_sysreg_table(void);
void inject_undef64(struct kvm_vcpu *vcpu);
*/
static void pvm_init_traps_aa64pfr0(struct kvm_vcpu *vcpu)
{
- const u64 feature_ids = get_pvm_id_aa64pfr0(vcpu);
+ const u64 feature_ids = pvm_read_id_reg(vcpu, SYS_ID_AA64PFR0_EL1);
u64 hcr_set = HCR_RW;
u64 hcr_clear = 0;
u64 cptr_set = 0;
*/
static void pvm_init_traps_aa64pfr1(struct kvm_vcpu *vcpu)
{
- const u64 feature_ids = get_pvm_id_aa64pfr1(vcpu);
+ const u64 feature_ids = pvm_read_id_reg(vcpu, SYS_ID_AA64PFR1_EL1);
u64 hcr_set = 0;
u64 hcr_clear = 0;
*/
static void pvm_init_traps_aa64dfr0(struct kvm_vcpu *vcpu)
{
- const u64 feature_ids = get_pvm_id_aa64dfr0(vcpu);
+ const u64 feature_ids = pvm_read_id_reg(vcpu, SYS_ID_AA64DFR0_EL1);
u64 mdcr_set = 0;
u64 mdcr_clear = 0;
u64 cptr_set = 0;
*/
static void pvm_init_traps_aa64mmfr0(struct kvm_vcpu *vcpu)
{
- const u64 feature_ids = get_pvm_id_aa64mmfr0(vcpu);
+ const u64 feature_ids = pvm_read_id_reg(vcpu, SYS_ID_AA64MMFR0_EL1);
u64 mdcr_set = 0;
/* Trap Debug Communications Channel registers */
*/
static void pvm_init_traps_aa64mmfr1(struct kvm_vcpu *vcpu)
{
- const u64 feature_ids = get_pvm_id_aa64mmfr1(vcpu);
+ const u64 feature_ids = pvm_read_id_reg(vcpu, SYS_ID_AA64MMFR1_EL1);
u64 hcr_set = 0;
/* Trap LOR */
* based on allowed features, system features, and KVM support.
*/
-u64 get_pvm_id_aa64pfr0(const struct kvm_vcpu *vcpu)
+static u64 get_pvm_id_aa64pfr0(const struct kvm_vcpu *vcpu)
{
const struct kvm *kvm = (const struct kvm *)kern_hyp_va(vcpu->kvm);
u64 set_mask = 0;
return (id_aa64pfr0_el1_sys_val & allow_mask) | set_mask;
}
-u64 get_pvm_id_aa64pfr1(const struct kvm_vcpu *vcpu)
+static u64 get_pvm_id_aa64pfr1(const struct kvm_vcpu *vcpu)
{
const struct kvm *kvm = (const struct kvm *)kern_hyp_va(vcpu->kvm);
u64 allow_mask = PVM_ID_AA64PFR1_ALLOW;
return id_aa64pfr1_el1_sys_val & allow_mask;
}
-u64 get_pvm_id_aa64zfr0(const struct kvm_vcpu *vcpu)
+static u64 get_pvm_id_aa64zfr0(const struct kvm_vcpu *vcpu)
{
/*
* No support for Scalable Vectors, therefore, hyp has no sanitized
return 0;
}
-u64 get_pvm_id_aa64dfr0(const struct kvm_vcpu *vcpu)
+static u64 get_pvm_id_aa64dfr0(const struct kvm_vcpu *vcpu)
{
/*
* No support for debug, including breakpoints, and watchpoints,
return 0;
}
-u64 get_pvm_id_aa64dfr1(const struct kvm_vcpu *vcpu)
+static u64 get_pvm_id_aa64dfr1(const struct kvm_vcpu *vcpu)
{
/*
* No support for debug, therefore, hyp has no sanitized copy of the
return 0;
}
-u64 get_pvm_id_aa64afr0(const struct kvm_vcpu *vcpu)
+static u64 get_pvm_id_aa64afr0(const struct kvm_vcpu *vcpu)
{
/*
* No support for implementation defined features, therefore, hyp has no
return 0;
}
-u64 get_pvm_id_aa64afr1(const struct kvm_vcpu *vcpu)
+static u64 get_pvm_id_aa64afr1(const struct kvm_vcpu *vcpu)
{
/*
* No support for implementation defined features, therefore, hyp has no
return 0;
}
-u64 get_pvm_id_aa64isar0(const struct kvm_vcpu *vcpu)
+static u64 get_pvm_id_aa64isar0(const struct kvm_vcpu *vcpu)
{
return id_aa64isar0_el1_sys_val & PVM_ID_AA64ISAR0_ALLOW;
}
-u64 get_pvm_id_aa64isar1(const struct kvm_vcpu *vcpu)
+static u64 get_pvm_id_aa64isar1(const struct kvm_vcpu *vcpu)
{
u64 allow_mask = PVM_ID_AA64ISAR1_ALLOW;
return id_aa64isar1_el1_sys_val & allow_mask;
}
-u64 get_pvm_id_aa64mmfr0(const struct kvm_vcpu *vcpu)
+static u64 get_pvm_id_aa64mmfr0(const struct kvm_vcpu *vcpu)
{
u64 set_mask;
return (id_aa64mmfr0_el1_sys_val & PVM_ID_AA64MMFR0_ALLOW) | set_mask;
}
-u64 get_pvm_id_aa64mmfr1(const struct kvm_vcpu *vcpu)
+static u64 get_pvm_id_aa64mmfr1(const struct kvm_vcpu *vcpu)
{
return id_aa64mmfr1_el1_sys_val & PVM_ID_AA64MMFR1_ALLOW;
}
-u64 get_pvm_id_aa64mmfr2(const struct kvm_vcpu *vcpu)
+static u64 get_pvm_id_aa64mmfr2(const struct kvm_vcpu *vcpu)
{
return id_aa64mmfr2_el1_sys_val & PVM_ID_AA64MMFR2_ALLOW;
}
-/* Read a sanitized cpufeature ID register by its sys_reg_desc. */
-static u64 read_id_reg(const struct kvm_vcpu *vcpu,
- struct sys_reg_desc const *r)
+/* Read a sanitized cpufeature ID register by its encoding */
+u64 pvm_read_id_reg(const struct kvm_vcpu *vcpu, u32 id)
{
- u32 id = reg_to_encoding(r);
-
switch (id) {
case SYS_ID_AA64PFR0_EL1:
return get_pvm_id_aa64pfr0(vcpu);
return 0;
}
+static u64 read_id_reg(const struct kvm_vcpu *vcpu,
+ struct sys_reg_desc const *r)
+{
+ return pvm_read_id_reg(vcpu, reg_to_encoding(r));
+}
+
/*
* Accessor for AArch32 feature id registers.
*