#include <common.h>
#include <command.h>
#include <pci.h>
+#include <netdev.h>
#include "articiaS.h"
#include "memio.h"
#include "via686.h"
articiaS_pci_init ();
#endif
}
+
+int board_eth_init(bd_t *bis)
+{
+#if defined(CONFIG_3COM)
+ eth_3com_initialize(bis);
+#endif
+ return 0;
+}
#include <common.h>
#include <malloc.h>
#include <net.h>
+#include <netdev.h>
#include <asm/io.h>
#include <pci.h>
#include "../include/pci.h"
#include "../include/mv_gen_reg.h"
#include <net.h>
+#include <netdev.h>
#include "eth.h"
#include "mpsc.h"
icache_disable ();
dcache_disable ();
}
+
+int board_eth_init(bd_t *bis)
+{
+ return pci_eth_init(bis);
+}
#include "../include/pci.h"
#include "../include/mv_gen_reg.h"
#include <net.h>
+#include <netdev.h>
#include "eth.h"
#include "mpsc.h"
icache_disable ();
dcache_disable ();
}
+
+int board_eth_init(bd_t *bis)
+{
+ return pci_eth_init(bis);
+}
#include <common.h>
#include <mpc824x.h>
#include <pci.h>
+#include <netdev.h>
int checkboard (void)
{
{
pci_mpc824x_init(&hose);
}
+
+int board_eth_init(bd_t *bis)
+{
+ return pci_eth_init(bis);
+}
+
#include <i2c.h>
#include <libfdt.h>
#include <fdt_support.h>
+#include <netdev.h>
#include <asm/processor.h>
#include <asm/io.h>
#include <asm/gpio.h>
return (ctrlc());
}
#endif
+
+int board_eth_init(bd_t *bis)
+{
+ return pci_eth_init(bis);
+}
#include <asm/processor.h>
#include <asm/io.h>
#include <spi.h>
+#include <netdev.h>
#include <asm/gpio.h>
extern int lcd_init(void);
return 1;
}
#endif /* CONFIG_PCI */
+
+int board_eth_init(bd_t *bis)
+{
+ return pci_eth_init(bis);
+}
#include <asm/processor.h>
#include <spd_sdram.h>
#include <ppc4xx_enet.h>
+#include <netdev.h>
#ifdef CFG_INIT_SHOW_RESET_REG
void show_reset_reg(void);
return (ctrlc());
}
#endif
+
+int board_eth_init(bd_t *bis)
+{
+ return pci_eth_init(bis);
+}
#include <common.h>
#include <ppc4xx.h>
#include <i2c.h>
+#include <netdev.h>
#include <asm/processor.h>
#include <asm/io.h>
#include <asm/4xx_pcie.h>
#endif
return (BOARD_OPTION_NOT_SELECTED);
}
+
+int board_eth_init(bd_t *bis)
+{
+ return pci_eth_init(bis);
+}
#include <common.h>
#include <command.h>
+#include <netdev.h>
#include <asm/processor.h>
#include "powerspan.h"
"swrecon - trigger a board reconfigure to the software selected configuration\n",
"\n"
" - trigger a board reconfigure to the software selected configuration\n");
+
+int board_eth_init(bd_t *bis)
+{
+ return pci_eth_init(bis);
+}
+
#include <asm/arch/at91_rstc.h>
#include <asm/arch/gpio.h>
#include <asm/arch/io.h>
+#include <asm/arch/hardware.h>
#include <lcd.h>
#include <atmel_lcdc.h>
#if defined(CONFIG_RESET_PHY_R) && defined(CONFIG_MACB)
#include <net.h>
#endif
+#include <netdev.h>
#define MP_BLOCK_3_BASE 0xFDF00000
#endif
}
#endif
+
+int board_eth_init(bd_t *bis)
+{
+ int rc = 0;
+#ifdef CONFIG_MACB
+ rc = macb_eth_initialize(0, (void *)AT91_BASE_EMAC, 0x00);
+#endif
+ return rc;
+}
#include <asm/arch/at91_rstc.h>
#include <asm/arch/gpio.h>
#include <asm/arch/io.h>
+#include <asm/arch/hardware.h>
#if defined(CONFIG_RESET_PHY_R) && defined(CONFIG_MACB)
#include <net.h>
#endif
+#include <netdev.h>
DECLARE_GLOBAL_DATA_PTR;
#endif
}
#endif
+
+int board_eth_init(bd_t *bis)
+{
+ int rc = 0;
+#ifdef CONFIG_MACB
+ rc = macb_eth_initialize(0, (void *)AT91_BASE_EMAC, 0x00);
+#endif
+ return rc;
+}
#include <asm/arch/at91_rstc.h>
#include <asm/arch/gpio.h>
#include <asm/arch/io.h>
+#include <asm/arch/hardware.h>
#include <lcd.h>
#include <atmel_lcdc.h>
#if defined(CONFIG_RESET_PHY_R) && defined(CONFIG_MACB)
#include <net.h>
#endif
+#include <netdev.h>
DECLARE_GLOBAL_DATA_PTR;
#endif
}
#endif
+
+int board_eth_init(bd_t *bis)
+{
+ int rc = 0;
+#ifdef CONFIG_MACB
+ rc = macb_eth_initialize(0, (void *)AT91_BASE_EMAC, 0x00);
+#endif
+ return rc;
+}
#include <asm/arch/clk.h>
#include <asm/arch/gpio.h>
#include <asm/arch/hmatrix.h>
+#include <netdev.h>
DECLARE_GLOBAL_DATA_PTR;
gd->bd->bi_phy_id[1] = 0x03;
}
-extern int macb_eth_initialize(int id, void *regs, unsigned int phy_addr);
-
#ifdef CONFIG_CMD_NET
int board_eth_init(bd_t *bi)
{
#include <asm/arch/clk.h>
#include <asm/arch/gpio.h>
#include <asm/arch/hmatrix.h>
+#include <netdev.h>
DECLARE_GLOBAL_DATA_PTR;
gd->bd->bi_phy_id[1] = 0x11;
}
-extern int macb_eth_initialize(int id, void *regs, unsigned int phy_addr);
-
#ifdef CONFIG_CMD_NET
int board_eth_init(bd_t *bi)
{
#include <common.h>
#include <mpc5xxx.h>
#include <pci.h>
+#include <netdev.h>
#ifdef CONFIG_VIDEO_SM501
#include <sm501.h>
}
#endif /* CONFIG_VIDEO_SM501 */
+
+int board_eth_init(bd_t *bis)
+{
+ cpu_eth_init(bis); /* Built in FEC comes first */
+ return pci_eth_init(bis);
+}
#include <asm/io.h>
#include <net.h>
#include <asm/mach-common/bits/bootrom.h>
+#include <netdev.h>
/**
* is_valid_ether_addr - Determine if the given Ethernet address is valid
#if defined(CONFIG_BFIN_MAC)
-extern int bfin_EMAC_initialize(bd_t *bis);
-
int board_eth_init(bd_t *bis)
{
return bfin_EMAC_initialize(bis);
#include <asm/io.h>
#include <pci.h>
#include <i2c.h>
+#include <netdev.h>
int sysControlDisplay(int digit, uchar ascii_code);
extern void Plx9030Init(void);
writeb(val, BCSR_BASE + 0x04);
}
# endif
+
+int board_eth_init(bd_t *bis)
+{
+ return pci_eth_init(bis);
+}
#include <mpc8260.h>
#include "cpu87.h"
#include <pci.h>
+#include <netdev.h>
/*
* I/O Port configuration table
pci_mpc8250_init(&hose);
}
#endif
+
+int board_eth_init(bd_t *bis)
+{
+ return pci_eth_init(bis);
+}
#include <mpc824x.h>
#include <asm/processor.h>
#include <pci.h>
+#include <netdev.h>
DECLARE_GLOBAL_DATA_PTR;
{
pci_mpc824x_init(&hose);
}
+
+int board_eth_init(bd_t *bis)
+{
+ return pci_eth_init(bis);
+}
#include <asm/io.h>
#include <pci.h>
#include <ide.h>
+#include <netdev.h>
#include "piix_pci.h"
#include "eXalion.h"
{
pci_mpc824x_init (&hose);
}
+
+int board_eth_init(bd_t *bis)
+{
+ return pci_eth_init(bis);
+}
* Place, Suite 330, Boston, MA 02111-1307 USA
*/
#include <common.h>
+#include <netdev.h>
#include <asm/io.h>
#include <asm/sdram.h>
}
#if defined(CONFIG_MACB) && defined(CONFIG_CMD_NET)
-extern int macb_eth_initialize(int id, void *regs, unsigned int phy_addr);
-
int board_eth_init(bd_t *bi)
{
return macb_eth_initialize(0, (void *)MACB0_BASE, bi->bi_phy_id[0]);
#include <74xx_7xx.h>
#include <ns87308.h>
#include <video_fb.h>
+#include <netdev.h>
DECLARE_GLOBAL_DATA_PTR;
#endif
/*---------------------------------------------------------------------------*/
+
+int board_eth_init(bd_t *bis)
+{
+ return pci_eth_init(bis);
+}
#include <command.h>
#include <mpc106.h>
#include <video_fb.h>
+#include <netdev.h>
DECLARE_GLOBAL_DATA_PTR;
return;
}
#endif
+
+int board_eth_init(bd_t *bis)
+{
+ return pci_eth_init(bis);
+}
*/
#include <common.h>
+#include <netdev.h>
#include "adciop.h"
/* ------------------------------------------------------------------------- */
}
/* ------------------------------------------------------------------------- */
+
+int board_eth_init(bd_t *bis)
+{
+ return pci_eth_init(bis);
+}
return 0;
}
-phys_size_t initdram (int board_type)
-{
- unsigned long val;
-
- mtdcr(memcfga, mem_mb0cf);
- val = mfdcr(memcfgd);
-
- return (4*1024*1024 << ((val & 0x000e0000) >> 17));
-}
-
#ifdef CONFIG_IDE_RESET
void ide_set_reset(int on)
{
common/cmd_mem.o (.text)
common/cmd_nvedit.o (.text)
common/console.o (.text)
- common/lists.o (.text)
common/main.o (.text)
/*
return 0;
}
-
-/* ------------------------------------------------------------------------- */
-
-int misc_init_f (void)
-{
- return 0; /* dummy implementation */
-}
-
-
int misc_init_r (void)
{
volatile unsigned char *duart0_mcr = (unsigned char *)((ulong)DUART0_BA + 4);
return 0;
}
-/* ------------------------------------------------------------------------- */
-
-phys_size_t initdram (int board_type)
-{
- unsigned long val;
-
- mtdcr(memcfga, mem_mb0cf);
- val = mfdcr(memcfgd);
-
- return (4*1024*1024 << ((val & 0x000e0000) >> 17));
-}
-
-/* ------------------------------------------------------------------------- */
-
void reset_phy(void)
{
#ifdef CONFIG_LXT971_NO_SLEEP
common/cmd_mem.o (.text)
common/cmd_nvedit.o (.text)
common/console.o (.text)
- common/lists.o (.text)
common/main.o (.text)
net/net.o (.text)
return 0;
}
-
-/* ------------------------------------------------------------------------- */
-
-int misc_init_f (void)
-{
- return 0; /* dummy implementation */
-}
-
-
int misc_init_r (void)
{
/* adjust flash start and offset */
/* ------------------------------------------------------------------------- */
-phys_size_t initdram (int board_type)
-{
- unsigned long val;
-
- mtdcr(memcfga, mem_mb0cf);
- val = mfdcr(memcfgd);
-
- return (4*1024*1024 << ((val & 0x000e0000) >> 17));
-}
-
-/* ------------------------------------------------------------------------- */
-
#if defined(CFG_EEPROM_WREN)
/* Input: <dev_addr> I2C address of EEPROM device to enable.
* <state> -1: deliver current state
return 0;
}
-
-int misc_init_f (void)
-{
- return 0; /* dummy implementation */
-}
-
-
int misc_init_r (void)
{
unsigned long cntrl0Reg;
return 0;
}
-/* ------------------------------------------------------------------------- */
-
-phys_size_t initdram (int board_type)
-{
- unsigned long val;
-
- mtdcr(memcfga, mem_mb0cf);
- val = mfdcr(memcfgd);
-
- return (4*1024*1024 << ((val & 0x000e0000) >> 17));
-}
-
-/* ------------------------------------------------------------------------- */
-
#if defined(CFG_EEPROM_WREN)
/* Input: <dev_addr> I2C address of EEPROM device to enable.
* <state> -1: deliver current state
}
}
-int misc_init_f (void)
-{
- return 0; /* dummy implementation */
-}
-
int misc_init_r (void)
{
unsigned long cntrl0Reg;
return 0;
}
-/* ------------------------------------------------------------------------- */
-
-phys_size_t initdram (int board_type)
-{
- unsigned long val;
-
- mtdcr(memcfga, mem_mb0cf);
- val = mfdcr(memcfgd);
-
- return (4*1024*1024 << ((val & 0x000e0000) >> 17));
-}
-
void reset_phy(void)
{
#ifdef CONFIG_LXT971_NO_SLEEP
#endif
}
-/* ------------------------------------------------------------------------- */
-
#ifdef CONFIG_CPCI405_VER2
#ifdef CONFIG_IDE_RESET
#include <mpc5xxx.h>
#include <pci.h>
#include <command.h>
+#include <netdev.h>
#include "mt46v16m16-75.h"
}
}
+int board_eth_init(bd_t *bis)
+{
+ return pci_eth_init(bis);
+}
+
int do_writepci(cmd_tbl_t * cmdtp, int flag, int argc, char *argv[])
{
unsigned int addr;
return 0;
}
-
-/* ------------------------------------------------------------------------- */
-
-phys_size_t initdram (int board_type)
-{
- return (16 * 1024 * 1024);
-}
-
-/* ------------------------------------------------------------------------- */
-
-int testdram (void)
-{
- /* TODO: XXX XXX XXX */
- printf ("test: 16 MB - ok\n");
-
- return (0);
-}
-
-/* ------------------------------------------------------------------------- */
*/
#include <common.h>
+#include <netdev.h>
#include "dasa_sim.h"
/* ------------------------------------------------------------------------- */
return 0;
}
-
-/* ------------------------------------------------------------------------- */
-
phys_size_t initdram (int board_type)
{
return (16 * 1024 * 1024);
}
-
-/* ------------------------------------------------------------------------- */
-
-int testdram (void)
-{
- /* TODO: XXX XXX XXX */
- printf ("test: 16 MB - ok\n");
-
- return (0);
-}
-
-/* ------------------------------------------------------------------------- */
common/cmd_mem.o (.text)
common/cmd_nvedit.o (.text)
common/console.o (.text)
- common/lists.o (.text)
common/main.o (.text)
board/esd/dasa_sim/flash.o (.text)
return 0;
}
-
-/* ------------------------------------------------------------------------- */
-
-int misc_init_f (void)
-{
- return 0; /* dummy implementation */
-}
-
-
int misc_init_r (void)
{
/* adjust flash start and offset */
return 0;
}
-
-/* ------------------------------------------------------------------------- */
-
-phys_size_t initdram (int board_type)
-{
- unsigned long val;
-
- mtdcr(memcfga, mem_mb0cf);
- val = mfdcr(memcfgd);
-
-#if 0
- printf("\nmb0cf=%x\n", val); /* test-only */
- printf("strap=%x\n", mfdcr(strap)); /* test-only */
-#endif
-
- return (4*1024*1024 << ((val & 0x000e0000) >> 17));
-}
-
-/* ------------------------------------------------------------------------- */
-
-int testdram (void)
-{
- /* TODO: XXX XXX XXX */
- printf ("test: 16 MB - ok\n");
-
- return (0);
-}
return 0;
}
-
-
-phys_size_t initdram (int board_type)
-{
- return (16 * 1024 * 1024);
-}
-
-
-int testdram (void)
-{
- /* TODO: XXX XXX XXX */
- printf ("test: 16 MB - ok\n");
-
- return (0);
-}
return 0;
}
-
-phys_size_t initdram (int board_type)
-{
- unsigned long val;
-
- mtdcr(memcfga, mem_mb0cf);
- val = mfdcr(memcfgd);
-
-#if 0
- printf("\nmb0cf=%x\n", val); /* test-only */
- printf("strap=%x\n", mfdcr(strap)); /* test-only */
-#endif
-
- return (4*1024*1024 << ((val & 0x000e0000) >> 17));
-}
-
-
#ifdef CONFIG_IDE_RESET
void ide_set_reset(int on)
{
return 0;
}
-
-int misc_init_f (void)
-{
- return 0; /* dummy implementation */
-}
-
-
int misc_init_r (void)
{
volatile unsigned char *duart0_mcr = (unsigned char *)((ulong)DUART0_BA + 4);
return 0;
}
-
-
-phys_size_t initdram (int board_type)
-{
- unsigned long val;
-
- mtdcr(memcfga, mem_mb0cf);
- val = mfdcr(memcfgd);
-
- return (4*1024*1024 << ((val & 0x000e0000) >> 17));
-}
#include <mpc5xxx.h>
#include <pci.h>
#include <command.h>
+#include <netdev.h>
#include "mt46v16m16-75.h"
__asm__ volatile ("sync");
}
}
+
+int board_eth_init(bd_t *bis)
+{
+ return pci_eth_init(bis);
+}
return 0;
}
-
-int misc_init_f (void)
-{
- return 0; /* dummy implementation */
-}
-
-
/*
* Check Board Identity:
*/
return (0);
}
-
-
-phys_size_t initdram (int board_type)
-{
- unsigned long val;
-
- mtdcr (memcfga, mem_mb0cf);
- val = mfdcr (memcfgd);
-
-#if 0
- printf ("\nmb0cf=%x\n", val); /* test-only */
- printf ("strap=%x\n", mfdcr (strap)); /* test-only */
-#endif
-
- return (4 * 1024 * 1024 << ((val & 0x000e0000) >> 17));
-}
-
-
-int testdram (void)
-{
- /* TODO: XXX XXX XXX */
- printf ("test: 16 MB - ok\n");
-
- return (0);
-}
#include <mpc5xxx.h>
#include <pci.h>
#include <command.h>
+#include <netdev.h>
#include "mt46v16m16-75.h"
__asm__ volatile ("sync");
}
+int board_eth_init(bd_t *bis)
+{
+ return pci_eth_init(bis);
+}
+
void power_set_reset(int power)
{
debug("ide_set_reset(%d)\n", power);
# esd PLU405 boards
#
-TEXT_BASE = 0xFFFC0000
-#TEXT_BASE = 0x00FC0000
+TEXT_BASE = 0xFFFA0000
int N_AU_IMAGES = (sizeof(au_image) / sizeof(au_image[0]));
-
/* Prototypes */
int gunzip(void *, int, unsigned char *, unsigned long *);
-
int board_early_init_f (void)
{
/*
mtdcr(uiccr, 0x00000000); /* set all to be non-critical*/
mtdcr(uicpr, 0xFFFFFF99); /* set int polarities */
mtdcr(uictr, 0x10000000); /* set int trigger levels */
- mtdcr(uicvcr, 0x00000001); /* set vect base=0,INT0 highest priority*/
+ mtdcr(uicvcr, 0x00000001); /* set vect base=0,INT0 highest prio */
mtdcr(uicsr, 0xFFFFFFFF); /* clear all ints */
/*
- * EBC Configuration Register: set ready timeout to 512 ebc-clks -> ca. 15 us
+ * EBC Configuration Register: set ready timeout to
+ * 512 ebc-clks -> ca. 15 us
*/
mtebc (epcr, 0xa8400000); /* ebc always driven */
return 0;
}
-
-int misc_init_f (void)
-{
- return 0; /* dummy implementation */
-}
-
-
int misc_init_r (void)
{
unsigned char *duart0_mcr = (unsigned char *)((ulong)DUART0_BA + 4);
printf("\nFPGA: Booting failed ");
switch (status) {
case ERROR_FPGA_PRG_INIT_LOW:
- printf("(Timeout: INIT not low after asserting PROGRAM*)\n ");
+ printf("(Timeout: INIT not low "
+ "after asserting PROGRAM*)\n");
break;
case ERROR_FPGA_PRG_INIT_HIGH:
- printf("(Timeout: INIT not high after deasserting PROGRAM*)\n ");
+ printf("(Timeout: INIT not high "
+ "after deasserting PROGRAM*)\n");
break;
case ERROR_FPGA_PRG_DONE:
- printf("(Timeout: DONE not high after programming FPGA)\n ");
+ printf("(Timeout: DONE not high "
+ "after programming FPGA)\n");
break;
}
/*
* Reset external DUARTs
*/
- out_be32((void*)GPIO0_OR, in_be32((void*)GPIO0_OR) | CFG_DUART_RST); /* set reset to high */
- udelay(10); /* wait 10us */
- out_be32((void*)GPIO0_OR, in_be32((void*)GPIO0_OR) & ~CFG_DUART_RST); /* set reset to low */
- udelay(1000); /* wait 1ms */
+ out_be32((void*)GPIO0_OR, in_be32((void*)GPIO0_OR) | CFG_DUART_RST);
+ udelay(10);
+ out_be32((void*)GPIO0_OR, in_be32((void*)GPIO0_OR) & ~CFG_DUART_RST);
+ udelay(1000);
/*
* Set NAND-FLASH GPIO signals to default
*/
- out_be32((void*)GPIO0_OR, in_be32((void*)GPIO0_OR) & ~(CFG_NAND_CLE | CFG_NAND_ALE));
+ out_be32((void*)GPIO0_OR,
+ in_be32((void*)GPIO0_OR) & ~(CFG_NAND_CLE | CFG_NAND_ALE));
out_be32((void*)GPIO0_OR, in_be32((void*)GPIO0_OR) | CFG_NAND_CE);
/*
return (0);
}
-
/*
* Check Board Identity:
*/
return 0;
}
-
-phys_size_t initdram (int board_type)
-{
- unsigned long val;
-
- mtdcr(memcfga, mem_mb0cf);
- val = mfdcr(memcfgd);
-
- return (4*1024*1024 << ((val & 0x000e0000) >> 17));
-}
-
-
#ifdef CONFIG_IDE_RESET
void ide_set_reset(int on)
{
}
#endif /* CONFIG_IDE_RESET */
-
void reset_phy(void)
{
#ifdef CONFIG_LXT971_NO_SLEEP
#endif
}
-
#if defined(CFG_EEPROM_WREN)
/* Input: <dev_addr> I2C address of EEPROM device to enable.
* <state> -1: deliver current state
switch (state) {
case 1:
/* Enable write access, clear bit GPIO0. */
- out_be32((void*)GPIO0_OR, in_be32((void*)GPIO0_OR) & ~CFG_EEPROM_WP);
+ out_be32((void*)GPIO0_OR,
+ in_be32((void*)GPIO0_OR) & ~CFG_EEPROM_WP);
state = 0;
break;
case 0:
/* Disable write access, set bit GPIO0. */
- out_be32((void*)GPIO0_OR, in_be32((void*)GPIO0_OR) | CFG_EEPROM_WP);
+ out_be32((void*)GPIO0_OR,
+ in_be32((void*)GPIO0_OR) | CFG_EEPROM_WP);
state = 0;
break;
default:
/* Read current status back. */
- state = (0 == (in_be32((void*)GPIO0_OR) & CFG_EEPROM_WP));
+ state = (0 == (in_be32((void*)GPIO0_OR) &
+ CFG_EEPROM_WP));
break;
}
}
/* the sector layout of our flash chips! XXX FIXME XXX */
cpu/ppc4xx/start.o (.text)
- cpu/ppc4xx/traps.o (.text)
- cpu/ppc4xx/interrupts.o (.text)
- cpu/ppc4xx/4xx_uart.o (.text)
- cpu/ppc4xx/cpu_init.o (.text)
- cpu/ppc4xx/speed.o (.text)
- cpu/ppc4xx/4xx_enet.o (.text)
- common/dlmalloc.o (.text)
- lib_generic/crc32.o (.text)
- lib_ppc/extable.o (.text)
- lib_generic/zlib.o (.text)
-
-/* . = env_offset;*/
-/* common/environment.o(.text)*/
*(.text)
*(.fixup)
.u_boot_cmd : { *(.u_boot_cmd) }
__u_boot_cmd_end = .;
-
. = .;
__start___ex_table = .;
__ex_table : { *(__ex_table) }
}
/* ------------------------------------------------------------------------- */
-
-phys_size_t initdram (int board_type)
-{
- unsigned long val;
-
- mtdcr(memcfga, mem_mb0cf);
- val = mfdcr(memcfgd);
-
-#if 0
- printf("\nmb0cf=%x\n", val); /* test-only */
- printf("strap=%x\n", mfdcr(strap)); /* test-only */
-#endif
-
- return (4*1024*1024 << ((val & 0x000e0000) >> 17));
-}
-
-
-/* ------------------------------------------------------------------------- */
void reset_phy(void)
{
#ifdef CONFIG_LXT971_NO_SLEEP
return 0;
}
-
-int misc_init_f (void)
-{
- return 0; /* dummy implementation */
-}
-
-
int misc_init_r (void)
{
unsigned char *duart0_mcr = (unsigned char *)((ulong)DUART0_BA + 4);
return 0;
}
-/* ------------------------------------------------------------------------- */
-
-phys_size_t initdram (int board_type)
-{
- unsigned long val;
-
- mtdcr(memcfga, mem_mb0cf);
- val = mfdcr(memcfgd);
-
-#if 0
- printf("\nmb0cf=%x\n", val); /* test-only */
- printf("strap=%x\n", mfdcr(strap)); /* test-only */
-#endif
-
- return (4*1024*1024 << ((val & 0x000e0000) >> 17));
-}
-
-/* ------------------------------------------------------------------------- */
-
-int testdram (void)
-{
- /* TODO: XXX XXX XXX */
- printf ("test: 16 MB - ok\n");
-
- return (0);
-}
-
-/* ------------------------------------------------------------------------- */
-
#ifdef CONFIG_IDE_RESET
void ide_set_reset(int on)
{
/* the sector layout of our flash chips! XXX FIXME XXX */
cpu/ppc4xx/start.o (.text)
- cpu/ppc4xx/traps.o (.text)
- cpu/ppc4xx/interrupts.o (.text)
- cpu/ppc4xx/4xx_uart.o (.text)
- cpu/ppc4xx/cpu_init.o (.text)
- cpu/ppc4xx/speed.o (.text)
- common/dlmalloc.o (.text)
- lib_generic/crc32.o (.text)
- lib_ppc/extable.o (.text)
- lib_generic/zlib.o (.text)
-
-/* . = env_offset;*/
-/* common/environment.o(.text)*/
*(.text)
*(.fixup)
};
int filesize = sizeof(fpgadata);
-
int board_early_init_f (void)
{
/*
return 0;
}
-
-/* ------------------------------------------------------------------------- */
-
int misc_init_r (void)
{
/* adjust flash start and offset */
return (0);
}
-
/*
* Check Board Identity:
*/
-
int checkboard (void)
{
char str[64];
return 0;
}
-/* ------------------------------------------------------------------------- */
-
-phys_size_t initdram (int board_type)
-{
- unsigned long val;
-
- mtdcr(memcfga, mem_mb0cf);
- val = mfdcr(memcfgd);
-
-#if 0
- printf("\nmb0cf=%x\n", val); /* test-only */
- printf("strap=%x\n", mfdcr(strap)); /* test-only */
-#endif
-
- return (4*1024*1024 << ((val & 0x000e0000) >> 17));
-}
-
-/* ------------------------------------------------------------------------- */
-
void reset_phy(void)
{
#ifdef CONFIG_LXT971_NO_SLEEP
return 0;
}
-
-/* ------------------------------------------------------------------------- */
-
-int misc_init_f (void)
-{
- return 0; /* dummy implementation */
-}
-
-
int misc_init_r (void)
{
volatile unsigned char *duart0_mcr = (unsigned char *)((ulong)DUART0_BA + 4);
return 0;
}
-
-/* ------------------------------------------------------------------------- */
-
-phys_size_t initdram (int board_type)
-{
- unsigned long val;
-
- mtdcr(memcfga, mem_mb0cf);
- val = mfdcr(memcfgd);
-
- return (4*1024*1024 << ((val & 0x000e0000) >> 17));
-}
#include <mpc824x.h>
#include <pci.h>
#include <i2c.h>
+#include <netdev.h>
DECLARE_GLOBAL_DATA_PTR;
(char*)&gd->bd->bi_enetaddr[0], 6);
return 0;
}
+
+int board_eth_init(bd_t *bis)
+{
+ return pci_eth_init(bis);
+}
#include <mpc824x.h>
#include <pci.h>
#include <i2c.h>
+#include <netdev.h>
#include <asm/processor.h>
int checkboard(void)
asm volatile("sync");
}
}
+
+int board_eth_init(bd_t *bis)
+{
+ return pci_eth_init(bis);
+}
#include <asm/cache.h>
#include <miiphy.h>
#include <net.h>
+#include <netdev.h>
#include "eth.h"
#include "eth_addrtbl.h"
#include <galileo/pci.h>
#include <galileo/gt64260R.h>
#include <net.h>
+#include <netdev.h>
#include <asm/io.h>
#include "eth.h"
sram_boot = 1;
#endif
- if (!sram_boot)
memoryMapDeviceSpace(DEVICE0, CFG_DEV0_SPACE, CFG_DEV0_SIZE);
memoryMapDeviceSpace(DEVICE1, CFG_DEV1_SPACE, CFG_DEV1_SIZE);
printf(" BOOT: base - 0x%08x\tsize - %dM bytes\twidth - %d bits\n",
base, size>>20, width);
}
+
+int board_eth_init(bd_t *bis)
+{
+ gt6426x_eth_initialize(bis);
+ return 0;
+}
COBJS-${CONFIG_FSL_PIXIS} += pixis.o
COBJS-${CONFIG_PQ_MDS_PIB} += pq-mds-pib.o
COBJS-${CONFIG_ID_EEPROM} += sys_eeprom.o
+COBJS-${CONFIG_FSL_SGMII_RISER} += sgmii_riser.o
COBJS-${CONFIG_MPC8541CDS} += cds_pci_ft.o
COBJS-${CONFIG_MPC8548CDS} += cds_pci_ft.o
#include <command.h>
#include <watchdog.h>
#include <asm/cache.h>
+#include <asm/io.h>
#include "pixis.h"
"diswd - Disable watchdog timer \n",
NULL);
+#ifdef CONFIG_FSL_SGMII_RISER
+int pixis_set_sgmii(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
+{
+ int which_tsec = -1;
+ uchar mask;
+ uchar switch_mask;
+
+ if (argc > 2)
+ if (strcmp(argv[1], "all") != 0)
+ which_tsec = simple_strtoul(argv[1], NULL, 0);
+
+ switch (which_tsec) {
+ case 1:
+ mask = PIXIS_VSPEED2_TSEC1SER;
+ switch_mask = PIXIS_VCFGEN1_TSEC1SER;
+ break;
+ case 3:
+ mask = PIXIS_VSPEED2_TSEC3SER;
+ switch_mask = PIXIS_VCFGEN1_TSEC3SER;
+ break;
+ default:
+ mask = PIXIS_VSPEED2_TSEC1SER | PIXIS_VSPEED2_TSEC3SER;
+ switch_mask = PIXIS_VCFGEN1_TSEC1SER | PIXIS_VCFGEN1_TSEC3SER;
+ break;
+ }
+
+ /* Toggle whether the switches or FPGA control the settings */
+ if (!strcmp(argv[argc - 1], "switch"))
+ clrbits_8((unsigned char *)PIXIS_BASE + PIXIS_VCFGEN1,
+ switch_mask);
+ else
+ setbits_8((unsigned char *)PIXIS_BASE + PIXIS_VCFGEN1,
+ switch_mask);
+
+ /* If it's not the switches, enable or disable SGMII, as specified */
+ if (!strcmp(argv[argc - 1], "on"))
+ clrbits_8((unsigned char *)PIXIS_BASE + PIXIS_VSPEED2, mask);
+ else if (!strcmp(argv[argc - 1], "off"))
+ setbits_8((unsigned char *)PIXIS_BASE + PIXIS_VSPEED2, mask);
+
+ return 0;
+}
+
+U_BOOT_CMD(
+ pixis_set_sgmii, CFG_MAXARGS, 1, pixis_set_sgmii,
+ "pixis_set_sgmii"
+ " - Enable or disable SGMII mode for a given TSEC \n",
+ "\npixis_set_sgmii [TSEC num] <on|off|switch>\n"
+ " TSEC num: 1,2,3,4 or 'all'. 'all' is default.\n"
+ " on - enables SGMII\n"
+ " off - disables SGMII\n"
+ " switch - use switch settings\n");
+#endif
+
/*
* This function takes the non-integral cpu:mpx pll ratio
* and converts it to an integer that can be used to assign
--- /dev/null
+/*
+ * Freescale SGMII Riser Card
+ *
+ * This driver supports the SGMII Riser card found on the
+ * "DS" style of development board from Freescale.
+ *
+ * This software may be used and distributed according to the
+ * terms of the GNU Public License, Version 2, incorporated
+ * herein by reference.
+ *
+ * Copyright 2008 Freescale Semiconductor, Inc.
+ *
+ */
+
+#include <config.h>
+#include <common.h>
+#include <tsec.h>
+
+void fsl_sgmii_riser_init(struct tsec_info_struct *tsec_info, int num)
+{
+ int i;
+
+ for (i = 0; i < num; i++)
+ if (tsec_info[i].flags & TSEC_SGMII)
+ tsec_info[i].phyaddr += SGMII_RISER_PHY_OFFSET;
+}
--- /dev/null
+/*
+ * Freescale SGMII Riser Card
+ *
+ * This driver supports the SGMII Riser card found on the
+ * "DS" style of development board from Freescale.
+ *
+ * This software may be used and distributed according to the
+ * terms of the GNU Public License, Version 2, incorporated
+ * herein by reference.
+ *
+ * Copyright 2008 Freescale Semiconductor, Inc.
+ *
+ */
+
+void fsl_sgmii_riser_init(struct tsec_info_struct *tsec_info, int num);
#include <common.h>
#include <74xx_7xx.h>
#include <fdt_support.h>
+#include <netdev.h>
#undef DEBUG
fdt_fixup_memory(blob, (u64)bd->bi_memstart, (u64)bd->bi_memsize);
}
#endif
+
+int board_eth_init(bd_t *bis)
+{
+ int rc = 0;
+#if defined(CONFIG_TSI108_ETH)
+ rc = tsi108_eth_initialize(bis);
+#endif
+ return rc;
+}
#include <fdt_support.h>
#include <pci.h>
#include <mpc83xx.h>
+#include <netdev.h>
DECLARE_GLOBAL_DATA_PTR;
fdt_tsec1_fixup(blob, bd);
}
#endif
+
+int board_eth_init(bd_t *bis)
+{
+ cpu_eth_init(bis); /* Initialize TSECs first */
+ return pci_eth_init(bis);
+}
#include <miiphy.h>
#include <libfdt.h>
#include <fdt_support.h>
+#include <tsec.h>
+#include <netdev.h>
#include "../common/pixis.h"
+#include "../common/sgmii_riser.h"
#if defined(CONFIG_DDR_ECC) && !defined(CONFIG_ECC_INIT_VIA_DDRCONTROLLER)
extern void ddr_enable_ecc(unsigned int dram_size);
return val;
}
+int board_eth_init(bd_t *bis)
+{
+#ifdef CONFIG_TSEC_ENET
+ struct tsec_info_struct tsec_info[2];
+ volatile ccsr_gur_t *gur = (void *)(CFG_MPC85xx_GUTS_ADDR);
+ uint io_sel = (gur->pordevsr & MPC85xx_PORDEVSR_IO_SEL) >> 19;
+ int num = 0;
+
+#ifdef CONFIG_TSEC1
+ SET_STD_TSEC_INFO(tsec_info[num], 1);
+ if (!(gur->pordevsr & MPC85xx_PORDEVSR_SGMII1_DIS))
+ tsec_info[num].flags |= TSEC_SGMII;
+ num++;
+#endif
+#ifdef CONFIG_TSEC3
+ SET_STD_TSEC_INFO(tsec_info[num], 3);
+ if (!(gur->pordevsr & MPC85xx_PORDEVSR_SGMII3_DIS))
+ tsec_info[num].flags |= TSEC_SGMII;
+ num++;
+#endif
+
+ if (!num) {
+ printf("No TSECs initialized\n");
+
+ return 0;
+ }
+
+ if (io_sel & 1)
+ fsl_sgmii_riser_init(tsec_info, num);
+
+
+ tsec_eth_init(bis, tsec_info, num);
+#endif
+ return pci_eth_init(bis);
+}
+
#if defined(CONFIG_OF_BOARD_SETUP)
void
#include <libfdt.h>
#include <fdt_support.h>
#include <spd_sdram.h>
+#include <netdev.h>
#include "../common/pixis.h"
return val;
}
-extern int uli526x_initialize(bd_t *);
-
int board_eth_init(bd_t *bis)
{
-#if defined(CONFIG_ULI526)
- uli526x_initialize(bis);
-#endif
- return 0;
+ return pci_eth_init(bis);
}
#include <asm/io.h>
#include <libfdt.h>
#include <fdt_support.h>
+#include <netdev.h>
#include "../common/pixis.h"
return val;
}
+
+int board_eth_init(bd_t *bis)
+{
+ /* Initialize TSECs */
+ cpu_eth_init(bis);
+ return pci_eth_init(bis);
+}
#include <common.h>
#include <mpc824x.h>
#include <pci.h>
+#include <netdev.h>
int checkboard (void)
{
{
pci_mpc824x_init(&hose);
}
+
+int board_eth_init(bd_t *bis)
+{
+ return pci_eth_init(bis);
+}
#include <pci.h>
#include <asm/processor.h>
#include <libfdt.h>
+#include <netdev.h>
#if defined(CONFIG_LITE5200B)
#include "mt46v32m16.h"
ft_cpu_setup(blob, bd);
}
#endif
+
+int board_eth_init(bd_t *bis)
+{
+ cpu_eth_init(bis); /* Built in FEC comes first */
+ return pci_eth_init(bis);
+}
#include <common.h>
#include <command.h>
+#include <netdev.h>
#include <asm/addrspace.h>
#include <asm/inca-ip.h>
#include <asm/io.h>
return 0;
}
+
+#if defined(CONFIG_INCA_IP_SWITCH)
+int board_eth_init(bd_t *bis)
+{
+ return inca_switch_initialize(bis);
+}
+#endif
#include <pci.h>
#endif
+#include <netdev.h>
+
DECLARE_GLOBAL_DATA_PTR;
void flash__init (void);
{
return CFG_HZ_CLOCK/div_clock;
}
+
+int board_eth_init(bd_t *bis)
+{
+ return pci_eth_init(bis);
+}
#include <common.h>
#include <command.h>
#include <malloc.h>
+#include <netdev.h>
#include <asm/arch/ixp425.h>
DECLARE_GLOBAL_DATA_PTR;
pci_ixp_init(&hose);
}
#endif
+
+int board_eth_init(bd_t *bis)
+{
+ return pci_eth_init(bis);
+}
#include <mpc824x.h>
#include <asm/io.h>
#include <ns16550.h>
+#include <netdev.h>
#ifdef CONFIG_PCI
#include <pci.h>
out_8((volatile u8*)UART_DCR, 1);
return 0;
}
+
+int board_eth_init(bd_t *bis)
+{
+ return pci_eth_init(bis);
+}
#include <fpga.h>
#include <environment.h>
#include <fdt_support.h>
+#include <netdev.h>
#include <asm/io.h>
#include "fpga.h"
#include "mvbc_p.h"
ft_cpu_setup(blob, bd);
fdt_fixup_memory(blob, (u64)bd->bi_memstart, (u64)bd->bi_memsize);
}
+
+int board_eth_init(bd_t *bis)
+{
+ cpu_eth_init(bis); /* Built in FEC comes first */
+ return pci_eth_init(bis);
+}
* MA 02111-1307 USA
*/
#include <common.h>
+#include <netdev.h>
#include <asm/io.h>
#include <asm/sdram.h>
#endif /* CONFIG_ATMEL_SPI */
#ifdef CONFIG_CMD_NET
-extern int macb_eth_initialize(int id, void *regs, unsigned int phy_addr);
-
int board_eth_init(bd_t *bi)
{
macb_eth_initialize(0, (void *)MACB0_BASE, bi->bi_phy_id[0]);
#include "../cpu/at32ap/at32ap700x/sm.h"
#include <common.h>
+#include <netdev.h>
#include <asm/io.h>
#include <asm/sdram.h>
.refresh_period = (781 * (SDRAMC_BUS_HZ / 1000)) / 100000,
};
-extern int macb_eth_initialize(int id, void *regs, unsigned int phy_addr);
-
#ifdef CONFIG_CMD_NET
int board_eth_init(bd_t *bis)
{
#include <common.h>
#include <mpc824x.h>
+#include <netdev.h>
#include <asm/processor.h>
#include "mousse.h"
get_tod ();
return 0;
}
+
+int board_eth_init(bd_t *bis)
+{
+ return pci_eth_init(bis);
+}
*/
#include <common.h>
+#include <netdev.h>
#include <asm/processor.h>
#include <asm/mmu.h>
#include <asm/immap_85xx.h>
return (CFG_SDRAM_SIZE * 1024 * 1024);
}
#endif /* !defined(CONFIG_SPD_EEPROM) */
+
+int board_eth_init(bd_t *bis)
+{
+ /*
+ * This board either has PCI NICs or uses the CPU's TSECs
+ * pci_eth_init() will return 0 if no NICs found, so in that case
+ * returning -1 will force cpu_eth_init() to be called.
+ */
+ int num = pci_eth_init(bis);
+ return (num <= 0 ? -1 : num);
+}
#include <common.h>
#include <mpc824x.h>
#include <pci.h>
+#include <netdev.h>
int checkboard (void)
{
{
pci_mpc824x_init(&hose);
}
+
+int board_eth_init(bd_t *bis)
+{
+ return pci_eth_init(bis);
+}
#include <mpc824x.h>
#include <asm/io.h>
#include <ns16550.h>
+#include <netdev.h>
#ifdef CONFIG_PCI
#include <pci.h>
{
pci_mpc824x_init (&hose);
}
+
+int board_eth_init(bd_t *bis)
+{
+ return pci_eth_init(bis);
+}
#endif
#include <common.h>
#include <mpc5xxx.h>
#include <pci.h>
+#include <netdev.h>
#define SDRAM_MODE 0x00CD0000
#define SDRAM_CONTROL 0x504F0000
pci_mpc5xxx_init(&hose);
}
#endif
+
+int board_eth_init(bd_t *bis)
+{
+ cpu_eth_init(bis); /* Built in FEC comes first */
+ return pci_eth_init(bis);
+}
#include <mpc824x.h>
#include <pci.h>
#include <i2c.h>
+#include <netdev.h>
DECLARE_GLOBAL_DATA_PTR;
#endif
return (0);
}
+
+int board_eth_init(bd_t *bis)
+{
+ return pci_eth_init(bis);
+}
#include <linux/mtd/doc2000.h>
#include <watchdog.h>
#include <pci.h>
+#include <netdev.h>
#include "hardware.h"
#include "pcippc2.h"
#endif
#endif /* CONFIG_WATCHDOG */
+
+int board_eth_init(bd_t *bis)
+{
+ return pci_eth_init(bis);
+}
#include <common.h>
#include <mpc5xxx.h>
#include <pci.h>
+#include <netdev.h>
#if defined(CONFIG_MPC5200_DDR)
#include "mt46v16m16-75.h"
doc_probe (CFG_DOC_BASE);
}
#endif
+
+int board_eth_init(bd_t *bis)
+{
+ cpu_eth_init(bis); /* Built in FEC comes first */
+ return pci_eth_init(bis);
+}
#include <ioports.h>
#include <mpc8260.h>
#include <pci.h>
+#include <netdev.h>
/*
* I/O Port configuration table
pci_mpc8250_init(&hose);
}
#endif
+
+int board_eth_init(bd_t *bis)
+{
+ return pci_eth_init(bis);
+}
#include <ioports.h>
#include <mpc8260.h>
#include <pci.h>
+#include <netdev.h>
/*
* I/O Port configuration table
pci_mpc8250_init(&hose);
}
#endif
+
+int board_eth_init(bd_t *bis)
+{
+ return pci_eth_init(bis);
+}
#include <common.h>
#include <pci.h>
+#include <netdev.h>
#include <asm/processor.h>
#include <asm/mmu.h>
#include <asm/immap_85xx.h>
pci_mpc85xx_init(&hose);
#endif /* CONFIG_PCI */
}
+
+int board_eth_init(bd_t *bis)
+{
+ cpu_eth_init(bis); /* Intialize TSECs first */
+ return pci_eth_init(bis);
+}
#include <ioports.h>
#include <spd_sdram.h>
#include <miiphy.h>
+#include <netdev.h>
#if defined(CONFIG_DDR_ECC)
extern void ddr_enable_ecc(unsigned int dram_size);
pci_mpc85xx_init(&hose);
#endif /* CONFIG_PCI */
}
+
+int board_eth_init(bd_t *bis)
+{
+ cpu_eth_init(bis); /* Intialize TSECs first */
+ return pci_eth_init(bis);
+}
#include <common.h>
#include <mpc824x.h>
#include <pci.h>
+#include <netdev.h>
#include "pn62.h"
mac[0], mac[1], mac[2],
mac[3], mac[4], mac[5]);
}
+
+int board_eth_init(bd_t *bis)
+{
+ return pci_eth_init(bis);
+}
#include <common.h>
#include <command.h>
+#include <netdev.h>
/* Define some MPC107 (memory controller) registers */
/* Should never get here */
while(1);
}
+
+int board_eth_init(bd_t *bis)
+{
+ return pci_eth_init(bis);
+}
#include <common.h>
#include <command.h>
+#include <netdev.h>
#include <asm/inca-ip.h>
#include <asm/regdef.h>
#include <asm/mipsregs.h>
start += CFG_CACHELINE_SIZE;
}
}
+
+#ifdef CONFIG_PLB2800_ETHER
+int board_eth_init(bd_t *bis)
+{
+ return plb2800_eth_initialize(bis);
+}
+#endif
+
{
pci_sh7751_init(&hose);
}
+
+int board_eth_init(bd_t *bis)
+{
+ return pci_eth_init(bis);
+}
#include <asm/processor.h>
#include <asm/io.h>
#include <asm/pci.h>
+#include <netdev.h>
#include "r7780mp.h"
int checkboard(void)
{
pci_sh7780_init(&hose);
}
+
+int board_eth_init(bd_t *bis)
+{
+ return pci_eth_init(bis);
+}
#include <common.h>
#include <mpc824x.h>
#include <pci.h>
+#include <netdev.h>
int checkboard (void)
{
{
pci_mpc824x_init(&hose);
}
+
+int board_eth_init(bd_t *bis)
+{
+ return pci_eth_init(bis);
+}
#include <mpc824x.h>
#include <asm/processor.h>
#include <pci.h>
+#include <netdev.h>
DECLARE_GLOBAL_DATA_PTR;
return (0);
}
#endif /* CONFIG_MISC_INIT_R */
+
+int board_eth_init(bd_t *bis)
+{
+ return pci_eth_init(bis);
+}
#include <pci.h>
#include <i2c.h>
#include <malloc.h>
+#include <netdev.h>
#undef writel
#undef writeb
hose.config_table = pci_solidcard3_config_table;
pci_405gp_init(&hose);
}
+
+int board_eth_init(bd_t *bis)
+{
+ return pci_eth_init(bis);
+}
#include <asm/ic/sc520.h>
#include <asm/ic/ali512x.h>
#include <spi.h>
+#include <netdev.h>
DECLARE_GLOBAL_DATA_PTR;
#endif
return res;
}
+
+int board_eth_init(bd_t *bis)
+{
+ return pci_eth_init(bis);
+}
#include <common.h>
#include <pci.h>
#include <ssi.h>
+#include <netdev.h>
#include <asm/io.h>
#include <asm/pci.h>
#include <asm/ic/sc520.h>
spi_eeprom_write(1, offset, buffer, len) :
mw_eeprom_write(1, offset, buffer, len);
}
+
+int board_eth_init(bd_t *bis)
+{
+ return pci_eth_init(bis);
+}
#include <common.h>
#include <mpc824x.h>
#include <pci.h>
+#include <netdev.h>
int checkboard (void)
{
pci_mpc824x_init(&hose);
}
-extern int skge_initialize(bd_t *bis);
-
int board_eth_init(bd_t *bis)
{
int rc = 0;
#include <asm/processor.h>
#include <asm/mmu.h>
#include <pci.h>
+#include <netdev.h>
phys_size_t initdram (int board_type)
{
pci_mpc8220_init (&hose);
#endif /* CONFIG_PCI */
}
+
+int board_eth_init(bd_t *bis)
+{
+ return pci_eth_init(bis);
+}
#include <asm/io.h>
#include <spd_sdram.h>
#include <miiphy.h>
+#include <netdev.h>
long int fixed_sdram (void);
pci_mpc85xx_init(hose);
#endif /* CONFIG_PCI */
}
+
+int board_eth_init(bd_t *bis)
+{
+ cpu_eth_init(bis); /* Initialize TSECs first */
+ return pci_eth_init(bis);
+}
+
return 0;
}
+
+int board_eth_init(bd_t *bis)
+{
+ return pci_eth_init(bis);
+}
#include <common.h>
#include <mpc5xxx.h>
#include <pci.h>
+#include <netdev.h>
#include "sdram.h"
}
#endif /* CONFIG_VIDEO_SED13806 */
+
+int board_eth_init(bd_t *bis)
+{
+ cpu_eth_init(bis); /* Built in FEC comes first */
+ return pci_eth_init(bis);
+}
#include <pci.h>
#include <asm/processor.h>
#include <libfdt.h>
+#include <netdev.h>
#ifdef CONFIG_VIDEO_SM501
#include <sm501.h>
fdt_fixup_memory(blob, (u64)bd->bi_memstart, (u64)bd->bi_memsize);
}
#endif /* defined(CONFIG_OF_LIBFDT) && defined(CONFIG_OF_BOARD_SETUP) */
+
+int board_eth_init(bd_t *bis)
+{
+ cpu_eth_init(bis); /* Built in FEC comes first */
+ return pci_eth_init(bis);
+}
#include <mpc8260.h>
#include <command.h>
+#include <netdev.h>
#ifdef CONFIG_PCI
#include <pci.h>
#include <asm/m8260_pci.h>
pci_mpc8250_init(&hose);
}
#endif
+
+int board_eth_init(bd_t *bis)
+{
+ return pci_eth_init(bis);
+}
#include <flash.h>
#include <libfdt.h>
#include <fdt_support.h>
+#include <netdev.h>
DECLARE_GLOBAL_DATA_PTR;
return (0);
}
#endif /* CONFIG_BOARD_EARLY_INIT_R */
+
+int board_eth_init(bd_t *bis)
+{
+ cpu_eth_init(bis); /* Intialize TSECs first */
+ return pci_eth_init(bis);
+}
#include <asm/io.h>
#include <asm/mmu.h>
#include <pci.h>
+#include <netdev.h>
#define SAVE_SZ 32
icache_enable();
}
+
+int board_eth_init(bd_t *bis)
+{
+ return pci_eth_init(bis);
+}
LIB = $(obj)lib$(SOC).a
-COBJS-y += ether.o
COBJS-y += timer.o
COBJS-$(CONFIG_HAS_DATAFLASH) +=spi.o
COBJS-y += usb.o
+++ /dev/null
-/*
- * (C) Copyright 2007-2008
- * Stelian Pop <stelian.pop@leadtechdesign.com>
- * Lead Tech Design <www.leadtechdesign.com>
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-
-#include <common.h>
-#include <asm/arch/hardware.h>
-
-extern int macb_eth_initialize(int id, void *regs, unsigned int phy_addr);
-
-#if defined(CONFIG_MACB) && defined(CONFIG_CMD_NET)
-void at91sam9_eth_initialize(bd_t *bi)
-{
- macb_eth_initialize(0, (void *)AT91_BASE_EMAC, 0x00);
-}
-#endif
#include <common.h>
#include <watchdog.h>
#include <command.h>
+#include <netdev.h>
DECLARE_GLOBAL_DATA_PTR;
/* ------------------------------------------------------------------------- */
-extern int greth_initialize(bd_t *bis);
-
#ifdef CONFIG_GRETH
int cpu_eth_init(bd_t *bis)
{
#include <common.h>
#include <watchdog.h>
#include <command.h>
+#include <netdev.h>
#include <asm/io.h>
#include <asm/processor.h>
}
/* ------------------------------------------------------------------------- */
-extern int greth_initialize(bd_t *bis);
#ifdef CONFIG_GRETH
int cpu_eth_init(bd_t *bis)
#include <common.h>
#include <watchdog.h>
#include <command.h>
+#include <netdev.h>
#include <asm/immap.h>
* int board_eth_init(bd_t *bis)
*/
-extern int mcffec_initialize(bd_t*);
-
int cpu_eth_init(bd_t *bis)
{
return mcffec_initialize(bis);
#include <watchdog.h>
#include <command.h>
#include <asm/immap.h>
+#include <netdev.h>
#ifdef CONFIG_M5271
/*
* int board_eth_init(bd_t *bis)
*/
-extern int mcffec_initialize(bd_t*);
-
int cpu_eth_init(bd_t *bis)
{
return mcffec_initialize(bis);
#include <common.h>
#include <watchdog.h>
#include <command.h>
+#include <netdev.h>
#include <asm/immap.h>
* int board_eth_init(bd_t *bis)
*/
-extern int mcffec_initialize(bd_t*);
-
int cpu_eth_init(bd_t *bis)
{
return mcffec_initialize(bis);
#include <common.h>
#include <watchdog.h>
#include <command.h>
+#include <netdev.h>
#include <asm/immap.h>
* int board_eth_init(bd_t *bis)
*/
-extern int mcffec_initialize(bd_t*);
-
int cpu_eth_init(bd_t *bis)
{
return mcffec_initialize(bis);
#include <common.h>
#include <watchdog.h>
#include <command.h>
+#include <netdev.h>
#include <asm/immap.h>
* int board_eth_init(bd_t *bis)
*/
-extern int mcdmafec_initialize(bd_t *bis);
-extern int mcffec_initialize(bd_t*);
-
int cpu_eth_init(bd_t *bis)
{
#if defined(CONFIG_FSLDMAFEC)
#include <common.h>
#include <command.h>
#include <mpc512x.h>
+#include <netdev.h>
#include <asm/processor.h>
#if defined(CONFIG_OF_LIBFDT)
#endif
}
#endif
+
+#ifdef CONFIG_MPC512x_FEC
+/* Default initializations for FEC controllers. To override,
+ * create a board-specific function called:
+ * int board_eth_init(bd_t *bis)
+ */
+
+int cpu_eth_init(bd_t *bis)
+{
+ return mpc512x_fec_initialize(bis);
+}
+#endif
#include <watchdog.h>
#include <command.h>
#include <mpc5xxx.h>
+#include <netdev.h>
#include <asm/io.h>
#include <asm/processor.h>
return (*save_addr & 0x0000ffff);
}
#endif /* CONFIG_BOOTCOUNT_LIMIT */
+
+#ifdef CONFIG_MPC5xxx_FEC
+/* Default initializations for FEC controllers. To override,
+ * create a board-specific function called:
+ * int board_eth_init(bd_t *bis)
+ */
+
+int cpu_eth_init(bd_t *bis)
+{
+ return mpc5xxx_fec_initialize(bis);
+}
+#endif
#include <mpc83xx.h>
#include <asm/processor.h>
#include <libfdt.h>
+#include <tsec.h>
DECLARE_GLOBAL_DATA_PTR;
}
#endif /*CONFIG_DDR_ECC*/
-#ifdef CONFIG_TSEC_ENET
-/* Default initializations for TSEC controllers. To override,
- * create a board-specific function called:
- * int board_eth_init(bd_t *bis)
+/*
+ * Initializes on-chip ethernet controllers.
+ * to override, implement board_eth_init()
*/
-
-extern int tsec_initialize(bd_t * bis, int index, char *devname);
-
int cpu_eth_init(bd_t *bis)
{
-#if defined(CONFIG_TSEC1)
- tsec_initialize(bis, 0, CONFIG_TSEC1_NAME);
-#endif
-#if defined(CONFIG_TSEC2)
- tsec_initialize(bis, 1, CONFIG_TSEC2_NAME);
+#if defined(CONFIG_TSEC_ENET)
+ tsec_standard_init(bis);
#endif
+
return 0;
}
-#endif
* MA 02111-1307 USA
*/
+#include <config.h>
#include <common.h>
#include <watchdog.h>
#include <command.h>
+#include <tsec.h>
#include <asm/cache.h>
#include <asm/io.h>
return dma_check();
}
#endif
+
/*
* Configures a UPM. Currently, the loop fields in MxMR (RLF, WLF and TLF)
* are hardcoded as "1"."size" is the number or entries, not a sizeof.
out_be32(mxmr, loopval); /* OP_NORMAL */
}
-#if defined(CONFIG_TSEC_ENET) || defined(CONFIGMPC85XX_FEC)
-/* Default initializations for TSEC controllers. To override,
- * create a board-specific function called:
- * int board_eth_init(bd_t *bis)
- */
-
-extern int tsec_initialize(bd_t * bis, int index, char *devname);
+/*
+ * Initializes on-chip ethernet controllers.
+ * to override, implement board_eth_init()
+ */
int cpu_eth_init(bd_t *bis)
{
-#if defined(CONFIG_TSEC1)
- tsec_initialize(bis, 0, CONFIG_TSEC1_NAME);
-#endif
-#if defined(CONFIG_TSEC2)
- tsec_initialize(bis, 1, CONFIG_TSEC2_NAME);
-#endif
-#if defined(CONFIG_MPC85XX_FEC)
- tsec_initialize(bis, 2, CONFIG_MPC85XX_FEC_NAME);
-#else
-#if defined(CONFIG_TSEC3)
- tsec_initialize(bis, 2, CONFIG_TSEC3_NAME);
-#endif
-#if defined(CONFIG_TSEC4)
- tsec_initialize(bis, 3, CONFIG_TSEC4_NAME);
-#endif
+#if defined(CONFIG_TSEC_ENET) || defined(CONFIG_MPC85xx_FEC)
+ tsec_standard_init(bis);
#endif
+
return 0;
}
-#endif
#include <asm/cache.h>
#include <asm/mmu.h>
#include <mpc86xx.h>
+#include <tsec.h>
#include <asm/fsl_law.h>
}
-#ifdef CONFIG_TSEC_ENET
-/* Default initializations for TSEC controllers. To override,
- * create a board-specific function called:
- * int board_eth_init(bd_t *bis)
+/*
+ * Initializes on-chip ethernet controllers.
+ * to override, implement board_eth_init()
*/
-
-extern int tsec_initialize(bd_t * bis, int index, char *devname);
-
int cpu_eth_init(bd_t *bis)
{
-#if defined(CONFIG_TSEC1)
- tsec_initialize(bis, 0, CONFIG_TSEC1_NAME);
-#endif
-#if defined(CONFIG_TSEC2)
- tsec_initialize(bis, 1, CONFIG_TSEC2_NAME);
-#endif
-#if defined(CONFIG_TSEC3)
- tsec_initialize(bis, 2, CONFIG_TSEC3_NAME);
-#endif
-#if defined(CONFIG_TSEC4)
- tsec_initialize(bis, 3, CONFIG_TSEC4_NAME);
+#if defined(CONFIG_TSEC_ENET)
+ tsec_standard_init(bis);
#endif
+
return 0;
}
-#endif /* CONFIG_TSEC_ENET */
#include <common.h>
#include <config.h>
#include <net.h>
+#include <netdev.h>
#include <command.h>
#include <malloc.h>
#include <common.h>
#include <malloc.h>
#include <net.h>
+#include <netdev.h>
#include <pci.h>
#undef DEBUG_SROM
card_number++;
}
- return 1;
+ return card_number;
}
#include <common.h>
#include <malloc.h>
#include <net.h>
+#include <netdev.h>
#include <asm/io.h>
#include <pci.h>
#include <common.h>
#include <malloc.h>
#include <net.h>
+#include <netdev.h>
#include <asm/io.h>
#include <pci.h>
#include <miiphy.h>
#include <common.h>
#include <command.h>
#include <net.h>
+#include <netdev.h>
#include <malloc.h>
#include <asm/processor.h>
#include <ambapp.h>
#include <malloc.h>
#include <net.h>
+#include <netdev.h>
#include <asm/inca-ip.h>
#include <asm/addrspace.h>
printf("Leaving inca_switch_initialize()\n");
#endif
- return 1;
+ return 0;
}
*/
#include <net.h>
+#include <netdev.h>
#include <malloc.h>
#include <linux/mii.h>
#include <command.h>
#include <net.h>
+#include <netdev.h>
#include <miiphy.h>
#undef ET_DEBUG
#include <mpc512x.h>
#include <malloc.h>
#include <net.h>
+#include <netdev.h>
#include <miiphy.h>
#include "mpc512x_fec.h"
#include <mpc5xxx_sdma.h>
#include <malloc.h>
#include <net.h>
+#include <netdev.h>
#include <miiphy.h>
#include "mpc5xxx_fec.h"
#include <common.h>
#include <malloc.h>
#include <net.h>
+#include <netdev.h>
#include <asm/io.h>
#include <pci.h>
#include <common.h>
#include <malloc.h>
#include <net.h>
+#include <netdev.h>
#include <asm/io.h>
#include <pci.h>
#include <common.h>
#include <malloc.h>
#include <net.h>
+#include <netdev.h>
#include <asm/io.h>
#include <pci.h>
#include <common.h>
#include <malloc.h>
#include <net.h>
+#include <netdev.h>
#include <asm/addrspace.h>
if (!(dev = (struct eth_device *) malloc (sizeof *dev)))
{
printf("Failed to allocate memory\n");
- return 0;
+ return -1;
}
memset(dev, 0, sizeof(*dev));
printf("Leaving plb2800_eth_initialize()\n");
#endif
- return 1;
+ return 0;
}
static int plb2800_eth_init(struct eth_device *dev, bd_t * bis)
#include <common.h>
#include <malloc.h>
#include <net.h>
+#include <netdev.h>
#include <asm/io.h>
#include <pci.h>
#include <common.h>
#include <malloc.h>
#include <net.h>
+#include <netdev.h>
#include <asm/io.h>
#include <pci.h>
*/
#include <common.h>
+#include <netdev.h>
#include "h/skdrv1st.h"
#include "h/skdrv2nd.h"
#error "SMC911X: undefined bus width"
#endif /* CONFIG_DRIVER_SMC911X_16_BIT */
+u32 pkt_data_pull(u32 addr) \
+ __attribute__ ((weak, alias ("reg_read")));
+void pkt_data_push(u32 addr, u32 val) \
+ __attribute__ ((weak, alias ("reg_write")));
+
#define mdelay(n) udelay((n)*1000)
/* Below are the register offsets and bit definitions
tmplen = (length + 3) / 4;
while (tmplen--)
- reg_write(TX_DATA_FIFO, *data++);
+ pkt_data_push(TX_DATA_FIFO, *data++);
/* wait for transmission */
while (!((reg_read(TX_FIFO_INF) & TX_FIFO_INF_TSUSED) >> 16));
tmplen = (pktlen + 2+ 3) / 4;
while (tmplen--)
- *data++ = reg_read(RX_DATA_FIFO);
+ *data++ = pkt_data_pull(RX_DATA_FIFO);
if (status & RX_STS_ES)
printf(DRIVERNAME
#include <malloc.h>
#include <net.h>
#include <command.h>
+#include <tsec.h>
-#include "tsec.h"
#include "miiphy.h"
DECLARE_GLOBAL_DATA_PTR;
rxbd8_t rxbd[PKTBUFSRX];
} RTXBD;
-struct tsec_info_struct {
- unsigned int phyaddr;
- u32 flags;
- unsigned int phyregidx;
-};
-
-/* The tsec_info structure contains 3 values which the
- * driver uses to determine how to operate a given ethernet
- * device. The information needed is:
- * phyaddr - The address of the PHY which is attached to
- * the given device.
- *
- * flags - This variable indicates whether the device
- * supports gigabit speed ethernet, and whether it should be
- * in reduced mode.
- *
- * phyregidx - This variable specifies which ethernet device
- * controls the MII Management registers which are connected
- * to the PHY. For now, only TSEC1 (index 0) has
- * access to the PHYs, so all of the entries have "0".
- *
- * The values specified in the table are taken from the board's
- * config file in include/configs/. When implementing a new
- * board with ethernet capability, it is necessary to define:
- * TSECn_PHY_ADDR
- * TSECn_PHYIDX
- *
- * for n = 1,2,3, etc. And for FEC:
- * FEC_PHY_ADDR
- * FEC_PHYIDX
- */
-static struct tsec_info_struct tsec_info[] = {
-#ifdef CONFIG_TSEC1
- {TSEC1_PHY_ADDR, TSEC1_FLAGS, TSEC1_PHYIDX},
-#else
- {0, 0, 0},
-#endif
-#ifdef CONFIG_TSEC2
- {TSEC2_PHY_ADDR, TSEC2_FLAGS, TSEC2_PHYIDX},
-#else
- {0, 0, 0},
-#endif
-#ifdef CONFIG_MPC85XX_FEC
- {FEC_PHY_ADDR, FEC_FLAGS, FEC_PHYIDX},
-#else
-#ifdef CONFIG_TSEC3
- {TSEC3_PHY_ADDR, TSEC3_FLAGS, TSEC3_PHYIDX},
-#else
- {0, 0, 0},
-#endif
-#ifdef CONFIG_TSEC4
- {TSEC4_PHY_ADDR, TSEC4_FLAGS, TSEC4_PHYIDX},
-#else
- {0, 0, 0},
-#endif /* CONFIG_TSEC4 */
-#endif /* CONFIG_MPC85XX_FEC */
-};
-
-#define MAXCONTROLLERS (4)
+#define MAXCONTROLLERS (8)
static int relocated = 0;
static struct tsec_private *privlist[MAXCONTROLLERS];
+static int num_tsecs = 0;
#ifdef __GNUC__
static RTXBD rtx __attribute__ ((aligned(8)));
static int tsec_mcast_addr (struct eth_device *dev, u8 mcast_mac, u8 set);
#endif
+/* Default initializations for TSEC controllers. */
+
+static struct tsec_info_struct tsec_info[] = {
+#ifdef CONFIG_TSEC1
+ STD_TSEC_INFO(1), /* TSEC1 */
+#endif
+#ifdef CONFIG_TSEC2
+ STD_TSEC_INFO(2), /* TSEC2 */
+#endif
+#ifdef CONFIG_MPC85XX_FEC
+ {
+ .regs = (tsec_t *)(TSEC_BASE_ADDR + 0x2000),
+ .miiregs = (tsec_t *)(TSEC_BASE_ADDR),
+ .devname = CONFIG_MPC85XX_FEC_NAME,
+ .phyaddr = FEC_PHY_ADDR,
+ .flags = FEC_FLAGS
+ }, /* FEC */
+#endif
+#ifdef CONFIG_TSEC3
+ STD_TSEC_INFO(3), /* TSEC3 */
+#endif
+#ifdef CONFIG_TSEC4
+ STD_TSEC_INFO(4), /* TSEC4 */
+#endif
+};
+
+int tsec_eth_init(bd_t *bis, struct tsec_info_struct *tsecs, int num)
+{
+ int i;
+
+ for (i = 0; i < num; i++)
+ tsec_initialize(bis, &tsecs[i]);
+
+ return 0;
+}
+
+int tsec_standard_init(bd_t *bis)
+{
+ return tsec_eth_init(bis, tsec_info, ARRAY_SIZE(tsec_info));
+}
+
/* Initialize device structure. Returns success if PHY
* initialization succeeded (i.e. if it recognizes the PHY)
*/
-int tsec_initialize(bd_t * bis, int index, char *devname)
+int tsec_initialize(bd_t * bis, struct tsec_info_struct *tsec_info)
{
struct eth_device *dev;
int i;
if (NULL == priv)
return 0;
- privlist[index] = priv;
- priv->regs = (volatile tsec_t *)(TSEC_BASE_ADDR + index * TSEC_SIZE);
- priv->phyregs = (volatile tsec_t *)(TSEC_BASE_ADDR +
- tsec_info[index].phyregidx *
- TSEC_SIZE);
+ privlist[num_tsecs++] = priv;
+ priv->regs = tsec_info->regs;
+ priv->phyregs = tsec_info->miiregs;
- priv->phyaddr = tsec_info[index].phyaddr;
- priv->flags = tsec_info[index].flags;
+ priv->phyaddr = tsec_info->phyaddr;
+ priv->flags = tsec_info->flags;
- sprintf(dev->name, devname);
+ sprintf(dev->name, tsec_info->devname);
dev->iobase = 0;
dev->priv = priv;
dev->init = tsec_init;
/* If there's no link, fail */
return (priv->link ? 0 : -1);
-
}
-/* Write value to the device's PHY through the registers
- * specified in priv, modifying the register specified in regnum.
- * It will wait for the write to be done (or for a timeout to
- * expire) before exiting
- */
-void write_any_phy_reg(struct tsec_private *priv, uint phyid, uint regnum, uint value)
+/* Writes the given phy's reg with value, using the specified MDIO regs */
+static void tsec_local_mdio_write(volatile tsec_t *phyregs, uint addr,
+ uint reg, uint value)
{
- volatile tsec_t *regbase = priv->phyregs;
int timeout = 1000000;
- regbase->miimadd = (phyid << 8) | regnum;
- regbase->miimcon = value;
+ phyregs->miimadd = (addr << 8) | reg;
+ phyregs->miimcon = value;
asm("sync");
timeout = 1000000;
- while ((regbase->miimind & MIIMIND_BUSY) && timeout--) ;
+ while ((phyregs->miimind & MIIMIND_BUSY) && timeout--) ;
}
-/* #define to provide old write_phy_reg functionality without duplicating code */
-#define write_phy_reg(priv, regnum, value) write_any_phy_reg(priv,priv->phyaddr,regnum,value)
+
+/* Provide the default behavior of writing the PHY of this ethernet device */
+#define write_phy_reg(priv, regnum, value) tsec_local_mdio_write(priv->phyregs,priv->phyaddr,regnum,value)
/* Reads register regnum on the device's PHY through the
- * registers specified in priv. It lowers and raises the read
+ * specified registers. It lowers and raises the read
* command, and waits for the data to become valid (miimind
* notvalid bit cleared), and the bus to cease activity (miimind
* busy bit cleared), and then returns the value
*/
-uint read_any_phy_reg(struct tsec_private *priv, uint phyid, uint regnum)
+uint tsec_local_mdio_read(volatile tsec_t *phyregs, uint phyid, uint regnum)
{
uint value;
- volatile tsec_t *regbase = priv->phyregs;
/* Put the address of the phy, and the register
* number into MIIMADD */
- regbase->miimadd = (phyid << 8) | regnum;
+ phyregs->miimadd = (phyid << 8) | regnum;
/* Clear the command register, and wait */
- regbase->miimcom = 0;
+ phyregs->miimcom = 0;
asm("sync");
/* Initiate a read command, and wait */
- regbase->miimcom = MIIM_READ_COMMAND;
+ phyregs->miimcom = MIIM_READ_COMMAND;
asm("sync");
/* Wait for the the indication that the read is done */
- while ((regbase->miimind & (MIIMIND_NOTVALID | MIIMIND_BUSY))) ;
+ while ((phyregs->miimind & (MIIMIND_NOTVALID | MIIMIND_BUSY))) ;
/* Grab the value read from the PHY */
- value = regbase->miimstat;
+ value = phyregs->miimstat;
return value;
}
/* #define to provide old read_phy_reg functionality without duplicating code */
-#define read_phy_reg(priv,regnum) read_any_phy_reg(priv,priv->phyaddr,regnum)
+#define read_phy_reg(priv,regnum) tsec_local_mdio_read(priv->phyregs,priv->phyaddr,regnum)
+
+#define TBIANA_SETTINGS ( \
+ TBIANA_ASYMMETRIC_PAUSE \
+ | TBIANA_SYMMETRIC_PAUSE \
+ | TBIANA_FULL_DUPLEX \
+ )
+
+#define TBICR_SETTINGS ( \
+ TBICR_PHY_RESET \
+ | TBICR_ANEG_ENABLE \
+ | TBICR_FULL_DUPLEX \
+ | TBICR_SPEED1_SET \
+ )
+/* Configure the TBI for SGMII operation */
+static void tsec_configure_serdes(struct tsec_private *priv)
+{
+ tsec_local_mdio_write(priv->phyregs, CFG_TBIPA_VALUE, TBI_ANA,
+ TBIANA_SETTINGS);
+ tsec_local_mdio_write(priv->phyregs, CFG_TBIPA_VALUE, TBI_TBICON,
+ TBICON_CLK_SELECT);
+ tsec_local_mdio_write(priv->phyregs, CFG_TBIPA_VALUE, TBI_CR,
+ TBICR_SETTINGS);
+}
/* Discover which PHY is attached to the device, and configure it
* properly. If the PHY is not recognized, then return 0
{
struct tsec_private *priv = (struct tsec_private *)dev->priv;
struct phy_info *curphy;
- volatile tsec_t *regs = (volatile tsec_t *)(TSEC_BASE_ADDR);
+ volatile tsec_t *phyregs = priv->phyregs;
+ volatile tsec_t *regs = priv->regs;
/* Assign a Physical address to the TBI */
regs->tbipa = CFG_TBIPA_VALUE;
- regs = (volatile tsec_t *)(TSEC_BASE_ADDR + TSEC_SIZE);
- regs->tbipa = CFG_TBIPA_VALUE;
+ phyregs->tbipa = CFG_TBIPA_VALUE;
asm("sync");
/* Reset MII (due to new addresses) */
return 0;
}
+ if (regs->ecntrl & ECNTRL_SGMII_MODE)
+ tsec_configure_serdes(priv);
+
priv->phyinfo = curphy;
phy_run_commands(priv, priv->phyinfo->config);
},
};
+/*
+ * Since to access LED register we need do switch the page, we
+ * do LED configuring in the miim_read-like function as follows
+ */
+uint mii_88E1121_set_led (uint mii_reg, struct tsec_private *priv)
+{
+ uint pg;
+
+ /* Switch the page to access the led register */
+ pg = read_phy_reg(priv, MIIM_88E1121_PHY_PAGE);
+ write_phy_reg(priv, MIIM_88E1121_PHY_PAGE, MIIM_88E1121_PHY_LED_PAGE);
+
+ /* Configure leds */
+ write_phy_reg(priv, MIIM_88E1121_PHY_LED_CTRL,
+ MIIM_88E1121_PHY_LED_DEF);
+
+ /* Restore the page pointer */
+ write_phy_reg(priv, MIIM_88E1121_PHY_PAGE, pg);
+ return 0;
+}
+
+struct phy_info phy_info_M88E1121R = {
+ 0x01410cb,
+ "Marvell 88E1121R",
+ 4,
+ (struct phy_cmd[]){ /* config */
+ /* Reset and configure the PHY */
+ {MIIM_CONTROL, MIIM_CONTROL_RESET, NULL},
+ {MIIM_GBIT_CONTROL, MIIM_GBIT_CONTROL_INIT, NULL},
+ {MIIM_ANAR, MIIM_ANAR_INIT, NULL},
+ /* Configure leds */
+ {MIIM_88E1121_PHY_LED_CTRL, miim_read,
+ &mii_88E1121_set_led},
+ {MIIM_CONTROL, MIIM_CONTROL_INIT, &mii_cr_init},
+ {miim_end,}
+ },
+ (struct phy_cmd[]){ /* startup */
+ /* Status is read once to clear old link state */
+ {MIIM_STATUS, miim_read, NULL},
+ {MIIM_STATUS, miim_read, &mii_parse_sr},
+ {MIIM_STATUS, miim_read, &mii_parse_link},
+ {miim_end,}
+ },
+ (struct phy_cmd[]){ /* shutdown */
+ {miim_end,}
+ },
+};
+
static unsigned int m88e1145_setmode(uint mii_reg, struct tsec_private *priv)
{
uint mii_data = read_phy_reg(priv, mii_reg);
&phy_info_M88E1011S,
&phy_info_M88E1111S,
&phy_info_M88E1118,
+ &phy_info_M88E1121R,
&phy_info_M88E1145,
&phy_info_M88E1149S,
&phy_info_dm9161,
return -1;
}
- ret = (unsigned short)read_any_phy_reg(priv, addr, reg);
+ ret = (unsigned short)tsec_local_mdio_read(priv->phyregs, addr, reg);
*value = ret;
return 0;
return -1;
}
- write_any_phy_reg(priv, addr, reg, value);
+ tsec_local_mdio_write(priv->phyregs, addr, reg, value);
return 0;
}
#include <common.h>
#include <malloc.h>
#include <net.h>
+#include <netdev.h>
#include <asm/cache.h>
#ifdef DEBUG
#include <common.h>
#include <malloc.h>
#include <net.h>
+#include <netdev.h>
#include <asm/io.h>
#include <pci.h>
#include <miiphy.h>
#define PIXIS_VSPEED1 0x18 /* VELA VSpeed 1 */
#define PIXIS_VCLKH 0x19 /* VELA VCLKH register */
#define PIXIS_VCLKL 0x1A /* VELA VCLKL register */
+#define PIXIS_VSPEED2 0x1d /* VELA VSpeed 2 */
#define CFG_PIXIS_VBOOT_MASK 0x40 /* Reset altbank mask*/
+#define PIXIS_VSPEED2_TSEC1SER 0x2
+#define PIXIS_VSPEED2_TSEC3SER 0x1
+#define PIXIS_VCFGEN1_TSEC1SER 0x20
+#define PIXIS_VCFGEN1_TSEC3SER 0x40
/* define to use L1 as initial stack */
#define CONFIG_TSEC3 1
#define CONFIG_TSEC3_NAME "eTSEC3"
+#define CONFIG_FSL_SGMII_RISER 1
+#define SGMII_RISER_PHY_OFFSET 0x1c
+
#define TSEC1_PHY_ADDR 0
#define TSEC3_PHY_ADDR 1
#define CONFIG_MII 1 /* MII PHY management */
#define CONFIG_PHY_ADDR 0 /* PHY address */
#define CONFIG_LXT971_NO_SLEEP 1 /* disable sleep mode in LXT971 */
-#define CONFIG_RESET_PHY_R 1 /* use reset_phy() to disable phy sleep mode */
+#define CONFIG_RESET_PHY_R 1 /* use reset_phy() */
#define CONFIG_PHY_CLK_FREQ EMAC_STACR_CLK_66MHZ /* 66 MHz OPB clock*/
#define CONFIG_CMD_MII
#define CONFIG_CMD_PING
#define CONFIG_CMD_EEPROM
+#define CONFIG_CMD_USB
+#define CONFIG_OF_LIBFDT
+#define CONFIG_OF_BOARD_SETUP
#define CONFIG_MAC_PARTITION
#define CONFIG_DOS_PARTITION
#define CFG_HZ 1000 /* decrementer freq: 1 ms ticks */
+#define CONFIG_CMDLINE_EDITING 1 /* add command line history */
#define CONFIG_ZERO_BOOTDELAY_CHECK /* check for keypress on bootdelay==0 */
#define CONFIG_BOOTDELAY 3 /* autoboot after 3 seconds */
#define CFG_RX_ETH_BUFFER 16 /* use 16 rx buffer on 405 emac */
-/*-----------------------------------------------------------------------
+/*
* NAND-FLASH stuff
- *-----------------------------------------------------------------------
*/
-#define CFG_NAND_BASE_LIST { CFG_NAND_BASE }
+#define CFG_NAND_BASE_LIST {CFG_NAND_BASE}
#define NAND_MAX_CHIPS 1
#define CFG_MAX_NAND_DEVICE 1 /* Max number of NAND devices */
#define NAND_BIG_DELAY_US 25
#define CFG_NAND_SKIP_BAD_DOT_I 1 /* ".i" read skips bad blocks */
#define CFG_NAND_QUIET 1
-/*-----------------------------------------------------------------------
+/*
* PCI stuff
- *-----------------------------------------------------------------------
*/
#define PCI_HOST_ADAPTER 0 /* configure as pci adapter */
#define PCI_HOST_FORCE 1 /* configure as pci host */
#define PCI_HOST_AUTO 2 /* detected via arbiter enable */
#define CONFIG_PCI /* include pci support */
-#define CONFIG_PCI_HOST PCI_HOST_HOST /* select pci host function */
+#define CONFIG_PCI_HOST PCI_HOST_FORCE /* select pci host function */
#define CONFIG_PCI_PNP /* do pci plug-and-play */
/* resource configuration */
#define CFG_PCI_PTM1PCI 0x00000000 /* Host: use this pci address */
#define CFG_PCI_PTM2LA 0xffc00000 /* point to flash */
#define CFG_PCI_PTM2MS 0xffc00001 /* 4MB, enable */
-#define CFG_PCI_PTM2PCI 0x04000000 /* Host: use this pci address */
+#define CFG_PCI_PTM2PCI 0x08000000 /* Host: use this pci address */
-/*-----------------------------------------------------------------------
+/*
* IDE/ATA stuff
- *-----------------------------------------------------------------------
*/
#undef CONFIG_IDE_8xx_DIRECT /* no pcmcia interface required */
#undef CONFIG_IDE_LED /* no led for ide supported */
#define CONFIG_IDE_RESET 1 /* reset for ide supported */
#define CFG_IDE_MAXBUS 1 /* max. 1 IDE busses */
-#define CFG_IDE_MAXDEVICE (CFG_IDE_MAXBUS*1) /* max. 1 drives per IDE bus */
+/* max. 1 drives per IDE bus */
+#define CFG_IDE_MAXDEVICE (CFG_IDE_MAXBUS*1)
#define CFG_ATA_BASE_ADDR 0xF0100000
#define CFG_ATA_IDE0_OFFSET 0x0000
-#define CFG_ATA_DATA_OFFSET 0x0000 /* Offset for data I/O */
-#define CFG_ATA_REG_OFFSET 0x0000 /* Offset for normal register accesses */
-#define CFG_ATA_ALT_OFFSET 0x0000 /* Offset for alternate registers */
+#define CFG_ATA_DATA_OFFSET 0x0000 /* Offset for data I/O */
+#define CFG_ATA_REG_OFFSET 0x0000 /* Offset for normal register access */
+#define CFG_ATA_ALT_OFFSET 0x0000 /* Offset for alternate registers */
/*
* For booting Linux, the board info and command line data
* have to be in the first 8 MB of memory, since this is
* the maximum mapped by the Linux kernel during initialization.
*/
-#define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */
-/*-----------------------------------------------------------------------
+#define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */
+
+/*
* FLASH organization
*/
-#define FLASH_BASE0_PRELIM 0xFFC00000 /* FLASH bank #0 */
+#define FLASH_BASE0_PRELIM 0xFFC00000 /* FLASH bank #0 */
-#define CFG_MAX_FLASH_BANKS 1 /* max number of memory banks */
-#define CFG_MAX_FLASH_SECT 256 /* max number of sectors on one chip */
+#define CFG_MAX_FLASH_BANKS 1 /* max number of memory banks */
+#define CFG_MAX_FLASH_SECT 256 /* max number of sectors on one chip */
-#define CFG_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */
-#define CFG_FLASH_WRITE_TOUT 1000 /* Timeout for Flash Write (in ms) */
+#define CFG_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */
+#define CFG_FLASH_WRITE_TOUT 1000 /* Timeout for Flash Write (in ms) */
-#define CFG_FLASH_WORD_SIZE unsigned short /* flash word size (width) */
-#define CFG_FLASH_ADDR0 0x5555 /* 1st address for flash config cycles */
-#define CFG_FLASH_ADDR1 0x2AAA /* 2nd address for flash config cycles */
+#define CFG_FLASH_WORD_SIZE unsigned short /* flash word size (width) */
+#define CFG_FLASH_ADDR0 0x5555 /* 1st addr for flash config cycles */
+#define CFG_FLASH_ADDR1 0x2AAA /* 2nd addr for flash config cycles */
/*
* The following defines are added for buggy IOP480 byte interface.
* All other boards should use the standard values (CPCI405 etc.)
*/
-#define CFG_FLASH_READ0 0x0000 /* 0 is standard */
-#define CFG_FLASH_READ1 0x0001 /* 1 is standard */
-#define CFG_FLASH_READ2 0x0002 /* 2 is standard */
+#define CFG_FLASH_READ0 0x0000 /* 0 is standard */
+#define CFG_FLASH_READ1 0x0001 /* 1 is standard */
+#define CFG_FLASH_READ2 0x0002 /* 2 is standard */
-#define CFG_FLASH_EMPTY_INFO /* print 'E' for empty sector on flinfo */
+#define CFG_FLASH_EMPTY_INFO /* print 'E' for empty sector */
-/*-----------------------------------------------------------------------
+/*
* Start addresses for the final memory configuration
* (Set up by the startup code)
* Please note that CFG_SDRAM_BASE _must_ start at 0
*/
#define CFG_SDRAM_BASE 0x00000000
-#define CFG_FLASH_BASE 0xFFFC0000
+#define CFG_FLASH_BASE 0xFFFA0000
#define CFG_MONITOR_BASE TEXT_BASE
-#define CFG_MONITOR_LEN (256 * 1024) /* Reserve 256 kB for Monitor */
-#define CFG_MALLOC_LEN (256 * 1024) /* Reserve 256 kB for malloc() */
+#define CFG_MONITOR_LEN (384 * 1024) /* Reserve 384kB for Monitor */
+#define CFG_MALLOC_LEN (384 * 1024) /* Reserve 384kB for malloc() */
-#if (CFG_MONITOR_BASE < FLASH_BASE0_PRELIM)
-# define CFG_RAMBOOT 1
-#else
-# undef CFG_RAMBOOT
-#endif
-
-/*-----------------------------------------------------------------------
+/*
* Environment Variable setup
*/
#define CFG_ENV_IS_IN_EEPROM 1 /* use EEPROM for environment vars */
-#define CFG_ENV_OFFSET 0x100 /* environment starts at the beginning of the EEPROM */
-#define CFG_ENV_SIZE 0x700 /* 2048 bytes may be used for env vars*/
- /* total size of a CAT24WC16 is 2048 bytes */
+#define CFG_ENV_OFFSET 0x100 /* reseve 0x100 bytes for strapping */
+#define CFG_ENV_SIZE 0x700
-/*-----------------------------------------------------------------------
- * I2C EEPROM (CAT24WC16) for environment
+/*
+ * I2C EEPROM (24WC16) for environment
*/
#define CONFIG_HARD_I2C /* I2c with hardware support */
#define CFG_I2C_SPEED 400000 /* I2C speed and slave address */
#define CFG_I2C_SLAVE 0x7F
-#define CFG_I2C_EEPROM_ADDR 0x50 /* EEPROM CAT24WC08 */
+#define CFG_I2C_EEPROM_ADDR 0x50 /* EEPROM 24WC16 */
#define CFG_EEPROM_WREN 1
-/* CAT24WC08/16... */
+/* 24WC16 */
#define CFG_I2C_EEPROM_ADDR_LEN 1 /* Bytes of address */
-/* mask of address bits that overflow into the "EEPROM chip address" */
+/* mask of address bits that overflow into the "EEPROM chip address" */
#define CFG_I2C_EEPROM_ADDR_OVERFLOW 0x07
-#define CFG_EEPROM_PAGE_WRITE_BITS 4 /* The Catalyst CAT24WC08 has */
- /* 16 byte page write mode using*/
- /* last 4 bits of the address */
+#define CFG_EEPROM_PAGE_WRITE_BITS 4 /* The 24WC16 has */
+ /* 16 byte page write mode using */
+ /* last 4 bits of the address */
#define CFG_EEPROM_PAGE_WRITE_DELAY_MS 10 /* and takes up to 10 msec */
#define CFG_EEPROM_PAGE_WRITE_ENABLE
-/*-----------------------------------------------------------------------
+/*
* External Bus Controller (EBC) Setup
*/
-
-#define CAN_BA 0xF0000000 /* CAN Base Address */
-#define DUART0_BA 0xF0000400 /* DUART Base Address */
-#define DUART1_BA 0xF0000408 /* DUART Base Address */
-#define RTC_BA 0xF0000500 /* RTC Base Address */
-#define VGA_BA 0xF1000000 /* Epson VGA Base Address */
-#define CFG_NAND_BASE 0xF4000000 /* NAND FLASH Base Address */
-
-/* Memory Bank 0 (Flash Bank 0, NOR-FLASH) initialization */
+#define CAN_BA 0xF0000000 /* CAN Base Address */
+#define DUART0_BA 0xF0000400 /* DUART Base Address */
+#define DUART1_BA 0xF0000408 /* DUART Base Address */
+#define RTC_BA 0xF0000500 /* RTC Base Address */
+#define VGA_BA 0xF1000000 /* Epson VGA Base Address */
+#define CFG_NAND_BASE 0xF4000000 /* NAND FLASH Base Address */
+
+/* Memory Bank 0 (Flash Bank 0, NOR-FLASH) initialization */
+/* TWT=16,CSN=1,OEN=1,WBN=1,WBF=1,TH=4,SOR=1 */
#define CFG_EBC_PB0AP 0x92015480
-/*#define CFG_EBC_PB0AP 0x08055880 /XXX* TWT=16,CSN=1,OEN=1,WBN=1,WBF=1,TH=4,SOR=1 */
-#define CFG_EBC_PB0CR 0xFFC5A000 /* BAS=0xFFC,BS=4MB,BU=R/W,BW=16bit */
+/* BAS=0xFFC,BS=4MB,BU=R/W,BW=16bit */
+#define CFG_EBC_PB0CR 0xFFC5A000
-/* Memory Bank 1 (Flash Bank 1, NAND-FLASH) initialization */
+/* Memory Bank 1 (Flash Bank 1, NAND-FLASH) initialization */
#define CFG_EBC_PB1AP 0x92015480
-#define CFG_EBC_PB1CR 0xF4018000 /* BAS=0xF40,BS=1MB,BU=R/W,BW=8bit */
+/* BAS=0xF40,BS=1MB,BU=R/W,BW=8bit */
+#define CFG_EBC_PB1CR 0xF4018000
-/* Memory Bank 2 (8 Bit Peripheral: CAN, UART, RTC) initialization */
-#define CFG_EBC_PB2AP 0x010053C0 /* BWT=2,WBN=1,WBF=1,TH=1,RE=1,SOR=1,BEM=1 */
-#define CFG_EBC_PB2CR 0xF0018000 /* BAS=0xF00,BS=1MB,BU=R/W,BW=8bit */
+/* Memory Bank 2 (8 Bit Peripheral: CAN, UART, RTC) initialization */
+/* BWT=2,WBN=1,WBF=1,TH=1,RE=1,SOR=1,BEM=1 */
+#define CFG_EBC_PB2AP 0x010053C0
+/* BAS=0xF00,BS=1MB,BU=R/W,BW=8bit */
+#define CFG_EBC_PB2CR 0xF0018000
-/* Memory Bank 3 (16 Bit Peripheral: FPGA internal, dig. IO) initialization */
-#define CFG_EBC_PB3AP 0x010053C0 /* BWT=2,WBN=1,WBF=1,TH=1,RE=1,SOR=1,BEM=1 */
-#define CFG_EBC_PB3CR 0xF011A000 /* BAS=0xF01,BS=1MB,BU=R/W,BW=16bit */
+/* Memory Bank 3 (16 Bit Peripheral: FPGA internal, dig. IO) initialization */
+/* BWT=2,WBN=1,WBF=1,TH=1,RE=1,SOR=1,BEM=1 */
+#define CFG_EBC_PB3AP 0x010053C0
+/* BAS=0xF01,BS=1MB,BU=R/W,BW=16bit */
+#define CFG_EBC_PB3CR 0xF011A000
-/*-----------------------------------------------------------------------
+/*
* FPGA stuff
*/
-
-#define CFG_FPGA_BASE_ADDR 0xF0100100 /* FPGA internal Base Address */
+#define CFG_FPGA_BASE_ADDR 0xF0100100 /* FPGA internal Base Address */
/* FPGA internal regs */
#define CFG_FPGA_CTRL 0x000
#define CFG_FPGA_CTRL_WDI 0x0002
#define CFG_FPGA_CTRL_PS2_RESET 0x0020
-#define CFG_FPGA_SPARTAN2 1 /* using Xilinx Spartan 2 now */
+#define CFG_FPGA_SPARTAN2 1 /* using Xilinx Spartan 2 now */
#define CFG_FPGA_MAX_SIZE 128*1024 /* 128kByte is enough for XC2S50E*/
/* FPGA program pin configuration */
#define CFG_FPGA_PRG 0x04000000 /* FPGA program pin (ppc output) */
-#define CFG_FPGA_CLK 0x02000000 /* FPGA clk pin (ppc output) */
-#define CFG_FPGA_DATA 0x01000000 /* FPGA data pin (ppc output) */
-#define CFG_FPGA_INIT 0x00010000 /* FPGA init pin (ppc input) */
-#define CFG_FPGA_DONE 0x00008000 /* FPGA done pin (ppc input) */
+#define CFG_FPGA_CLK 0x02000000 /* FPGA clk pin (ppc output) */
+#define CFG_FPGA_DATA 0x01000000 /* FPGA data pin (ppc output) */
+#define CFG_FPGA_INIT 0x00010000 /* FPGA init pin (ppc input) */
+#define CFG_FPGA_DONE 0x00008000 /* FPGA done pin (ppc input) */
-/*-----------------------------------------------------------------------
+/*
* Definitions for initial stack pointer and data area (in data cache)
*/
/* use on chip memory ( OCM ) for temperary stack until sdram is tested */
/* On Chip Memory location */
#define CFG_OCM_DATA_ADDR 0xF8000000
#define CFG_OCM_DATA_SIZE 0x1000
-#define CFG_INIT_RAM_ADDR CFG_OCM_DATA_ADDR /* inside of SDRAM */
-#define CFG_INIT_RAM_END CFG_OCM_DATA_SIZE /* End of used area in RAM */
+#define CFG_INIT_RAM_ADDR CFG_OCM_DATA_ADDR /* inside of SDRAM */
+#define CFG_INIT_RAM_END CFG_OCM_DATA_SIZE /* End of used area in RAM */
-#define CFG_GBL_DATA_SIZE 128 /* size in bytes reserved for initial data */
+#define CFG_GBL_DATA_SIZE 128 /* size in bytes reserved for initial data */
#define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
#define CFG_INIT_SP_OFFSET CFG_GBL_DATA_OFFSET
-/*-----------------------------------------------------------------------
+/*
* Definitions for GPIO setup (PPC405EP specific)
*
* GPIO0[0] - External Bus Controller BLAST output
*
* Boot Flags
*/
-#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */
-#define BOOTFLAG_WARM 0x02 /* Software reboot */
+#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */
+#define BOOTFLAG_WARM 0x02 /* Software reboot */
/*
- * Default speed selection (cpu_plb_opb_ebc) in mhz.
+ * Default speed selection (cpu_plb_opb_ebc) in MHz.
* This value will be set if iic boot eprom is disabled.
*/
-#if 0
+#if 1
#define PLLMR0_DEFAULT PLLMR0_266_133_66_33
#define PLLMR1_DEFAULT PLLMR1_266_133_66_33
#endif
#define PLLMR0_DEFAULT PLLMR0_200_100_50_33
#define PLLMR1_DEFAULT PLLMR1_200_100_50_33
#endif
-#if 1
+#if 0
#define PLLMR0_DEFAULT PLLMR0_133_66_66_33
#define PLLMR1_DEFAULT PLLMR1_133_66_66_33
#endif
+/*
+ * PCI OHCI controller
+ */
+#define CONFIG_USB_OHCI_NEW 1
+#define CONFIG_PCI_OHCI 1
+#define CFG_OHCI_SWAP_REG_ACCESS 1
+#define CFG_USB_OHCI_MAX_ROOT_PORTS 15
+#define CFG_USB_OHCI_SLOT_NAME "ohci_pci"
+#define CONFIG_USB_STORAGE 1
+
#endif /* __CONFIG_H */
/*
* board/config.h - configuration options, board specific
*/
-
#ifndef __CONFIG_H
#define __CONFIG_H
* High Level Configuration Options
* (easy to change)
*/
-
#define CONFIG_405EP 1 /* This is a PPC405 CPU */
#define CONFIG_4xx 1 /* ...member of PPC4xx family */
#define CONFIG_VOM405 1 /* ...on a VOM405 board */
#define CONFIG_BOOTP_DNS2
#define CONFIG_BOOTP_SEND_HOSTNAME
-
/*
* Command line configuration.
*/
#define CONFIG_CMD_DHCP
#define CONFIG_CMD_BSP
-#define CONFIG_CMD_PCI
#define CONFIG_CMD_IRQ
#define CONFIG_CMD_ELF
#define CONFIG_CMD_I2C
#define CONFIG_CMD_PING
#define CONFIG_CMD_EEPROM
+#define CONFIG_OF_LIBFDT
+#define CONFIG_OF_BOARD_SETUP
#undef CONFIG_WATCHDOG /* watchdog disabled */
#define CFG_HZ 1000 /* decrementer freq: 1 ms ticks */
+#define CONFIG_CMDLINE_EDITING 1 /* add command line history */
#define CONFIG_ZERO_BOOTDELAY_CHECK /* check for keypress on bootdelay==0 */
#define CONFIG_VERSION_VARIABLE 1 /* include version env variable */
#define CFG_RX_ETH_BUFFER 16 /* use 16 rx buffer on 405 emac */
-/*-----------------------------------------------------------------------
- * PCI stuff
- *-----------------------------------------------------------------------
- */
-#define PCI_HOST_ADAPTER 0 /* configure as pci adapter */
-#define PCI_HOST_FORCE 1 /* configure as pci host */
-#define PCI_HOST_AUTO 2 /* detected via arbiter enable */
-
-#define CONFIG_PCI /* include pci support */
-#define CONFIG_PCI_HOST PCI_HOST_HOST /* select pci host function */
-#undef CONFIG_PCI_PNP /* do pci plug-and-play */
- /* resource configuration */
-
-#undef CONFIG_PCI_SCAN_SHOW /* print pci devices @ startup */
-
-#define CFG_PCI_SUBSYS_VENDORID 0x12FE /* PCI Vendor ID: esd gmbh */
-#define CFG_PCI_SUBSYS_DEVICEID 0x0405 /* PCI Device ID: CPCI-405 */
-#define CFG_PCI_CLASSCODE 0x0b20 /* PCI Class Code: Processor/PPC*/
-#define CFG_PCI_PTM1LA 0x00000000 /* point to sdram */
-#define CFG_PCI_PTM1MS 0xfc000001 /* 64MB, enable hard-wired to 1 */
-#define CFG_PCI_PTM1PCI 0x00000000 /* Host: use this pci address */
-#define CFG_PCI_PTM2LA 0xffc00000 /* point to flash */
-#define CFG_PCI_PTM2MS 0xffc00001 /* 4MB, enable */
-#define CFG_PCI_PTM2PCI 0x04000000 /* Host: use this pci address */
-
/*
* For booting Linux, the board info and command line data
* have to be in the first 8 MB of memory, since this is
* the maximum mapped by the Linux kernel during initialization.
*/
#define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */
-/*-----------------------------------------------------------------------
+/*
* FLASH organization
*/
#define FLASH_BASE0_PRELIM 0xFFC00000 /* FLASH bank #0 */
#define CFG_FLASH_EMPTY_INFO /* print 'E' for empty sector on flinfo */
-#if 0 /* test-only */
-#define CFG_JFFS2_FIRST_BANK 0 /* use for JFFS2 */
-#define CFG_JFFS2_NUM_BANKS 1 /* ! second bank contains U-Boot */
-#endif
-
-/*-----------------------------------------------------------------------
+/*
* Start addresses for the final memory configuration
* (Set up by the startup code)
* Please note that CFG_SDRAM_BASE _must_ start at 0
# undef CFG_RAMBOOT
#endif
-/*-----------------------------------------------------------------------
+/*
* Environment Variable setup
*/
#define CFG_ENV_IS_IN_EEPROM 1 /* use EEPROM for environment vars */
#define CFG_NVRAM_BASE_ADDR 0xF0000500 /* NVRAM base address */
#define CFG_NVRAM_SIZE 242 /* NVRAM size */
-/*-----------------------------------------------------------------------
+/*
* I2C EEPROM (CAT24WC16) for environment
*/
#define CONFIG_HARD_I2C /* I2c with hardware support */
#define CFG_EEPROM_PAGE_WRITE_DELAY_MS 10 /* and takes up to 10 msec */
#define CFG_EEPROM_PAGE_WRITE_ENABLE
-/*-----------------------------------------------------------------------
+/*
* External Bus Controller (EBC) Setup
*/
-
#define CAN_BA 0xF0000000 /* CAN Base Address */
/* Memory Bank 0 (Flash Bank 0, NOR-FLASH) initialization */
#define CFG_EBC_PB2AP 0x010053C0 /* BWT=2,WBN=1,WBF=1,TH=1,RE=1,SOR=1,BEM=1 */
#define CFG_EBC_PB2CR 0xF0018000 /* BAS=0xF00,BS=1MB,BU=R/W,BW=8bit */
-/*-----------------------------------------------------------------------
+/*
* FPGA stuff
*/
#define CFG_FPGA_XC95XL 1 /* using Xilinx XC95XL CPLD */
#define CFG_FPGA_INIT 0x00010000 /* unused (ppc input) */
#define CFG_FPGA_DONE 0x00008000 /* JTAG TDI->TDO pin (ppc input) */
-/*-----------------------------------------------------------------------
+/*
* Definitions for initial stack pointer and data area (in data cache)
*/
/* use on chip memory ( OCM ) for temperary stack until sdram is tested */
#define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
#define CFG_INIT_SP_OFFSET CFG_GBL_DATA_OFFSET
-/*-----------------------------------------------------------------------
+/*
* Definitions for GPIO setup (PPC405EP specific)
*
* GPIO0[0] - External Bus Controller BLAST output
--- /dev/null
+/*
+ * (C) Copyright 2008
+ * Benjamin Warren, biggerbadderben@gmail.com
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+/*
+ * netdev.h - definitions an prototypes for network devices
+ */
+
+#ifndef _NETDEV_H_
+#define _NETDEV_H_
+
+/*
+ * Board and CPU-specific initialization functions
+ * board_eth_init() has highest priority. cpu_eth_init() only
+ * gets called if board_eth_init() isn't instantiated or fails.
+ * Return values:
+ * 0: success
+ * -1: failure
+ */
+
+int board_eth_init(bd_t *bis);
+int cpu_eth_init(bd_t *bis);
+
+/* Driver initialization prototypes */
+int bfin_EMAC_initialize(bd_t *bis);
+int dc21x4x_initialize(bd_t *bis);
+int e1000_initialize(bd_t *bis);
+int eepro100_initialize(bd_t *bis);
+int eth_3com_initialize (bd_t * bis);
+int greth_initialize(bd_t *bis);
+void gt6426x_eth_initialize(bd_t *bis);
+int inca_switch_initialize(bd_t *bis);
+int macb_eth_initialize(int id, void *regs, unsigned int phy_addr);
+int mcdmafec_initialize(bd_t *bis);
+int mcffec_initialize(bd_t *bis);
+int mpc512x_fec_initialize(bd_t *bis);
+int mpc5xxx_fec_initialize(bd_t *bis);
+int natsemi_initialize(bd_t *bis);
+int ns8382x_initialize(bd_t *bis);
+int pcnet_initialize(bd_t *bis);
+int plb2800_eth_initialize(bd_t *bis);
+int rtl8139_initialize(bd_t *bis);
+int rtl8169_initialize(bd_t *bis);
+int skge_initialize(bd_t *bis);
+int tsi108_eth_initialize(bd_t *bis);
+int uli526x_initialize(bd_t *bis);
+
+/* Boards with PCI network controllers can call this from their board_eth_init()
+ * function to initialize whatever's on board.
+ * Return value is total # of devices found */
+
+static inline int pci_eth_init(bd_t *bis)
+{
+ int num = 0;
+
+#ifdef CONFIG_PCI
+
+#ifdef CONFIG_EEPRO100
+ num += eepro100_initialize(bis);
+#endif
+#ifdef CONFIG_TULIP
+ num += dc21x4x_initialize(bis);
+#endif
+#ifdef CONFIG_E1000
+ num += e1000_initialize(bis);
+#endif
+#ifdef CONFIG_PCNET
+ num += pcnet_initialize(bis);
+#endif
+#ifdef CONFIG_NATSEMI
+ num += natsemi_initialize(bis);
+#endif
+#ifdef CONFIG_NS8382X
+ num += ns8382x_initialize(bis);
+#endif
+#if defined(CONFIG_RTL8139)
+ num += rtl8139_initialize(bis);
+#endif
+#if defined(CONFIG_RTL8169)
+ num += rtl8169_initialize(bis);
+#endif
+#if defined(CONFIG_ULI526)
+ num += uli526x_initialize(bis);
+#endif
+
+#endif /* CONFIG_PCI */
+ return num;
+}
+
+#endif /* _NETDEV_H_ */
+
#define TSEC_SIZE 0x01000
/* FIXME: Should these be pushed back to 83xx and 85xx config files? */
-#if defined(CONFIG_MPC85xx) || defined(CONFIG_MPC86xx)
- #define TSEC_BASE_ADDR (CFG_IMMR + CFG_TSEC1_OFFSET)
-#elif defined(CONFIG_MPC83XX)
+#if defined(CONFIG_MPC85xx) || defined(CONFIG_MPC86xx) \
+ || defined(CONFIG_MPC83XX)
#define TSEC_BASE_ADDR (CFG_IMMR + CFG_TSEC1_OFFSET)
#endif
+#define STD_TSEC_INFO(num) \
+{ \
+ .regs = (tsec_t *)(TSEC_BASE_ADDR + ((num - 1) * TSEC_SIZE)), \
+ .miiregs = (tsec_t *)TSEC_BASE_ADDR, \
+ .devname = CONFIG_TSEC##num##_NAME, \
+ .phyaddr = TSEC##num##_PHY_ADDR, \
+ .flags = TSEC##num##_FLAGS \
+}
+
+#define SET_STD_TSEC_INFO(x, num) \
+{ \
+ x.regs = (tsec_t *)(TSEC_BASE_ADDR + ((num - 1) * TSEC_SIZE)); \
+ x.miiregs = (tsec_t *)TSEC_BASE_ADDR; \
+ x.devname = CONFIG_TSEC##num##_NAME; \
+ x.phyaddr = TSEC##num##_PHY_ADDR; \
+ x.flags = TSEC##num##_FLAGS;\
+}
+
+
#define MAC_ADDR_LEN 6
#define PHY_AUTONEGOTIATE_TIMEOUT 5000 /* in ms */
+/* TBI register addresses */
+#define TBI_CR 0x00
+#define TBI_SR 0x01
+#define TBI_ANA 0x04
+#define TBI_ANLPBPA 0x05
+#define TBI_ANEX 0x06
+#define TBI_TBICON 0x11
+
+/* TBI MDIO register bit fields*/
+#define TBICON_CLK_SELECT 0x0020
+#define TBIANA_ASYMMETRIC_PAUSE 0x0100
+#define TBIANA_SYMMETRIC_PAUSE 0x0080
+#define TBIANA_HALF_DUPLEX 0x0040
+#define TBIANA_FULL_DUPLEX 0x0020
+#define TBICR_PHY_RESET 0x8000
+#define TBICR_ANEG_ENABLE 0x1000
+#define TBICR_RESTART_ANEG 0x0200
+#define TBICR_FULL_DUPLEX 0x0100
+#define TBICR_SPEED1_SET 0x0040
+
+
/* MAC register bits */
#define MACCFG1_SOFT_RESET 0x80000000
#define MACCFG1_RESET_RX_MC 0x00080000
#define MIIM_88E1111_PHY_LED_DIRECT 0x4100
#define MIIM_88E1111_PHY_LED_COMBINE 0x411C
+/* 88E1121 PHY LED Control Register */
+#define MIIM_88E1121_PHY_LED_CTRL 16
+#define MIIM_88E1121_PHY_LED_PAGE 3
+#define MIIM_88E1121_PHY_LED_DEF 0x0030
+
+#define MIIM_88E1121_PHY_PAGE 22
+
/* 88E1145 Extended PHY Specific Control Register */
#define MIIM_88E1145_PHY_EXT_CR 20
#define MIIM_M88E1145_RGMII_RX_DELAY 0x0080
/* This flag currently only has
* meaning if we're using the eTSEC */
-#define TSEC_REDUCED (1 << 1)
+#define TSEC_REDUCED (1 << 1)
+
+#define TSEC_SGMII (1 << 2)
struct tsec_private {
volatile tsec_t *regs;
struct phy_cmd *shutdown;
};
+struct tsec_info_struct {
+ tsec_t *regs;
+ tsec_t *miiregs;
+ char *devname;
+ unsigned int phyaddr;
+ u32 flags;
+};
+
+int tsec_initialize(bd_t * bis, struct tsec_info_struct *tsec_info);
+int tsec_standard_init(bd_t *bis);
+int tsec_eth_init(bd_t *bis, struct tsec_info_struct *tsec_info, int num);
+
#endif /* __TSEC_H */
int cpu_eth_init(bd_t *bis) __attribute((weak, alias("__def_eth_init")));
int board_eth_init(bd_t *bis) __attribute((weak, alias("__def_eth_init")));
-#ifdef CFG_GT_6426x
-extern int gt6426x_eth_initialize(bd_t *bis);
-#endif
-
extern int au1x00_enet_initialize(bd_t*);
-extern int dc21x4x_initialize(bd_t*);
-extern int e1000_initialize(bd_t*);
-extern int eepro100_initialize(bd_t*);
-extern int eth_3com_initialize(bd_t*);
extern int fec_initialize(bd_t*);
-extern int inca_switch_initialize(bd_t*);
-extern int mpc5xxx_fec_initialize(bd_t*);
-extern int mpc512x_fec_initialize(bd_t*);
extern int mpc8220_fec_initialize(bd_t*);
extern int mv6436x_eth_initialize(bd_t *);
extern int mv6446x_eth_initialize(bd_t *);
-extern int natsemi_initialize(bd_t*);
-extern int ns8382x_initialize(bd_t*);
-extern int pcnet_initialize(bd_t*);
-extern int plb2800_eth_initialize(bd_t*);
extern int ppc_4xx_eth_initialize(bd_t *);
-extern int rtl8139_initialize(bd_t*);
-extern int rtl8169_initialize(bd_t*);
extern int scc_initialize(bd_t*);
-extern int tsi108_eth_initialize(bd_t*);
extern int npe_initialize(bd_t *);
extern int uec_initialize(int);
-extern int at91sam9_eth_initialize(bd_t *);
#ifdef CONFIG_API
extern void (*push_packet)(volatile void *, int);
#if defined(CONFIG_4xx) && !defined(CONFIG_IOP480) && !defined(CONFIG_AP1000)
ppc_4xx_eth_initialize(bis);
#endif
-#ifdef CONFIG_INCA_IP_SWITCH
- inca_switch_initialize(bis);
-#endif
-#ifdef CONFIG_PLB2800_ETHER
- plb2800_eth_initialize(bis);
-#endif
#ifdef SCC_ENET
scc_initialize(bis);
#endif
-#if defined(CONFIG_MPC5xxx_FEC)
- mpc5xxx_fec_initialize(bis);
-#endif
-#if defined(CONFIG_MPC512x_FEC)
- mpc512x_fec_initialize (bis);
-#endif
#if defined(CONFIG_MPC8220_FEC)
mpc8220_fec_initialize(bis);
#endif
#if defined(CONFIG_IXP4XX_NPE)
npe_initialize(bis);
#endif
-#ifdef CONFIG_E1000
- e1000_initialize(bis);
-#endif
-#ifdef CONFIG_EEPRO100
- eepro100_initialize(bis);
-#endif
-#ifdef CONFIG_TULIP
- dc21x4x_initialize(bis);
-#endif
-#ifdef CONFIG_3COM
- eth_3com_initialize(bis);
-#endif
-#ifdef CONFIG_PCNET
- pcnet_initialize(bis);
-#endif
-#ifdef CFG_GT_6426x
- gt6426x_eth_initialize(bis);
-#endif
-#ifdef CONFIG_NATSEMI
- natsemi_initialize(bis);
-#endif
-#ifdef CONFIG_NS8382X
- ns8382x_initialize(bis);
-#endif
-#if defined(CONFIG_TSI108_ETH)
- tsi108_eth_initialize(bis);
-#endif
-#if defined(CONFIG_RTL8139)
- rtl8139_initialize(bis);
-#endif
-#if defined(CONFIG_RTL8169)
- rtl8169_initialize(bis);
-#endif
-#if defined(CONFIG_AT91CAP9) || defined(CONFIG_AT91SAM9260) || \
- defined(CONFIG_AT91SAM9263)
- at91sam9_eth_initialize(bis);
-#endif
-
if (!eth_devices) {
puts ("No ethernet found.\n");
show_boot_progress (-64);
for (i=0; i<CFG_MAX_FLASH_BANKS; i++) {
/* start address in flash? */
+ if (flash_info[i].flash_id == FLASH_UNKNOWN)
+ continue;
if (load_addr + offset >= flash_info[i].start[0]) {
rc = 1;
break;
projects / platform / kernel / u-boot.git / commitdiff