drm/i915: s/intel_gen4_compute_page_offset/intel_compute_tile_offset/

Since intel_gen4_compute_page_offset() can now handle tiling formats
all the way down to gen2, rename it to intel_compute_tile_offset().
Not that we actually use it on gen2/3 since there's no DSPSURF etc.
registers which would take a page aligned address.

v2: s/page/tile/ (Daniel)

Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Reviewed-by: Daniel Vetter <daniel.vetter@ffwll.ch>
Link: http://patchwork.freedesktop.org/patch/msgid/1452625717-9713-7-git-send-email-ville.syrjala@linux.intel.com

diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
index 8a76e29..bffeacf 100644 (file)
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -2457,11 +2457,11 @@ static void intel_unpin_fb_obj(struct drm_framebuffer *fb,
 
 /* Computes the linear offset to the base tile and adjusts x, y. bytes per pixel
  * is assumed to be a power-of-two. */
-unsigned long intel_gen4_compute_page_offset(struct drm_i915_private *dev_priv,
-                                            int *x, int *y,
-                                            uint64_t fb_modifier,
-                                            unsigned int cpp,
-                                            unsigned int pitch)
+unsigned long intel_compute_tile_offset(struct drm_i915_private *dev_priv,
+                                       int *x, int *y,
+                                       uint64_t fb_modifier,
+                                       unsigned int cpp,
+                                       unsigned int pitch)
 {
        if (fb_modifier != DRM_FORMAT_MOD_NONE) {
                unsigned int tile_size, tile_width, tile_height;
@@ -2784,10 +2784,10 @@ static void i9xx_update_primary_plane(struct drm_plane *primary,
 
        if (INTEL_INFO(dev)->gen >= 4) {
                intel_crtc->dspaddr_offset =
-                       intel_gen4_compute_page_offset(dev_priv, &x, &y,
-                                                      fb->modifier[0],
-                                                      pixel_size,
-                                                      fb->pitches[0]);
+                       intel_compute_tile_offset(dev_priv, &x, &y,
+                                                 fb->modifier[0],
+                                                 pixel_size,
+                                                 fb->pitches[0]);
                linear_offset -= intel_crtc->dspaddr_offset;
        } else {
                intel_crtc->dspaddr_offset = linear_offset;
@@ -2892,10 +2892,10 @@ static void ironlake_update_primary_plane(struct drm_plane *primary,
 
        linear_offset = y * fb->pitches[0] + x * pixel_size;
        intel_crtc->dspaddr_offset =
-               intel_gen4_compute_page_offset(dev_priv, &x, &y,
-                                              fb->modifier[0],
-                                              pixel_size,
-                                              fb->pitches[0]);
+               intel_compute_tile_offset(dev_priv, &x, &y,
+                                         fb->modifier[0],
+                                         pixel_size,
+                                         fb->pitches[0]);
        linear_offset -= intel_crtc->dspaddr_offset;
        if (plane_state->base.rotation == BIT(DRM_ROTATE_180)) {
                dspcntr |= DISPPLANE_ROTATE_180;

diff --git a/drivers/gpu/drm/i915/intel_drv.h b/drivers/gpu/drm/i915/intel_drv.h
index 6aaaa8d..059b46e 100644 (file)
--- a/drivers/gpu/drm/i915/intel_drv.h
+++ b/drivers/gpu/drm/i915/intel_drv.h
@@ -1195,11 +1195,11 @@ void assert_fdi_rx_pll(struct drm_i915_private *dev_priv,
 void assert_pipe(struct drm_i915_private *dev_priv, enum pipe pipe, bool state);
 #define assert_pipe_enabled(d, p) assert_pipe(d, p, true)
 #define assert_pipe_disabled(d, p) assert_pipe(d, p, false)
-unsigned long intel_gen4_compute_page_offset(struct drm_i915_private *dev_priv,
-                                            int *x, int *y,
-                                            uint64_t fb_modifier,
-                                            unsigned int cpp,
-                                            unsigned int pitch);
+unsigned long intel_compute_tile_offset(struct drm_i915_private *dev_priv,
+                                       int *x, int *y,
+                                       uint64_t fb_modifier,
+                                       unsigned int cpp,
+                                       unsigned int pitch);
 void intel_prepare_reset(struct drm_device *dev);
 void intel_finish_reset(struct drm_device *dev);
 void hsw_enable_pc8(struct drm_i915_private *dev_priv);

diff --git a/drivers/gpu/drm/i915/intel_sprite.c b/drivers/gpu/drm/i915/intel_sprite.c
index 64083d7..22589fc 100644 (file)
--- a/drivers/gpu/drm/i915/intel_sprite.c
+++ b/drivers/gpu/drm/i915/intel_sprite.c
@@ -423,10 +423,10 @@ vlv_update_plane(struct drm_plane *dplane,
        crtc_h--;
 
        linear_offset = y * fb->pitches[0] + x * pixel_size;
-       sprsurf_offset = intel_gen4_compute_page_offset(dev_priv, &x, &y,
-                                                       fb->modifier[0],
-                                                       pixel_size,
-                                                       fb->pitches[0]);
+       sprsurf_offset = intel_compute_tile_offset(dev_priv, &x, &y,
+                                                  fb->modifier[0],
+                                                  pixel_size,
+                                                  fb->pitches[0]);
        linear_offset -= sprsurf_offset;
 
        if (plane_state->base.rotation == BIT(DRM_ROTATE_180)) {
@@ -557,10 +557,10 @@ ivb_update_plane(struct drm_plane *plane,
                sprscale = SPRITE_SCALE_ENABLE | (src_w << 16) | src_h;
 
        linear_offset = y * fb->pitches[0] + x * pixel_size;
-       sprsurf_offset = intel_gen4_compute_page_offset(dev_priv, &x, &y,
-                                                       fb->modifier[0],
-                                                       pixel_size,
-                                                       fb->pitches[0]);
+       sprsurf_offset = intel_compute_tile_offset(dev_priv, &x, &y,
+                                                  fb->modifier[0],
+                                                  pixel_size,
+                                                  fb->pitches[0]);
        linear_offset -= sprsurf_offset;
 
        if (plane_state->base.rotation == BIT(DRM_ROTATE_180)) {
@@ -696,10 +696,10 @@ ilk_update_plane(struct drm_plane *plane,
                dvsscale = DVS_SCALE_ENABLE | (src_w << 16) | src_h;
 
        linear_offset = y * fb->pitches[0] + x * pixel_size;
-       dvssurf_offset = intel_gen4_compute_page_offset(dev_priv, &x, &y,
-                                                       fb->modifier[0],
-                                                       pixel_size,
-                                                       fb->pitches[0]);
+       dvssurf_offset = intel_compute_tile_offset(dev_priv, &x, &y,
+                                                  fb->modifier[0],
+                                                  pixel_size,
+                                                  fb->pitches[0]);
        linear_offset -= dvssurf_offset;
 
        if (plane_state->base.rotation == BIT(DRM_ROTATE_180)) {