}
}
+/* Return the byte register name for a register rtx X. B should be 0
+ if you want a lower byte register. B should be 1 if you want an
+ upper byte register. */
+
static const char *
byte_reg (rtx x, int b)
{
h8300_emit_stack_adjustment (-1, round_frame_size (get_frame_size ()));
}
+/* Return nonzero if we can use "rts" for the function currently being
+ compiled. */
+
int
h8300_can_use_return_insn_p (void)
{
&& EXTRA_CONSTRAINT (op, 'U'));
}
+/* Return nonzero if OP is a MEM suitable for bit manipulation insns. */
+
int
bit_memory_operand (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
{
return result;
}
\f
+/* Compute the cost of an and insn. */
+
static int
h8300_and_costs (rtx x)
{
return compute_logical_op_length (GET_MODE (x), operands) / 2;
}
+/* Compute the cost of a shift insn. */
+
static int
h8300_shift_costs (rtx x)
{
return compute_a_shift_length (NULL, operands) / 2;
}
+/* Worker function for TARGET_RTX_COSTS. */
+
static bool
h8300_rtx_costs (rtx x, int code, int outer_code, int *total)
{
abort ();
}
+/* Worker function for RETURN_ADDR_RTX. */
+
rtx
h8300_return_addr_rtx (int count, rtx frame)
{
}
}
\f
+/* Output an addition insn. */
+
const char *
output_plussi (rtx *operands)
{
}
}
+/* Compute the length of an addition insn. */
+
unsigned int
compute_plussi_length (rtx *operands)
{
}
}
+/* Compute which flag bits are valid after an addition insn. */
+
int
compute_plussi_cc (rtx *operands)
{
}
}
\f
+/* Output a logical insn. */
+
const char *
output_logical_op (enum machine_mode mode, rtx *operands)
{
return "";
}
+/* Compute the length of a logical insn. */
+
unsigned int
compute_logical_op_length (enum machine_mode mode, rtx *operands)
{
return length;
}
+/* Compute which flag bits are valid after a logical insn. */
+
int
compute_logical_op_cc (enum machine_mode mode, rtx *operands)
{
|| (TARGET_H8300H && mode == SImode && count == 8));
}
-/* Emit the assembler code for doing shifts. */
+/* Output the assembler code for doing shifts. */
const char *
output_a_shift (rtx *operands)
}
}
+/* Count the number of assembly instructions in a string TEMPLATE. */
+
static unsigned int
h8300_asm_insn_count (const char *template)
{
return count;
}
+/* Compute the length of a shift insn. */
+
unsigned int
compute_a_shift_length (rtx insn ATTRIBUTE_UNUSED, rtx *operands)
{
}
}
+/* Compute which flag bits are valid after a shift insn. */
+
int
compute_a_shift_cc (rtx insn ATTRIBUTE_UNUSED, rtx *operands)
{
return 1;
}
-/* Output rotate insns. */
+/* Output a rotate insn. */
const char *
output_a_rotate (enum rtx_code code, rtx *operands)
return "";
}
+/* Compute the length of a rotate insn. */
+
unsigned int
compute_a_rotate_length (rtx *operands)
{
SYMBOL_REF_FLAGS (XEXP (rtl, 0)) |= extra_flags;
}
+/* Output a single-bit extraction. */
+
const char *
output_simode_bld (int bild, rtx operands[])
{
}
+/* Return nonzero if ADDR1 and ADDR2 point to consecutive memory
+ locations that can be accessed as a 16-bit word. */
+
int
byte_accesses_mergeable_p (rtx addr1, rtx addr2)
{
set_optab_libfunc (umod_optab, HImode, "__umodhi3");
}
\f
+/* Worker function for TARGET_RETURN_IN_MEMORY. */
+
static bool
h8300_return_in_memory (tree type, tree fntype ATTRIBUTE_UNUSED)
{