lib: utils/irqchip: Add shared MMIO region for PLIC in root domain
authorAnup Patel <apatel@ventanamicro.com>
Mon, 11 Dec 2023 08:37:56 +0000 (14:07 +0530)
committerAnup Patel <anup@brainfault.org>
Tue, 19 Dec 2023 10:26:37 +0000 (15:56 +0530)
On platforms with Smepmp, the MMIO regions accessed by M-mode need
to be explicitly marked with M-mode only read/write or shared (both
(M-mode and S-mode) read/write permission.

If the above is not done then runtime PLIC access from M-mode on
platforms with Smepmp will result in access fault when further
results in CPU hotplug not working.

Signed-off-by: Anup Patel <apatel@ventanamicro.com>
include/sbi_utils/irqchip/plic.h
lib/utils/fdt/fdt_helper.c
lib/utils/irqchip/plic.c
platform/fpga/ariane/platform.c
platform/fpga/openpiton/platform.c
platform/kendryte/k210/platform.c
platform/kendryte/k210/platform.h
platform/nuclei/ux600/platform.c
platform/template/platform.c

index 112a714fd37c0459cac2c9426f2d8f9c921b4351..2eda6310df87fc26f8f024db18b9c86a10762eee 100644 (file)
@@ -14,6 +14,7 @@
 
 struct plic_data {
        unsigned long addr;
+       unsigned long size;
        unsigned long num_src;
 };
 
index 4ed6bbc105e4a061b0c331e39e2eb67685287f82..e50f4d849f6643ca2cf6953bb82d16ced5252ac2 100644 (file)
@@ -880,6 +880,7 @@ int fdt_parse_plic_node(void *fdt, int nodeoffset, struct plic_data *plic)
        if (rc < 0 || !reg_addr || !reg_size)
                return SBI_ENODEV;
        plic->addr = reg_addr;
+       plic->size = reg_size;
 
        val = fdt_getprop(fdt, nodeoffset, "riscv,ndev", &len);
        if (len > 0)
index d63351484a3573cbdde81097065dbc394de8c72b..193e3201dbcb4964950ad0b08d868af77914eccb 100644 (file)
@@ -10,7 +10,9 @@
 
 #include <sbi/riscv_io.h>
 #include <sbi/riscv_encoding.h>
+#include <sbi/sbi_bitops.h>
 #include <sbi/sbi_console.h>
+#include <sbi/sbi_domain.h>
 #include <sbi/sbi_error.h>
 #include <sbi/sbi_string.h>
 #include <sbi_utils/irqchip/plic.h>
@@ -171,5 +173,7 @@ int plic_cold_irqchip_init(const struct plic_data *plic)
        for (i = 1; i <= plic->num_src; i++)
                plic_set_priority(plic, i, 0);
 
-       return 0;
+       return sbi_domain_root_add_memrange(plic->addr, plic->size, BIT(20),
+                                       (SBI_DOMAIN_MEMREGION_MMIO |
+                                        SBI_DOMAIN_MEMREGION_SHARED_SURW_MRW));
 }
index 975528f1372e15be029ac28ec43d9cef50807462..8be5e6ca3854e43e16eb1eba0d23af26f438622a 100644 (file)
@@ -25,6 +25,8 @@
 #define ARIANE_UART_REG_WIDTH                  4
 #define ARIANE_UART_REG_OFFSET                 0
 #define ARIANE_PLIC_ADDR                       0xc000000
+#define ARIANE_PLIC_SIZE                       (0x200000 + \
+                                                (ARIANE_HART_COUNT * 0x1000))
 #define ARIANE_PLIC_NUM_SOURCES                        3
 #define ARIANE_HART_COUNT                      1
 #define ARIANE_CLINT_ADDR                      0x2000000
@@ -36,6 +38,7 @@
 
 static struct plic_data plic = {
        .addr = ARIANE_PLIC_ADDR,
+       .size = ARIANE_PLIC_SIZE,
        .num_src = ARIANE_PLIC_NUM_SOURCES,
 };
 
index e59dc992fe3bec1d04674db961a56d2ef60327ad..2317a899e8d6a4c62a0d16718e32f5e4fbfc3a92 100644 (file)
@@ -24,6 +24,8 @@
 #define OPENPITON_DEFAULT_UART_REG_WIDTH       1
 #define OPENPITON_DEFAULT_UART_REG_OFFSET      0
 #define OPENPITON_DEFAULT_PLIC_ADDR            0xfff1100000
+#define OPENPITON_DEFAULT_PLIC_SIZE            (0x200000 + \
+                               (OPENPITON_DEFAULT_HART_COUNT * 0x1000))
 #define OPENPITON_DEFAULT_PLIC_NUM_SOURCES     2
 #define OPENPITON_DEFAULT_HART_COUNT           3
 #define OPENPITON_DEFAULT_CLINT_ADDR           0xfff1020000
@@ -40,6 +42,7 @@ static struct platform_uart_data uart = {
 };
 static struct plic_data plic = {
        .addr = OPENPITON_DEFAULT_PLIC_ADDR,
+       .size = OPENPITON_DEFAULT_PLIC_SIZE,
        .num_src = OPENPITON_DEFAULT_PLIC_NUM_SOURCES,
 };
 
index 637a217fcd7bdc3cbb97f3b82e4181ad964f53e4..27b23f7326d79c9ba78c284049f7ccd1ba7e0899 100644 (file)
@@ -32,6 +32,7 @@ unsigned long fw_platform_init(unsigned long arg0, unsigned long arg1,
 
 static struct plic_data plic = {
        .addr = K210_PLIC_BASE_ADDR,
+       .size = K210_PLIC_BASE_SIZE,
        .num_src = K210_PLIC_NUM_SOURCES,
 };
 
index be52aa30a531dd58a0754ad9072459d49131fa7d..9417403d246a13aaf01fe96023e839ca3e4f48fb 100644 (file)
@@ -27,6 +27,7 @@
 #define K210_ACLINT_MTIMER_ADDR \
                (K210_CLINT_BASE_ADDR + CLINT_MTIMER_OFFSET)
 #define K210_PLIC_BASE_ADDR    0x0C000000ULL
+#define K210_PLIC_BASE_SIZE    (0x200000ULL + (K210_HART_COUNT * 0x1000))
 
 /* Registers */
 #define K210_PLL0              0x08
index 6fd6cd7082f0ff3803f0d381e943adde3127a41a..f688b50a68dca1bb64e9ba1e322f55275832df0e 100644 (file)
@@ -39,6 +39,8 @@
                                         CLINT_MTIMER_OFFSET)
 
 #define UX600_PLIC_ADDR                        0x8000000
+#define UX600_PLIC_SIZE                        (0x200000 + \
+                                        (UX600_HART_COUNT * 0x1000))
 #define UX600_PLIC_NUM_SOURCES         0x35
 #define UX600_PLIC_NUM_PRIORITIES      7
 
@@ -63,6 +65,7 @@ static u32 ux600_clk_freq = 8000000;
 
 static struct plic_data plic = {
        .addr = UX600_PLIC_ADDR,
+       .size = UX600_PLIC_SIZE,
        .num_src = UX600_PLIC_NUM_SOURCES,
 };
 
index 86381ca2b7096802a9e1190149a68ca4cbd989fd..4b3f2acff97af2fd390f087379dfc5f48cdfa123 100644 (file)
@@ -19,6 +19,8 @@
 #include <sbi_utils/timer/aclint_mtimer.h>
 
 #define PLATFORM_PLIC_ADDR             0xc000000
+#define PLATFORM_PLIC_SIZE             (0x200000 + \
+                                        (PLATFORM_HART_COUNT * 0x1000))
 #define PLATFORM_PLIC_NUM_SOURCES      128
 #define PLATFORM_HART_COUNT            4
 #define PLATFORM_CLINT_ADDR            0x2000000
@@ -33,6 +35,7 @@
 
 static struct plic_data plic = {
        .addr = PLATFORM_PLIC_ADDR,
+       .size = PLATFORM_PLIC_SIZE,
        .num_src = PLATFORM_PLIC_NUM_SOURCES,
 };