RISC-V: add auipc elements to parse_asm header

Instruction parsing should not be done in individual code, but instead
supported by central

Right now kgdb and kprobes parse instructions and at least kprobes (and
the upcoming auipc+jalr alternative fixer-function) need the auipc
instruction.

Reviewed-by: Conor Dooley <conor.dooley@microchip.com>
Reviewed-by: Andrew Jones <ajones@ventanamicro.com>
Reviewed-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
Signed-off-by: Heiko Stuebner <heiko.stuebner@vrull.eu>
Link: https://lore.kernel.org/r/20221223221332.4127602-6-heiko@sntech.de
Signed-off-by: Palmer Dabbelt <palmer@rivosinc.com>

diff --git a/arch/riscv/include/asm/parse_asm.h b/arch/riscv/include/asm/parse_asm.h
index e830325..28742eb 100644 (file)
--- a/arch/riscv/include/asm/parse_asm.h
+++ b/arch/riscv/include/asm/parse_asm.h
@@ -118,6 +118,7 @@
 #define RVC_C2_RD_OPOFF                7
 
 /* parts of opcode for RVG*/
+#define RVG_OPCODE_AUIPC       0x17
 #define RVG_OPCODE_BRANCH      0x63
 #define RVG_OPCODE_JALR                0x67
 #define RVG_OPCODE_JAL         0x6f
@@ -149,6 +150,7 @@
 #define RVG_FUNCT12_EBREAK     0x1
 #define RVG_FUNCT12_SRET       0x102
 
+#define RVG_MATCH_AUIPC                (RVG_OPCODE_AUIPC)
 #define RVG_MATCH_JALR         (RV_ENCODE_FUNCT3(JALR) | RVG_OPCODE_JALR)
 #define RVG_MATCH_JAL          (RVG_OPCODE_JAL)
 #define RVG_MATCH_BEQ          (RV_ENCODE_FUNCT3(BEQ) | RVG_OPCODE_BRANCH)
@@ -167,6 +169,7 @@
 #define RVC_MATCH_C_JALR       (RVC_ENCODE_FUNCT4(C_JALR) | RVC_OPCODE_C2)
 #define RVC_MATCH_C_EBREAK     (RVC_ENCODE_FUNCT4(C_EBREAK) | RVC_OPCODE_C2)
 
+#define RVG_MASK_AUIPC         (RV_INSN_OPCODE_MASK)
 #define RVG_MASK_JALR          (RV_INSN_FUNCT3_MASK | RV_INSN_OPCODE_MASK)
 #define RVG_MASK_JAL           (RV_INSN_OPCODE_MASK)
 #define RVC_MASK_C_JALR                (RVC_INSN_FUNCT4_MASK | RVC_INSN_J_RS2_MASK | RVC_INSN_OPCODE_MASK)