Signed-off-by: Ken Wang <Qingqing.Wang@amd.com>
Reviewed-by: Jammy Zhou <Jammy.Zhou@amd.com>
uint32_t vram_type;
/* video memory bit width*/
uint32_t vram_bit_width;
+ /** constant engine ram size*/
+ uint32_t ce_ram_size;
};
dev->dev_info.num_shader_arrays_per_engine;
dev->info.vram_type = dev->dev_info.vram_type;
dev->info.vram_bit_width = dev->dev_info.vram_bit_width;
+ dev->info.ce_ram_size = dev->dev_info.ce_ram_size;
for (i = 0; i < (int)dev->info.num_shader_engines; i++) {
unsigned instance = (i << AMDGPU_INFO_MMR_SE_INDEX_SHIFT) |
uint32_t vram_type;
/** video memory bit width*/
uint32_t vram_bit_width;
+ /** constant engine ram size*/
+ uint32_t ce_ram_size;
};
struct drm_amdgpu_info_hw_ip {