target-mips: enable 10-bit ASIDs in I6400 CPU
authorLeon Alrae <leon.alrae@imgtec.com>
Mon, 27 Jun 2016 15:19:12 +0000 (16:19 +0100)
committerLeon Alrae <leon.alrae@imgtec.com>
Tue, 12 Jul 2016 08:10:21 +0000 (09:10 +0100)
Signed-off-by: Leon Alrae <leon.alrae@imgtec.com>
target-mips/translate_init.c

index c43bdb7c21ce3970dc37ab54ef40262140f12475..39ed5c4c1b129b88f82555181d04b6e8714e43df 100644 (file)
@@ -685,7 +685,7 @@ static const mips_def_t mips_defs[] =
                        (1 << CP0C3_BP) | (1 << CP0C3_BI) | (1 << CP0C3_ULRI) |
                        (1 << CP0C3_RXI) | (1 << CP0C3_LPA) | (1 << CP0C3_VInt),
         .CP0_Config4 = MIPS_CONFIG4 | (1U << CP0C4_M) | (3 << CP0C4_IE) |
-                       (0xfc << CP0C4_KScrExist),
+                       (1 << CP0C4_AE) | (0xfc << CP0C4_KScrExist),
         .CP0_Config5 = MIPS_CONFIG5 | (1 << CP0C5_XNP) | (1 << CP0C5_VP) |
                        (1 << CP0C5_LLB) | (1 << CP0C5_MRP),
         .CP0_Config5_rw_bitmask = (1 << CP0C5_MSAEn) | (1 << CP0C5_SBRI) |