net: hns3: adjust rss tc mode configure command

For the max rss size of PF may be up to 512, the max queue
number of single tc may be up to 512 too. For the total queue
numbers may be up to 1280, so the queue offset of each tc may
be more than 1024. So adjust the rss tc mode configuration
command, including extend tc size field from 10 bits to 11
bits, and extend tc size field from 3 bits to 4 bits.

Signed-off-by: Guojia Liao <liaoguojia@huawei.com>
Signed-off-by: Huazhong Tan <tanhuazhong@huawei.com>
Signed-off-by: David S. Miller <davem@davemloft.net>

diff --git a/drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_cmd.h b/drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_cmd.h
index a6c306b..edfadb5 100644 (file)
--- a/drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_cmd.h
+++ b/drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_cmd.h
@@ -572,9 +572,11 @@ struct hclge_rss_indirection_table_cmd {
 };
 
 #define HCLGE_RSS_TC_OFFSET_S          0
-#define HCLGE_RSS_TC_OFFSET_M          GENMASK(9, 0)
+#define HCLGE_RSS_TC_OFFSET_M          GENMASK(10, 0)
+#define HCLGE_RSS_TC_SIZE_MSB_B                11
 #define HCLGE_RSS_TC_SIZE_S            12
 #define HCLGE_RSS_TC_SIZE_M            GENMASK(14, 12)
+#define HCLGE_RSS_TC_SIZE_MSB_OFFSET   3
 #define HCLGE_RSS_TC_VALID_B           15
 struct hclge_rss_tc_mode_cmd {
        __le16 rss_tc_mode[HCLGE_MAX_TC_NUM];

diff --git a/drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_main.c b/drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_main.c
index 5de45a9..7a16411 100644 (file)
--- a/drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_main.c
+++ b/drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_main.c
@@ -4335,6 +4335,8 @@ static int hclge_set_rss_tc_mode(struct hclge_dev *hdev, u16 *tc_valid,
                hnae3_set_bit(mode, HCLGE_RSS_TC_VALID_B, (tc_valid[i] & 0x1));
                hnae3_set_field(mode, HCLGE_RSS_TC_SIZE_M,
                                HCLGE_RSS_TC_SIZE_S, tc_size[i]);
+               hnae3_set_bit(mode, HCLGE_RSS_TC_SIZE_MSB_B,
+                             tc_size[i] >> HCLGE_RSS_TC_SIZE_MSB_OFFSET & 0x1);
                hnae3_set_field(mode, HCLGE_RSS_TC_OFFSET_M,
                                HCLGE_RSS_TC_OFFSET_S, tc_offset[i]);