return false;
}
+bool AMDGPUInstructionSelector::selectG_FRAME_INDEX(MachineInstr &I) const {
+ MachineBasicBlock *BB = I.getParent();
+ MachineFunction *MF = BB->getParent();
+ MachineRegisterInfo &MRI = MF->getRegInfo();
+
+ Register DstReg = I.getOperand(0).getReg();
+ const RegisterBank *DstRB = RBI.getRegBank(DstReg, MRI, TRI);
+ const bool IsVGPR = DstRB->getID() == AMDGPU::VGPRRegBankID;
+ I.setDesc(TII.get(IsVGPR ? AMDGPU::V_MOV_B32_e32 : AMDGPU::S_MOV_B32));
+ if (IsVGPR)
+ I.addOperand(*MF, MachineOperand::CreateReg(AMDGPU::EXEC, false, true));
+
+ return RBI.constrainGenericRegister(
+ DstReg, IsVGPR ? AMDGPU::VGPR_32RegClass : AMDGPU::SReg_32RegClass, MRI);
+}
+
bool AMDGPUInstructionSelector::select(MachineInstr &I,
CodeGenCoverage &CoverageInfo) const {
return false;
case TargetOpcode::G_BRCOND:
return selectG_BRCOND(I);
+ case TargetOpcode::G_FRAME_INDEX:
+ return selectG_FRAME_INDEX(I);
}
return false;
}
bool selectG_SELECT(MachineInstr &I) const;
bool selectG_STORE(MachineInstr &I) const;
bool selectG_BRCOND(MachineInstr &I) const;
+ bool selectG_FRAME_INDEX(MachineInstr &I) const;
std::pair<Register, unsigned>
selectVOP3ModsImpl(Register Src, const MachineRegisterInfo &MRI) const;
--- /dev/null
+# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
+# RUN: llc -march=amdgcn -run-pass=instruction-select -verify-machineinstrs %s -o - | FileCheck %s -check-prefix=GCN
+
+---
+
+name: frame_index_s
+legalized: true
+regBankSelected: true
+stack:
+ - { id: 0, size: 4, alignment: 4 }
+
+body: |
+ bb.0:
+ ; GCN-LABEL: name: frame_index_s
+ ; GCN: [[S_MOV_B32_:%[0-9]+]]:sreg_32_xm0 = S_MOV_B32 %stack.0
+ ; GCN: $sgpr0 = COPY [[S_MOV_B32_]]
+ %0:sgpr(p5) = G_FRAME_INDEX %stack.0
+ $sgpr0 = COPY %0
+
+...
+
+---
+
+name: frame_index_v
+legalized: true
+regBankSelected: true
+stack:
+ - { id: 0, size: 4, alignment: 4 }
+
+body: |
+ bb.0:
+ ; GCN-LABEL: name: frame_index_v
+ ; GCN: [[V_MOV_B32_e32_:%[0-9]+]]:vgpr_32 = V_MOV_B32_e32 %stack.0, implicit $exec
+ ; GCN: $vgpr0 = COPY [[V_MOV_B32_e32_]]
+ %0:vgpr(p5) = G_FRAME_INDEX %stack.0
+ $vgpr0 = COPY %0
+
+...