ARM: dts: mvebu: pl310-cache disable double-linefill
authorYan Markman <ymarkman@marvell.com>
Sat, 15 Oct 2016 21:22:32 +0000 (00:22 +0300)
committerGregory CLEMENT <gregory.clement@free-electrons.com>
Thu, 26 Oct 2017 15:41:26 +0000 (17:41 +0200)
Under heavy system stress mvebu SoC using Cortex A9 sporadically
encountered instability issues.

The "double linefill" feature of L2 cache was identified as causing
dependency between read and write which lead to the deadlock.

Especially, it was the cause of deadlock seen under heavy PCIe traffic,
as this dependency violates PCIE overtaking rule.

Fixes: c8f5a878e554 ("ARM: mvebu: use DT properties to fine-tune the L2 configuration")
Cc: stable@vger.kernel.org
Signed-off-by: Yan Markman <ymarkman@marvell.com>
Signed-off-by: Igal Liberman <igall@marvell.com>
Signed-off-by: Nadav Haklai <nadavh@marvell.com>
[gregory.clement@free-electrons.com: reformulate commit log, add Armada
375 and add Fixes tag]
Signed-off-by: Gregory CLEMENT <gregory.clement@free-electrons.com>
arch/arm/boot/dts/armada-375.dtsi
arch/arm/boot/dts/armada-38x.dtsi
arch/arm/boot/dts/armada-39x.dtsi

index 7225c7c..2cb1bcd 100644 (file)
                                reg = <0x8000 0x1000>;
                                cache-unified;
                                cache-level = <2>;
-                               arm,double-linefill-incr = <1>;
+                               arm,double-linefill-incr = <0>;
                                arm,double-linefill-wrap = <0>;
-                               arm,double-linefill = <1>;
+                               arm,double-linefill = <0>;
                                prefetch-data = <1>;
                        };
 
index 4960722..00ff549 100644 (file)
                                reg = <0x8000 0x1000>;
                                cache-unified;
                                cache-level = <2>;
-                               arm,double-linefill-incr = <1>;
+                               arm,double-linefill-incr = <0>;
                                arm,double-linefill-wrap = <0>;
-                               arm,double-linefill = <1>;
+                               arm,double-linefill = <0>;
                                prefetch-data = <1>;
                        };
 
index ea65707..5218bd2 100644 (file)
                                reg = <0x8000 0x1000>;
                                cache-unified;
                                cache-level = <2>;
-                               arm,double-linefill-incr = <1>;
+                               arm,double-linefill-incr = <0>;
                                arm,double-linefill-wrap = <0>;
-                               arm,double-linefill = <1>;
+                               arm,double-linefill = <0>;
                                prefetch-data = <1>;
                        };