dt-bindings: clk: meson: add sm1 periph clock controller bindings
authorNeil Armstrong <narmstrong@baylibre.com>
Mon, 26 Aug 2019 07:25:35 +0000 (09:25 +0200)
committerJerome Brunet <jbrunet@baylibre.com>
Mon, 26 Aug 2019 09:00:15 +0000 (11:00 +0200)
Update the documentation to support clock driver for the Amlogic SM1 SoC
and expose the GP1, DSU and the CPU 1, 2 & 3 clocks.

SM1 clock tree is very close, the main differences are :
- each CPU core can achieve a different frequency, albeit a common PLL
- a similar tree as the clock tree has been added for the DynamIQ Shared
  Unit
- has a new GP1 PLL used for the DynamIQ Shared Unit
- SM1 has additional clocks like for CSI, NanoQ an other components

Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>
Reviewed-by: Kevin Hilman <khilman@baylibre.com>
Signed-off-by: Jerome Brunet <jbrunet@baylibre.com>
Documentation/devicetree/bindings/clock/amlogic,gxbb-clkc.txt
include/dt-bindings/clock/g12a-clkc.h

index 6eaa520..7ccecd5 100644 (file)
@@ -11,6 +11,7 @@ Required Properties:
                "amlogic,axg-clkc" for AXG SoC.
                "amlogic,g12a-clkc" for G12A SoC.
                "amlogic,g12b-clkc" for G12B SoC.
+               "amlogic,sm1-clkc" for SM1 SoC.
 - clocks : list of clock phandle, one for each entry clock-names.
 - clock-names : should contain the following:
   * "xtal": the platform xtal
index 8ccc29a..0837c1a 100644 (file)
 #define CLKID_VDEC_HEVCF                       210
 #define CLKID_TS                               212
 #define CLKID_CPUB_CLK                         224
+#define CLKID_GP1_PLL                          243
+#define CLKID_DSU_CLK                          252
+#define CLKID_CPU1_CLK                         253
+#define CLKID_CPU2_CLK                         254
+#define CLKID_CPU3_CLK                         255
 
 #endif /* __G12A_CLKC_H */