drm/msm/dpu: Wire up DSC mask for active CTL configuration

Active CTLs have to configure what DSC block(s) have to be enabled, and
what DSC block(s) have to be flushed; this value was initialized to zero
resulting in the necessary register writes to never happen (or would
write zero otherwise).  This seems to have gotten lost in the DSC v4->v5
series while refactoring how the combination with merge_3d was handled.

Fixes: 58dca9810749 ("drm/msm/disp/dpu1: Add support for DSC in encoder")
Signed-off-by: Marijn Suijten <marijn.suijten@somainline.org>
Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
Patchwork: https://patchwork.freedesktop.org/patch/515693/
Link: https://lore.kernel.org/r/20221221231943.1961117-2-marijn.suijten@somainline.org
Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>

diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_cmd.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_cmd.c
index ae28b2b93e697fceaba1eb962625a59cae035dc4..35791f93c33d7642a3bf09d187df2ddcf5f934f0 100644 (file)
--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_cmd.c
+++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_cmd.c
@@ -61,6 +61,7 @@ static void _dpu_encoder_phys_cmd_update_intf_cfg(
        intf_cfg.intf_mode_sel = DPU_CTL_MODE_SEL_CMD;
        intf_cfg.stream_sel = cmd_enc->stream_sel;
        intf_cfg.mode_3d = dpu_encoder_helper_get_3d_blend_mode(phys_enc);
+       intf_cfg.dsc = dpu_encoder_helper_get_dsc(phys_enc);
        ctl->ops.setup_intf_cfg(ctl, &intf_cfg);
 
        /* setup which pp blk will connect to this intf */

diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_vid.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_vid.c
index 2c14646661b7746d1bca09be435eae217ece8c59..8f64351fa2e85281f05c76dbd07befc557a01118 100644 (file)
--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_vid.c
+++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_vid.c
@@ -273,6 +273,7 @@ static void dpu_encoder_phys_vid_setup_timing_engine(
        intf_cfg.intf_mode_sel = DPU_CTL_MODE_SEL_VID;
        intf_cfg.stream_sel = 0; /* Don't care value for video mode */
        intf_cfg.mode_3d = dpu_encoder_helper_get_3d_blend_mode(phys_enc);
+       intf_cfg.dsc = dpu_encoder_helper_get_dsc(phys_enc);
        if (phys_enc->hw_pp->merge_3d)
                intf_cfg.merge_3d = phys_enc->hw_pp->merge_3d->idx;